METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE COMPRISING A POROUS SILICON LAYER

Abstract

METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE COMPRISING A POROUS SILICON LAYER The invention relates to a method for manufacturing a multilayer structure, comprising the following steps: providing a support substrate (40) comprising a support layer (41) and a porous silicon layer (42); providing a donor substrate (50) comprising a buried brittle plane (50B) and a surface layer (51); assembling (S3) the support substrate (40) and the donor substrate (50) by bonding, the surface layer (51) of the donor substrate being disposed in contact with the support substrate; separating the surface layer (51) from the donor substrate (50) by fracturing along the buried brittle plane (50B);at least one of the support and donor substrates (40, 50), referred to as the degraded substrate, comprises a degraded portion (60) so as to prevent its adhesion to the other of the support and donor substrates (50, 40) during the assembly step, the degraded portion (60) having an annular or substantially annular shape and being located less than 25 mm from the side of said degraded substrate. Figure to be published with the abbreviation: Figure 3B;

Description

Title of the invention: METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE COMPRISING A POROUS SILICON LAYER TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of semiconductor materials for microelectronic components. The invention relates more particularly to a multilayer structure adapted to high-performance radio frequency applications and comprising an embedded porous silicon layer. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Radio frequency (RF) integrated circuits are widely used in the field of telecommunications (cellular telephony, Wi-Fi, Bluetooth, etc.). These circuits are fabricated on substrates (also called wafers) which primarily serve as a support for their fabrication. The increasing degree of integration and performance of RF circuits leads to an increasingly strong coupling between their performance and the characteristics of the substrate on which they are formed.

[0003] As an example of circuit-substrate coupling, electromagnetic fields from high-frequency signals propagating in RF circuits penetrate deep into the substrate and interact with the charge carriers present there. This results in nonlinear distortion (harmonics) of the signal, unnecessary consumption of some of the signal energy due to insertion loss, and possible interference between circuits.

[0004] Radio frequency (RF) circuits, such as RF signal transmit-receive modules (so-called "front-end" modules), antenna switches and adapters and power amplifiers, can be developed on different types of substrates.

[0005] Fig. 1 shows a multilayer structure 10, derived from the silicon-on-insulator or SOI (for "Silicon On Insulator") multilayer structure and commonly used for the manufacture of RF integrated circuits.

[0006] This multilayer structure 10, called "TR-SOI", comprises successively a high-resistivity silicon support layer 11 (> 1 kQ.cm), a charge-trapping layer 12 (also called a trap-rich layer), a buried oxide layer 13, and an active layer 14 of monocrystalline silicon. The trapping layer 12 prevents the phenomenon of parasitic conduction at the interface between the support layer 11 and the buried oxide layer 13, this phenomenon being usually caused by free electrons that accumulate at the interface under the effect of the fixed positive charges contained in the oxide layer. buried 13. Thanks to the trapping layer 12, electrons are trapped and can no longer flow. The effective resistivity of the support layer 11 is thus increased compared to a multilayer structure without a trapping layer (a structure called "HR-SOI"). The trapping layer 12 can be made of polycrystalline silicon. The traps are located at the grain boundaries of the polycrystalline silicon.

[0007] The combination of a high-resistivity support layer 11 and a trapping layer 12 reduces the circuit-substrate coupling cited in the example and thus greatly improves the RF performance of integrated circuits fabricated from the multilayer structure 10, particularly in terms of linearity and crosstalk. The passive elements (inductors, capacitors, etc.) formed above the active layer 14 also benefit from a better quality factor.

[0008] However, a substrate with a polycrystalline silicon trapping layer exhibits RF performance that degrades as the operating temperature increases. This is because polycrystalline silicon has the disadvantage of undergoing partial recrystallization during high-temperature heat treatment steps, which contributes to reducing the trap density in the layer.

[0009] Figure [Fig. 2] schematically represents another adapted multilayer structure 20 to radio frequency applications and described in document WO2021 / 001066A1.

[0010] The multilayer structure 20 comprises a support layer 21 of silicon (resistivity between 0.5 Q.cm-4 Q.cm), a porous silicon layer 22 disposed on the support layer 21, a dielectric layer 23 (for example of silicon oxide) disposed on the porous silicon layer 22 and an active layer 24 (for example of silicon), also called the surface layer and disposed on the dielectric layer 23.

[0011] The manufacturing process for this multilayer structure 20 includes, in particular: • a step of supplying a silicon support substrate; • a porosification step of part of the support substrate to form the porous silicon layer 22; • a step of depositing the dielectric layer 23 onto the porous silicon layer 22; • a step of supplying a donor substrate comprising a buried fragile plane delimiting the surface layer 24; • a step of assembling the donor substrate onto the dielectric layer, by placing the surface layer 24 in contact with the dielectric layer 23; • a separation step along the buried fragile plane to transfer the surface layer 24 onto the dielectric layer 23; and • one or more heat treatment steps aimed at improving the crystalline quality of the surface layer 24 or its surface condition (roughness, etc.) effectiveness).

[0012] However, it sometimes happens that the surface layer 24 cracks during the separation step and / or that the substrate finally obtained, formed by the multilayer structure 20, bends excessively after the separation step, particularly during the heat treatment steps. Such defects render the substrate unusable for the manufacture of RF circuits. Summary of the invention

[0013] The invention aims to reduce the risk of cracking during the transfer of a surface layer from a donor substrate onto a support substrate comprising a porous silicon layer and to limit the curvature phenomenon of the multilayer structure thus obtained.

[0014] According to the invention, this goal is achieved by providing a method for manufacturing a multilayer structure, comprising the following steps: • provide a support substrate comprising a support layer and a porous silicon layer disposed on the support layer; • provide a donor substrate comprising a first face, a buried fragile plane and a surface layer delimited by the first face and the buried fragile plane; • assemble the support substrate and the donor substrate by gluing, with the surface layer of the donor substrate in contact with the support substrate; and • separate the surface layer of the donor substrate by fracturing along the buried fragile plane. This manufacturing process is remarkable in that at least one of the support and donor substrates, called the degraded substrate, includes a degraded portion so as to prevent its sticking to the other of the support and donor substrates during the assembly step, the degraded portion having an annular or substantially annular shape and being located less than 25 mm from the side of said degraded substrate, preferably less than 5 mm from the side of said degraded substrate.

[0015] In certain embodiments of the manufacturing process, the support substrate further comprises a peripheral portion of non-porous silicon arranged around the porous silicon layer and the degraded portion is located, in the assembly of the support substrate and the donor substrate, vertically at an interface between the peripheral portion of non-porous silicon and the porous silicon layer.

[0016] In another embodiment, the porous silicon layer comprises a central portion having a first substantially constant thickness and a peripheral portion having a second thickness increasing towards the side of the substrate support and the degraded portion is located, in the assembly of the support substrate and the donor substrate, vertically at a transition between the central portion and the peripheral portion of the porous silicon layer.

[0017] In another embodiment, the support substrate further comprises a peripheral portion of non-porous silicon disposed around the porous silicon layer, and the degraded portion consists of a cavity extending into the porous silicon layer and located at a distance of less than 2 mm from an interface between the peripheral portion of non-porous silicon and the porous silicon layer. Advantageously, the cavity is filled with a material having a Young's modulus lower than that of the porous silicon.

[0018] In addition to the characteristics mentioned in the preceding paragraphs, the manufacturing process according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • the degraded portion also extends to the side of said degraded substrate; • the degraded portion is spaced from the side of said degraded substrate and presents a width between 10 µm and 4 mm; • the degraded portion consists of a recessed portion; • the recessed portion belongs to the donor substrate; • The donor substrate supply step includes a light ion implantation step in a first substrate at an implantation depth to form the buried fragile plane, the recessed portion being obtained by forming a cavity with a depth greater than the implantation depth. • the recessed portion belongs to the supporting substrate; • the degraded portion consists of a textured portion exhibiting a surface roughness greater than or equal to 1 nm; • the degraded portion consists of a chamfered portion; • the supporting substrate further comprises a dielectric layer disposed on the porous silicon layer; and • the degraded portion is substantially annular and the degraded substrate includes a so-called non-degraded portion located in the extension of the degraded portion, said non-degraded portion being glued to the other of the support and donor substrates during the assembly step. BRIEF DESCRIPTION OF THE FIGURES

[0019] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which: • the [Fig.1], previously described, represents a multilayer structure according to the prior art, which can be used as a starting substrate for the manufacture of radio frequency integrated circuits; • the [Fig.2], previously described, represents another multilayer structure according to the prior art, also suitable for the manufacture of radio frequency circuits; • Figures 3A to 3C represent a first method of implementing the manufacturing process for a multilayer structure according to the invention; • Figures 4A to 4C represent a second method of implementing the multilayer structure manufacturing process; • Figures 5A to 5C represent a third method of implementing the multilayer structure manufacturing process; • Figures 6A to 6C represent a fourth method of implementing the multilayer structure manufacturing process; • Figures 7A to 7C represent a fifth method of implementing the multilayer structure manufacturing process; • Figures 8A to 8C represent a sixth method of implementing the multilayer structure manufacturing process; • Figures 9A to 9C represent a seventh method of implementing the multilayer structure manufacturing process; • Figures 10A to 10C illustrate one implementation method for the step of supplying the support substrate, including the porous silicon layer; and • [Fig. 11] represents a main face of a substrate comprising a degraded area of ​​roughly annular shape.

[0020] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0021] Figures 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C and 9A-9C illustrate different ways of implementing a manufacturing process for a multilayer structure 30. The multilayer structure 30 is intended to serve as a support for the fabrication of microelectronic components, in particular radio frequency (RF) integrated circuits. It thus constitutes a wafer.

[0022] These figures represent, in cross-section, only a portion of the multilayer structure 30 and the substrates 40, 50 necessary for its manufacture. The multilayer structure 30 and the substrates 40, 50 each comprise two principal faces (commonly referred to as front and back faces), for example, disc-shaped, which extend perpendicularly to the cross-sectional plane of the figures. Furthermore, the structure multilayer 30 and substrates 40, 50 advantageously present a plane of symmetry, symbolized by a mixed line (and passing through the center of the two main faces).

[0023] In a manner common to all embodiments, the manufacturing process of the multilayer structure 30 includes the following steps S1 to S4: • SI: provide a support substrate 40 comprising a support layer 41 and a porous silicon layer 42 disposed on the support layer 41 (see [Fig.3A], [Fig.4A], [Fig.5A], [Fig.6A], [Fig.7A], [Fig.8A] and [Fig.9A]); • S2: provide a donor substrate 50 comprising a first face 50A, a buried fragile plane 50B and a surface layer 51 delimited by the first face 50A and the buried fragile plane 50B (cf. [Fig.3A], [Fig.4A], [Fig.5A], [Fig.6A], [Fig.7A], [Fig.8A] and [Fig.9A]); • S3: assemble the support substrate 40 and the donor substrate 50 by bonding, the surface layer 51 of the donor substrate 50 being in contact with the support substrate 40 (see [Fig.3B], [Fig.4B], [Fig.5B], [Fig.6B], [Fig.7B], [Fig.8B] and [Fig.9B]); and • S4: separate the surface layer 51 from the donor substrate 50 by fracture along the buried fragile plane 50B (cf. [Fig.3C], [Fig.4C], [Fig.5C], [Fig.6C], [Fig.7C], [Fig.8C] and [Fig.9C]).

[0024] The multilayer structure 30 comprising the porous silicon layer 42 is suitable for radio frequency applications aimed at: • low insertion losses (low signal attenuation) and good linearity (low signal distortion causing harmonics); • stability of these performance levels over temperature, particularly within the operating range of RF integrated circuits [-40 °C; 150 °C], and even up to 225 °C; • weak capacitive coupling between RF integrated circuits and support layer 41, typically due to a dielectric permittivity lower than that of silicon.

[0025] The support layer 41 of the substrate 40 is intended to ensure the mechanical strength of the multilayer structure 30, particularly so that it can be handled during the manufacturing stages of the microelectronic components. Its thickness can be between 500 µm and 1 mm. The support layer 41 is preferably made of silicon. Advantageously, the silicon of the support layer 41 has an electrical resistivity between 5 mΩ·cm and 20 Ω·cm, preferably between 0.5 Ω·cm and 4 Ω·cm.

[0026] The porous silicon layer 42 comprises hollow pores preferably with a diameter between 2 nm and 50 nm. Hollow pores are understood to be pores that are not entirely filled by a solid material. The internal walls of the pores are advantageously coated with oxide, for example silicon dioxide (SiO2). The fact that the internal pore walls are coated with oxide indicates a stabilized state of the porous silicon layer 42, in which dangling Si-Hx bonds have been largely replaced by much more stable Si-O-Si bonds. This improves the mechanical stability of the porous silicon layer 42.

[0027] Advantageously, the porosity of the porous silicon layer 42 is between 40% and 70%. This porosity ensures a good balance between the mechanical and electrical properties of the porous silicon layer 42.

[0028] The porous silicon layer 42 advantageously has a resistivity greater than 20 kQ.cm.

[0029] The thickness of the porous silicon layer 42 is preferably between 5 pm and 50 pm. The thickness of the porous silicon layer 42, combined with its morphology (pore diameter, porosity rate), defines the mechanical strength of the porous silicon layer 42.

[0030] With reference to Figures 3A, 4A, 5A, 6A, 7A, 8A, and 9A, step SI of supplying the support substrate 40 may include a substep of porosifying a surface portion of a first silicon substrate. By surface portion (or layer) is meant a portion (layer) extending from a (main) face of the first substrate. The porosified portion of the first substrate constitutes the porous silicon layer 42, while the remaining, non-porized portion of the first substrate constitutes the support layer 4L

[0031] The porosification substep is generally carried out electrochemically or photoelectrochemically. It is based on an anodic dissolution phenomenon in an acidic medium, starting from the silicon of the first substrate. For example, the first substrate is immersed in a hydrofluoric acid (HF) solution. The first substrate is in contact with an anode, and a cathode is placed opposite the face of the first substrate to be porosified.

[0032] There are different configurations of porosification equipment. The most common configurations are called "single cell" and "double cell". In the first case, only one face of the first substrate is in contact with the acidic medium. In the second, both faces of the first substrate are in contact with the acidic medium, this acidic medium comprising either the same solution for both faces or two different solutions.

[0033] In one embodiment, only the surface portion (to be porosified) of the first substrate is made of silicon. The remaining portion of the first substrate, intended to form the support layer 41, may be made of another material (semiconductor or not).

[0034] After the porosification substep, step SI of supplying the support substrate 40 advantageously includes a substep of annealing the porous silicon layer 42 under an oxidizing atmosphere at a temperature between 300 °C and 400 °C, so as to stabilize the porous silicon layer 42. Preferably, the duration of the annealing under an oxidizing atmosphere is between 5 min and 200 min.

[0035] This annealing process makes it possible to replace mainly Si-Hx type pendant bonds, particularly those present on the internal walls of the pores, with much more stable Si-O-Si bonds.

[0036] Advantageously, annealing under an oxidizing atmosphere is followed by annealing under a neutral atmosphere, for example under nitrogen, at a temperature between 400 °C and 450 °C, for example at 420 °C. Annealing under a neutral atmosphere typically lasts between 2 and 16 hours, for example 10 hours.

[0037] Annealing under a neutral atmosphere prevents outgassing during subsequent heat treatments applied to the multilayer structure 30, as this outgassing could degrade the quality of said structure. Furthermore, annealing under a neutral atmosphere tends to stabilize the curvature of the substrate 40 with the porous silicon layer 42, thus limiting the curvature of the multilayer structure 30 after these heat treatments.

[0038] Finally, the SI step of supplying the support substrate 40 may include a substep of forming a dielectric layer 43 on the porous silicon layer 42. The dielectric layer 43 is an electrically insulating layer. It may be made of a nitride, for example silicon nitride (Si3N4), or an oxide such as silicon dioxide (SiO2) or aluminum oxide (Al2O3). Its thickness may be between 200 nm and 2 pm.

[0039] The dielectric layer 43 can be formed by a chemical vapor deposition technique, for example by low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDP-CVD).

[0040] With further reference to Figures 3A, 4A, 5A, 6A, 7A, 8A and 9A, at least one so-called "active" portion of the surface layer 51 of the donor substrate 50 is formed of a material selected from silicon, germanium, silicon carbide, piezoelectric materials (e.g., LiNbO3, LiTaO3...) and binary, ternary or quaternary alloys of type IV-IV (e.g., SiGe), III-V or ILVI semiconductor materials. The surface layer 51 is intended to be transferred onto the support substrate 40 and its active portion is intended to receive active components, such as transistors, during the fabrication of microelectronic components from the multilayer structure 30. The thickness of the active portion is preferably between 50 nm and 1.5 pm.

[0041] The surface layer 51 can be formed by a thin film (50 nm - 1.5 pm) of The piezoelectric or semiconductor material (silicon, germanium, silicon carbide, type IV-IV, III-V or II-VI alloys, etc.), intrinsic or doped (see Figs. 3A, 4A, 5A, 6A and 9A), is entirely designed to receive the active components. This is also referred to as the active layer.

[0042] Alternatively, the surface layer 51 can be formed from a stack of several sublayers (see Figs. 7A and 8A), for example a stack comprising an active sublayer 511 of piezoelectric or semiconducting material (whose thickness can be between 50 nm and 1.5 pm) and a dielectric sublayer 512 disposed on the active sublayer 511 (and whose thickness can be between 50 nm and 500 nm).

[0043] Step S2 of supplying the donor substrate 50 preferably includes a substep of forming the buried brittle plane 50B in a second substrate. Preferably, the second substrate is made of a material selected from silicon, germanium, silicon carbide, piezoelectric materials (e.g. LiNbO3, LiTaO3...) and binary, ternary or quaternary alloys of type IV-IV (e.g. SiGe), III-V or II-VI semiconductor materials.

[0044] The buried brittle plane 50B is advantageously formed by implanting light ions through a first face of the second substrate. The ions are implanted in the second substrate at a given implantation depth, measured from the first face of the second substrate. The implantation depth can be between 50 nm and 1.5 pm, for example, 400 nm. Light ions here refer to ions of chemical species having an atomic number less than or equal to 5. The light ions are preferably hydrogen or helium ions, as these ions are favorable to the formation of microcavities around the implantation depth, giving rise to the buried brittle plane 50B, as described in the manufacturing process for SOI substrates known as Smart Cut™ (registered trademark).

[0045] Before or after the implantation substep, the S2 step of supplying the donor substrate 50 can also include the deposition of a dielectric sublayer 512 (see Figs. 7A and 8A) on the first face of the second substrate (this dielectric sublayer 512 forming part of the surface layer 51).

[0046] The steps S3 and S4 described below relate to the transfer of the surface layer 51 of the donor substrate 50 onto the support substrate 40.

[0047] Step S3 of assembling the support substrate 40 and the donor substrate 50 consists of gluing the donor substrate 50 on the side of its first face 50A onto the support substrate 40. This assembly step S3 is also called the step of transferring the donor substrate 50 onto the support substrate 40.

[0048] In a preferred embodiment of the assembly step S3 illustrated by Figures 3B, 4B, 5B, 6B and 9B, the surface layer 51 of the donor substrate 50 is contact with the dielectric layer 43 of the support substrate 40.

[0049] In an embodiment illustrated by [Fig.7B], the surface layer 51 comprises on its surface a dielectric sublayer 512 which is in contact with the dielectric layer 43 of the support substrate 40. The dielectric sublayer 512 of the donor substrate 50 and the dielectric layer 43 of the support substrate 40 are advantageously formed of the same dielectric material, preferably an oxide (e.g. SiO2).

[0050] Finally, in an embodiment represented by [Fig.8B], the support substrate 40 is devoid of a dielectric layer 43 and the surface layer 51 includes on the surface a dielectric sublayer 512 which is in contact with the porous silicon layer 42 of the support substrate 40.

[0051] The assembly of the support and donor substrates 40, 50 can be accomplished by any known bonding technique, preferably by direct molecular adhesion bonding. This technique will not be described in detail here. However, it should be noted that, prior to bonding, the support substrate 40 and the donor substrate 50 preferably underwent surface cleaning and / or activation sequences to ensure the quality of the bonding interface in terms of defects and bonding energy. In addition, the support substrate 40 and the donor substrate 50 preferably underwent a polishing step (for example, by chemical planarization or CMP) of their bonding surface to obtain a surface roughness strictly less than 0.7 nm. This roughness value, as well as all those given subsequently, are expressed as root mean square values.The root mean square roughness (denoted Rq) is determined by a statistical analysis of an atomic force microscope image, taking as a sample a surface of 1x1 pm2.

[0052] Step S4, which involves separating the surface layer 51 by fracturing along the buried brittle plane 50B, allows the surface layer 51 to be detached from the donor substrate 50, thus obtaining the multilayer structure 30 on the one hand, and the remaining donor substrate 50 on the other. The remaining donor substrate 50 can be reused to transfer other surface layers during subsequent iterations of the manufacturing process.

[0053] Preferably, the S4 step of separating the surface layer 51 includes a heat treatment. For a silicon surface layer 51 (or an active sublayer 511), this heat treatment is carried out at a temperature between 200 °C and 500 °C, preferably between 350 °C and 450 °C. Such a heat treatment is suitable for increasing the embrittlement level of the buried brittle plane 50B, a phenomenon at the heart of the Smart Cut™ process.

[0054] A temperature of around 400 °C is advantageous because the assembly is subjected to less mechanical stress due to the different coefficients of expansion of the materials constituting the support substrate 40 and the donor substrate 50. Indeed, Excessive stresses are likely to affect the integrity of the porous silicon layer 42.

[0055] After the S4 separation step, the manufacturing process of the multilayer structure 30 may include one or more heat treatment steps to improve the crystalline quality and / or the surface condition (roughness, defect) of the surface layer 51 (so-called finishing anneals of the surface layer 51) or to consolidate the bonding interface (so-called consolidation anneal of the interface).

[0056] In the embodiments shown in Figures 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, and 8A-8C, the support substrate 40 further comprises a peripheral portion of non-porous silicon 44 (or bulk silicon) arranged around the porous silicon layer 42. In other words, the porous silicon layer 42 does not extend to the side of the support substrate 40. This is particularly the case when a "double-cell" type porosification device has been used to form the porous silicon layer 42 (a peripheral seal rests against the face of the first substrate in contact with the acidic medium). The peripheral portion of non-porous silicon 44 has a width L1 that varies between 1 mm and 5 mm (for example, depending on the device used). The width of a portion of a substrate here refers to the dimension of that portion measured along a radius of said substrate. The thickness of the peripheral portion 44 is equal to the thickness of the porous silicon layer 42.

[0057] The peripheral portion of non-porous silicon 44 tends to reduce the curvature of the multilayer structure 30 during subsequent heat treatment steps (finishing steps of the surface layer 51 or component manufacturing). Conversely, it is responsible for arc-shaped cracks that can appear in the surface layer 51 during the separation step S4.

[0058] The separation of the surface layer 51 results from the propagation of at least one fracture wave in the buried brittle plane 50B. The fracture wave originates at a point on the buried brittle plane 50B, generally on the edge (typically circular), and propagates in all directions of the buried brittle plane 50B, in the case presented here at different speeds due to the heterogeneous composition of the underlying support substrate 40. More specifically, the fracture wave propagates much faster over non-porous silicon than over porous silicon, which absorbs more of the fracture energy. This is the origin of the observed cracks.

[0059] In order to drastically reduce the risk of cracking of the surface layer 51 during the separation step S4, at least one of the support and donor substrates 40, 50 includes a degraded portion 60, configured not to be bonded to the other support and donor substrate 40, 50 during the assembly step S3. Thus, the bonding of the support and donor substrates 40, 50 is only partial (i.e., it occurs outside the degraded portion(s) 60). The substrate comprising the degraded portion 60 is referred to hereafter as degraded substrate.

[0060] This local lack of bonding between the supporting substrate 40 and the donor substrate 50 results in cracking not occurring (in the buried weak plane 50B) opposite the degraded portion 60 due to the absence of a stiffener. Consequently, the surface layer 51 of the donor substrate 50 is not transferred to the supporting substrate 40 opposite the degraded portion 60.

[0061] The degraded portion 60 has an annular or substantially annular shape. The expression "substantially annular" refers to a segment of a ring, this segment having a circumference (or outer perimeter) greater than or equal to 90% of the circumference of the (whole) ring. It can also refer to several segments of the same ring whose total circumference is greater than or equal to 90% of the circumference of the ring.

[0062] In the first embodiment shown in Figures 3A-3C, the degraded substrate is the donor substrate 50. In other words, the degraded portion 60 belongs to the donor substrate 50. In the assembly of substrates 40 and 50, it is located vertically at the interface between the porous silicon layer 42 and the peripheral non-porous silicon portion 44 (in other words, the vertical projection of the interface passes through the degraded portion 60). Furthermore, it extends to the side of the degraded substrate (here, the donor substrate 50).

[0063] The degraded portion 60 of Figures 3A-3C is formed by a portion recessed from the first face 50A of the donor substrate 50. This recessed portion, also called the hollowed-out portion, can be obtained by forming a cavity (annular or substantially annular) in the donor substrate 50 from the first face 50A (see [Fig. 3A]). The depth P of this cavity, measured from the first face 50A, is greater than the topology of the edge of the supporting substrate 40 (to avoid the risk of sticking to the supporting substrate). Furthermore, it is advantageously greater than the implantation depth of the light ions to form the buried fragile plane 50B. It is preferably between 200 nm and 10 pm, for example, 6 pm. The cavity can be obtained by etching or micromilling.

[0064] One advantage of this first embodiment is that the surface layer 51 transferred onto the support substrate 40 then has a sharp outline (see [Fig. 3C]). Furthermore, when the depth P of the cavity is greater than or equal to twice the implantation depth, the donor substrate 50 can be reused without needing to reform the cavity.

[0065] In the second embodiment shown in Figures 4A-4C, the degraded substrate is, on the contrary, the support substrate 40. In other words, the degraded portion 60 belongs to the support substrate 40. As before, it extends from the side of the degraded substrate (here the support substrate 40) until it reaches or exceed the vertical projection of the interface between the porous silicon layer 42 and the peripheral portion 44.

[0066] The degraded portion 60 of Figures 4A-4C consists of a textured portion of the dielectric layer 43, this portion being textured to have a surface roughness greater than or equal to 1 nm. Indeed, excessive roughness prevents the bonding of the support substrate 40 and the donor substrate 50. Apart from the degraded portion 60, the surface roughness of the support and donor substrates 40, 50 is therefore strictly less than 1 nm.

[0067] The textured portion can be obtained by etching the dielectric layer 43, by chemical treatment, by plasma treatment, by ion beam bombardment, by nanosecond laser annealing or by application (punching) of a textured ring to create defects.

[0068] In a first embodiment variant (not shown in the figures), the degraded portion 60 is a textured portion (Rq > 1 nm) belonging to the donor substrate 50, and more particularly to the surface layer 51.

[0069] In a second embodiment variant (also not shown in the figures), the degraded portion 60 is a recessed portion belonging to the support substrate 40, and more particularly to the dielectric layer 43. The depth of the corresponding cavity is preferably strictly less than the thickness of the dielectric layer 43.

[0070] Thus, in these first two embodiments and their variants, the degraded portion 60 is arranged so as to obtain a fracture wave that propagates over a homogeneous medium comprising the porous silicon layer 42. There are then no cracks. The width L2 of the degraded portion 60 is strictly greater than the width L1 of the peripheral portion 44, and preferably between 2 mm and 6 mm.

[0071] In the third embodiment shown in Figures 5A-5C, the degraded portion 60 belongs to the support substrate 40. It is also located (in the assembly of substrates 40 and 50) vertically above the interface between the porous silicon layer 42 and the peripheral portion 44. However, unlike the second embodiment (Figs. 4A-4C), it does not extend to the side of the support substrate 40. In other words, it is spaced from the side of the support substrate 40. It is located at a distance d of less than 5 mm from the side of the support substrate 40.

[0072] The degraded portion 60 can be formed by a recessed portion of the dielectric layer 43, as shown in Figures 5A-5C (and as in the second embodiment variant), or by a textured portion of high roughness of the dielectric layer 43 (as in the embodiment of Figures 4A-4C).

[0073] In the fourth embodiment represented by Figures 6A-6C, the The degraded portion 60 belongs to the donor substrate 50. It is also located vertically at the interface between the porous silicon layer 42 and the peripheral portion 44. However, and unlike the first embodiment (Figs. 3A-3C), it does not extend to the side of the donor substrate 50. It is nevertheless located at a distance d of less than 5 mm from the side of the donor substrate 50. The degraded portion 60 can be formed by a portion set back from the first face 50A of the donor substrate 50, as shown in Figures 6A-6C (and as in the embodiment of Figures 3A-3C), or by a textured portion with high roughness of the surface layer 51 (as in the first embodiment variant).

[0074] In these third and fourth embodiments, the degraded portion 60 is arranged to produce two fracture waves, each propagating in a specific region (peripheral or central) of the buried brittle plane 50B, above a homogeneous medium (comprising either the porous silicon layer 42 or the peripheral portion 44). Therefore, there are only two fracture fronts, which cannot meet, since the fracture waves do not propagate opposite the degraded portion 60 (absence of bonding of the surface layer 51). The width L3 of the degraded portion 60 is preferably between 10 µm and 4 mm.

[0075] The third and fourth embodiments of the manufacturing process also make it possible to obtain an (annular) portion of the active layer at the periphery of the multilayer structure 30 (unlike the previous embodiments), which can prove useful for the integration of microelectronic components.

[0076] In the fifth embodiment shown in Figures 7A-7C, the degraded portion 60 consists of a cavity (annular or substantially annular) extending (from the bonding face of the support substrate 40) into the porous silicon layer 42, at a distance d of less than 7 mm from the side of the support substrate 40 and at a distance d of less than 2 mm from the interface between the porous silicon layer 42 and the peripheral portion 44. The cavity 60 can be formed by etching, micromilling, or nanosecond laser annealing. Its width L4 is preferably between 10 pm and 1 mm.

[0077] Advantageously, the cavity 60 extends over the entire thickness of the porous silicon layer 42.

[0078] This cavity 60 allows the porous silicon layer 42 to deform (or rearrange) at least partly along the side rather than vertically, thus avoiding outgrowths or inhomogeneities which can impair the quality of the bonding (and consequently create non-transferred areas).

[0079] A dielectric material, typically that forming the dielectric layer 43, can The bottom and side walls of cavity 60 are coated, but not completely filled. Furthermore, cavity 60 can be (with or without a dielectric coating on the bottom and side walls) partially or completely filled with a fracture wave-absorbing material, thus forming an absorbing material chamber. The absorbing material has a Young's modulus lower than that of porous silicon (i.e., less than 20 GPa).

[0080] Again, the cavity 60 or the absorbing box makes it possible to distinguish two distinct zones of propagation of fracture waves, above a homogeneous or practically homogeneous medium, which prevents the appearance of cracks.

[0081] In the sixth embodiment shown in Figures 8A-8C, the degraded portion 60 is produced on one or both of the substrates 40-50 (on both in the example of Figures 8A-8C) by optimizing the chamfered edges of the wafer. This optimization is, for example, achieved by edge-grinding so that the chamfered edge portion of the wafer (constituting the degraded portion 60) extends to the porous silicon layer 42 (before assembly when it belongs to the support substrate 40 and after assembly when it belongs to the donor substrate 50) so that there can be no bonding beyond the porous silicon layer 42.

[0082] In the seventh embodiment shown in Figures 9A-9C, the porous silicon layer 42 comprises a central portion 421 having a substantially constant thickness e1 and a peripheral portion 422 of increasing thickness e2 towards the side of the support substrate 40. By substantially constant, it is understood that the thickness e1 of the central portion 421 does not vary by more than 5%. In contrast, the thickness e2 of the peripheral portion 422 can vary by more than 30% between the interface with the central portion 421 and the side of the support substrate 40.

[0083] Such a porous silicon layer 42 is obtained in particular when a "single-cell" type porosification device is used (as a reminder, one entire face of the first substrate is exposed to the acidic medium). The peripheral portion 422 of increasing thickness has a width Ll' which can vary between 2 mm and 25 mm.

[0084] In this scenario, the multilayer structure 30 is practically unaffected by the cracking phenomenon, as the fracture wave propagates over a medium (of composition) that is generally homogeneous. On the other hand, the inhomogeneity in thickness of the porous silicon at the wafer edge is responsible for an increase in the curvature of the multilayer structure 30 during annealing, particularly during the consolidation annealing of the bond interface, which can reach 1000 °C (the multilayer structure 30 can exhibit a deflection of 600 pm after annealing).

[0085] To limit or cancel the effect of the thickness gradient, and thus reduce the curvature of the multilayer structure 30, a degraded portion 60 is provided in one of the less of the support and donor substrates 40, 50. The degraded portion 60 is located, in the assembly of the support substrate 40 and the donor substrate 50, vertically at the transition between the central portion 421 and the peripheral portion 422 of the porous silicon layer 42.

[0086] The degraded portion 60 can be a recessed portion, a textured portion (with a roughness greater than or equal to 1 nm; see Figs. 9A-9C), a cavity (filled or not with absorbent material), or a chamfered portion of the plate edge, as described previously. It can extend to the side of the degraded substrate (L2 > L1'). Its width L2 is then advantageously between 3 mm and 26 mm.

[0087] The recessed portion in the dielectric layer 43 is the most favorable solution, since the dielectric layer 43 also plays a role in the curvature of the multilayer structure 30.

[0088] More generally, the degraded portion 60 is located less than 25 mm from the side of the degraded substrate, and preferably less than 7 mm in the embodiment shown in Figures 7A-7C and less than 5 mm in the embodiments shown in Figures 3A-3C, 4A-4C, 5A-5C, 6A-6C and 8A-8C. Thus, the risks of cracking of the surface layer 51 and / or excessive curvature of the multilayer structure 30 caused by inhomogeneities at the edge of the assembly can be reduced.

[0089] Figures 10A-10C represent an implementation of the step of supplying the support substrate 40, allowing the structure comprising a peripheral portion of non-porous silicon 44 to be recreated (see Figs. 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C), even though a "single cell" type porosification equipment is used to form the porous silicon layer 42.

[0090] In a first substep SI 1 illustrated by [Fig. 1OA], a first silicon substrate 90 is hollowed out (for example by etching) so as to form a central cavity 91 delimited laterally by a ring 92 (made of silicon). The ring 92 constitutes a peripheral portion of the first substrate 90.

[0091] The thickness e3 of this ring 92 (equal to the etching depth) is greater than or equal to the maximum thickness (e2) of the porous silicon layer to be formed (i.e., the thickness at the flank). Thus, during the second substep S12 of porosification using a "single-cell" type porosification device (see [Fig. 1OB]), the porous silicon layer 42' formed does not extend over the entire ring 92. A buried portion 921 of the ring 92 is left undisturbed. Preferably, the width L5 of the ring 92 is such that the peripheral portion of increasing thickness of the porous silicon layer 42' lies entirely within the ring 92.

[0092] Finally, in a third substep S23 (see [Fig. 1OC]), the ring 92 is completely removed so as to obtain a flat surface with the central portion (of thickness el substantially constant) of the porous silicon layer 42'.

[0093] The delimitation of a ring 92 at the periphery of the first substrate 90 during the first sub-step SI 1 therefore makes it possible to protect an underlying silicon portion from the porosification process (forming said peripheral portion 44 of the support substrate 40), this silicon portion being found to be arranged around the portion of porous silicon finally retained (forming said porous silicon layer 42 of the support substrate 40).

[0094] This particular implementation method of the SI step of supplying the support substrate 40 also prevents the porous silicon from spreading on the side of the multi-layer structure 30, which can be a source of fragility or contamination (e.g. infiltration of etching, cleaning solutions... used during the manufacture of the components).

[0095] As previously stated, the degraded portion 60 of the supporting substrate 40 or the donor substrate 50 may have a shape that is not completely annular (“substantially annular”). In other words, a portion of the supporting substrate 40 or the donor substrate 50 may be left intact in order to create a fracture initiation zone at the edge.

[0096] Figure 11 shows, by way of example, the bonding face of the substrate support 40 of Figure 4A. The dashed circle represents the interface between the porous silicon layer 42, in the center of the substrate, and the peripheral non-porous silicon portion 44. An undegraded portion 70 (here of the dielectric layer 43) is located in the extension of the degraded portion 60 in a ring segment, so that it completes the ring. By "undegraded portion" is meant a portion that is bonded to the other of the substrates during the assembly step S3.

[0097] The non-degraded portion 70 is advantageously arranged to encompass a notch 80 (commonly called a "notch") of the support substrate 40 (or of the donor substrate 50), as shown in [Fig. 11].

[0098] With reference to Figures 3C, 4C, 5C, 6C, 7C, 8C and 9C, the multilayer structure 30 thus comprises the support layer 41, the porous silicon layer 42 disposed on the support layer 41, a dielectric layer 43, 512 (dielectric layer 43 and / or dielectric sublayer 512) disposed on the porous silicon layer 42 and an active layer 51, 511 (surface / active layer 51 or active sublayer 511) disposed on the dielectric layer 43, 512.

[0099] In the case of an oxide, the dielectric layer 43, 512 can also be called a buried oxide layer or BOX (for "buried oxide layer" in English).

[0100] A particular feature of the multilayer structure 30 is that the active layer 51,511 includes a recess 510 of annular or substantially annular shape. The recess 510 extends to the dielectric layer 43, that is to say, over the entire the thickness of the active layer 51,511. Thus, the active layer 51,511 does not completely cover the support layer 41.

[0101] Such a recess in the active layer 51,511 near the flank of the multi-layer structure 30 is far less detrimental than excessive curvature or cracks for the manufacture of microelectronic components (these cracks generally extending much further towards the center of the wafer).

Claims

Demands

1. Method for manufacturing a multilayer structure (30), comprising the following steps: - providing (S1) a support substrate (40) comprising a support layer (41) and a porous silicon layer (42) disposed on the support layer; - providing (S2) a donor substrate (50) comprising a first face (50A), a buried fragile plane (50B) and a surface layer (51) delimited by the first face and the buried fragile plane; - assembling (S3) the support substrate (40) and the donor substrate (50) by bonding, the surface layer (51) of the donor substrate being disposed in contact with the support substrate; - separating (S4) the surface layer (51) from the donor substrate (50) by fracturing along the buried fragile plane (50B);process characterized in that at least one of the support and donor substrates (40, 50), referred to as the degraded substrate, comprises a degraded portion (60) so as to prevent its adhesion to the other of the support and donor substrates (50, 40) during the assembly step, the degraded portion (60) having an annular or substantially annular shape and being located less than 25 mm from the side of said degraded substrate.;

2. A method according to claim 1, wherein the support substrate (40) further comprises a peripheral portion of non-porous silicon (44) disposed around the porous silicon layer (42) and wherein the degraded portion (60) is located, in the assembly of the support substrate (40) and the donor substrate (50), vertically at an interface between the peripheral portion of non-porous silicon (44) and the porous silicon layer (42).

3. A method according to claim 1, wherein the porous silicon layer (42) comprises a central portion (421) having a substantially constant first thickness (e1) and a peripheral portion (422) having a second thickness (e2) increasing towards the flank of the support substrate (40), and wherein the degraded portion (60) is located, in the assembly of the support substrate (40) and the donor substrate (50), vertically at a transition between the central portion (421) and the portion peripheral (422) of the porous silicon layer (42).

4. A method according to any one of claims 1 to 3, wherein the degraded portion (60) further extends to the flank of said degraded substrate.

5. A method according to any one of claims 1 to 3, wherein the degraded portion (60) is spaced from the flank of said degraded substrate and has a width (L3) between 10 pm and 4 mm.

6. A method according to any one of claims 1 to 5, wherein the degraded portion (60) is constituted by a recessed portion.

7. Method according to claim 6, wherein the recessed portion belongs to the donor substrate (50).

8. A method according to claim 7, wherein the step (S2) of supplying the donor substrate (50) includes a substep of implanting light ions into a first substrate at an implantation depth to form the buried brittle plane (50B), the recessed portion being obtained by forming a cavity of a depth (P) greater than the implantation depth.

9. A method according to any one of claims 1 to 5, wherein the degraded portion (60) is constituted by a textured portion having a surface roughness greater than or equal to 1 nm.

10. A method according to claim 1, wherein the support substrate (40) further comprises a peripheral portion of non-porous silicon (44) disposed around the porous silicon layer (42) and wherein the degraded portion (60) consists of a cavity extending into the porous silicon layer (42) and located at a distance (d') less than 2 mm from an interface between the peripheral portion of non-porous silicon (44) and the porous silicon layer (42).

11. A method according to claim 10, wherein the cavity is filled with a material having a Young's modulus lower than that of porous silicon.

12. A method according to any one of claims 1 to 11, wherein the support substrate (40) further comprises a dielectric layer (43) disposed on the porous silicon layer (42).

13. A method according to any one of claims 1 to 12, wherein the degraded portion (60) is substantially annular and wherein said degraded substrate comprises a so-called non-degraded portion (70) situated in the extension of the degraded portion (60), said non-degraded portion (70) being bonded to the other of the support and donor substrates (50, 40) during the assembly step (S3).

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