HEMT transistor

Abstract

HEMT Transistor The present description relates to a method for forming a HEMT transistor (41) comprising the following successive steps: a) providing a stack comprising a channel semiconductor layer (23), a barrier semiconductor layer (13) on and in contact with the channel semiconductor layer (23) and a gate semiconductor layer (15) arranged on and in contact with the barrier semiconductor layer (13), the gate semiconductor layer (15) comprising P-type doping elements; and b) compensating the P-type doping with oxygen atoms, in an upper part (151) of the gate semiconductor layer (15), by annealing under oxygen, so as to define a PN junction at the interface between the upper part (151) and a central part (153) of the gate semiconductor layer (15). Figure for abstract: Fig. 2

Description

Title of the invention: HEMT transistor Technical field

[0001] The present description relates generally to the field of transistors and more particularly to the field of high electron mobility transistors also called HEMT (from the English "High Electron Mobility Transistor"). Prior art

[0002] HEMT transistors are based on a heterojunction on the surface of which a two-dimensional gas of electrons called 2DEG is formed.

[0003] There is a need for improvement of HEMT transistors and their manufacturing processes. Summary of the invention

[0004] For this, one embodiment provides a method for forming a HEMT transistor comprising the following successive steps: (a) providing a stack comprising a channel semiconductor layer, a barrier semiconductor layer on and in contact with the channel semiconductor layer and a gate semiconductor layer disposed on and in contact with the barrier semiconductor layer, the gate semiconductor layer comprising P-type dopant elements; and b) compensating for the P-type doping with oxygen atoms, in an upper part of the gate semiconductor layer, by annealing under oxygen, so as to define a PN junction at the interface between the upper part and a central part of the gate semiconductor layer.

[0005] According to one embodiment, the method comprises a step c) of etching the gate semiconductor layer.

[0006] According to one embodiment, the etching of step c) is carried out after step b).

[0007] According to one embodiment: - the etching of step c) is partial, part of the thickness of the semiconductor gate layer remaining at the end of the etching step; and - the etching of step c) is followed by another step of compensating for the P-type doping by oxygen atoms in a peripheral part of the etched semiconductor layer and another etching step making it possible to remove what remains of the gate semiconductor layer at the end of the etching step of step c).

[0008] Another embodiment provides a HEMT transistor comprising: - a channel semiconductor layer; - a barrier semiconductor layer on and in contact with the semiconductor layer- canal ductor; and - a semiconductor gate disposed on and in contact with a first face of the barrier semiconductor layer, opposite the channel semiconductor layer, wherein the gate comprises an upper portion and a central portion, the upper portion and the central portion comprising P-type doping elements, and the upper portion comprising oxygen atoms compensating for the P-type doping so as to define a PN junction at the interface between the central portion and the upper portion.

[0009] According to one embodiment, the grid comprises a peripheral part comprising P-type doping elements and comprising oxygen atoms compensating for the P-type doping.

[0010] According to one embodiment, the transistor comprises a passivation layer extending over the first face of the first semiconductor layer and the sides of the gate and a peripheral portion of a face of the gate opposite the first semiconductor layer.

[0011] According to one embodiment, the first passivation layer is made of alumina.

[0012] According to one embodiment, the first semiconductor layer is based on gallium nitride.

[0013] According to one embodiment, the first semiconductor layer is made of aluminum-gallium nitride.

[0014] According to one embodiment, the first semiconductor layer comprises a decreasing percentage of aluminum from its first face.

[0015] According to one embodiment, the transistor comprises a second semiconductor layer in contact with a second face of the first semiconductor layer, opposite the first face.

[0016] According to one embodiment, the second semiconductor layer is made of gallium nitride.

[0017] According to one embodiment, the semiconductor gate is made of gallium nitride.

[0018] Another embodiment provides a conversion or adaptation circuit of power comprising at least one transistor as described. Brief description of the drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [Fig.l] is a partial, schematic sectional view of an example of a HEMT transistor;

[0021] [Fig.2] is a partial and schematic sectional view of a HEMT transistor according to a first embodiment;

[0022] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D], [Fig.3E] and [Fig.3F] are sectional views illustrating steps of an example of a method of manufacturing the HEMT transistor illustrated in [Fig.2];

[0023] [Fig.4] is a partial and schematic sectional view of a HEMT transistor according to a second embodiment; and

[0024] [Fig.5] is a partial and schematic sectional view of a HEMT transistor according to a third embodiment. Description of the embodiments

[0025] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the applications that the HEMT transistors described may have are not detailed, the embodiments being compatible with the usual applications of HEMT transistors. Of particular interest here is the field of so-called power HEMT transistors, capable of withstanding relatively high voltages in the off state, for example voltages of the order of 100 to 650 volts. The transistors described may, for example, be used in various power conversion or adaptation circuits, for example in industrial equipment, display or lighting devices, telecommunications equipment, automotive devices, etc.

[0027] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0028] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0029] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0030] [Fig.l] is a partial, schematic, sectional view of an example of a HEMT transistor 11.

[0031] The HEMT transistor 11 comprises a first semiconductor layer 13 called barrier layer, arranged on a second conductive layer 23 called channel layer. The semiconductor layer 23 is for example in contact, by its lower face, with the upper face of the conductive layer 23. By way of example, the stack comprising the semiconductor layer 13 and the semiconductor layer 23 rests on a substrate 21. The semiconductor layer 23 is for example in contact, by its lower face, with the upper face of the substrate 21. The interface between the semiconductor layer 13 and the semiconductor layer 23 defines a heterojunction on the surface of which a two-dimensional electron gas 2DEG also called electron channel is formed.

[0032] The semiconductor layers 13 and 23 are for example made of III-V type semiconductor materials, for example based on gallium nitride (GaN). The semiconductor layer 13 is for example made of aluminum-gallium nitride (AlGaN). The semiconductor layer 13 is for example made of gallium nitride (GaN).

[0033] By way of example, the substrate 21 is made of a semiconductor material. The substrate 21 is, for example, made of silicon, or silicon carbide. Alternatively, the substrate 21 is made of aluminum nitride. The substrate 21 comprises, for example, on its upper face, a buffer layer, not detailed in the figures, for example made of gallium nitride. The buffer layer is, for example, in contact, by its upper face, with the lower face of the semiconductor layer 23.

[0034] The HEMT transistor 11 comprises a gate 15 on the upper face of the semiconductor layer 13. The gate 15 is for example in contact, by its lower face, with the upper face of the semiconductor layer 13.

[0035] The gate 15 is for example made of a semiconductor material, for example a III-V type semiconductor material, for example gallium nitride. The gate 15 comprises P-type doping elements, for example magnesium atoms. By way of example, the gate 15 has a thickness of between 20 nm and 200 nm, for example between 80 nm and 120 nm, for example of the order of 100 nm.

[0036] By way of example, the HEMT transistor 11 further comprises a source contact metallization 29 and a drain contact metallization 31. By way of example, the contact metallizations 29 and 31 are based on titanium, titanium nitride and / or an alloy of aluminum and copper. The source 29 and drain 31 contact metallizations each define, for example, an ohmic contact with the semiconductor layer 13. The contact metallizations 29 and 31 are, for example, located on and in contact with the semiconductor layer 13, on either side of the gate 15.

[0037] The HEMT transistor 11 further comprises a passivation layer 17 covering the sides of the gate, a part of the upper face of the gate 15 and extending over a part of the upper face of the semiconductor layer 13 not covered by the gate 15. By way of example, the passivation layer 17 is in contact, by its face lower, with the upper face of the semiconductor layer 13. The passivation layer 17 is for example also in contact with the sides of the gate 15. In the embodiment of [Fig.l], the passivation layer 17 extends laterally between the source 29 and drain 31 contact metallizations.

[0038] The passivation layer 17 has for example a thickness of between 2 nm and 20 nm, for example of between 2 nm and 10 nm, for example of the order of 5 nm. The passivation layer 17 is for example made of a dielectric material, for example alumina (A12O3), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum nitride (AIN) or hafnium oxide (HfO2).

[0039] The grid 15 is for example surmounted by a grid contact metallization 27.

[0040] By way of example, the gate contact metallization 27 is in contact, by its lower face, with the upper face of the gate 15. The gate contact metallization 27 then extends through the layer 17 which only covers the upper face of the gate 15 on its periphery.

[0041] By way of example, the gate contact metallization 27 is based on titanium nitride and / or titanium, and / or tantalum, and / or an alloy of tungsten and tantalum and / or an alloy of tungsten and titanium and / or an alloy of aluminum and copper.

[0042] In this example, the metallization 27 defines a Schottky contact with the semiconductor gate 15. The semiconductor gate 15 and the metallization 27 define a Schottky diode whose anode corresponds to the semiconductor gate 15 and whose cathode corresponds to the metallization 27.

[0043] The HEMT transistor 11 comprises, for example, several levels of insulating layers in, and for example on, which metallizations are formed.

[0044] By way of example, the HEMT transistor 11 comprises an insulating layer 33 on and in contact with the upper face of the passivation layer 17. By way of example, the insulating layer 33 covers the entire surface of the passivation layer 17. The insulating layer 33 is for example open opposite a central part of the upper face of the gate 15 so as to be crossed by the gate contact metallization 27. The insulating layer 33 is for example made of a dielectric material, for example an oxide, for example silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0045] For example, the HEMT transistor 11 comprises a metal region 37 extending over a portion of the surface of the insulating layer 33. For example, the metal region 37 is based on titanium nitride and / or titanium, and / or tantalum, and / or a tungsten and tantalum alloy and / or a tungsten and titanium alloy and / or an aluminum and copper alloy. The metal region 37 is for example made of the same material as the gate contact metallization 27.

[0046] The HEMT transistor 11 may comprise a second insulating layer 39 re- covering the entire structure with the exception of the source 29 and drain 31 contact metallizations. The second insulating layer 39 is, for example, made of the same material as the insulating layer 33.

[0047] The metal regions 37 and 41 have for example the function of modifying the profile of the distribution of the electric field of the edge of the gate, located on the drain side (the right edge of the gate in [Fig.l]), and of reducing the peak of the critical electric field, thus increasing the avalanche voltage. The metal regions 37 and 41 are for example called "field plates" or field plates.

[0048] By way of example, the source contact metallization 29 extends on the upper face of the insulating layer 39 in the direction of the drain contact metallization 31, without reaching the drain contact metallization 31.

[0049] In the transistor of [Fig.l], the 2DEG channel is for example normally closed ("normally-off" in English), that is to say it is interrupted under the gate 15 which prevents the circulation of a current between the source and the drain of the transistor. The transistor is said to be in the blocked state. The channel can be reestablished (that is to say made conducting) by the polarization of the gate 15. In this case, a current can be established between the source and the drain of the transistor. The embodiments described can also be applied to normally open transistors ("normally-on" in English).

[0050] The presence of the passivation layer 17 allows the protection of the upper face of the semiconductor layer 13 on which dangling connections may be present and likely to generate leakage currents and / or a reduction in the voltage resistance of the transistor. The passivation layer 17 fills these connections in order to make the surface of the semiconductor layer 13 electrically inactive.

[0051] The passivation layer 17 also makes it possible to protect the semiconductor layer 13 against oxidation and to improve its surface state to which the 2DEG channel is sensitive.

[0052] While the passivation layer 17 plays an important role in the quality and lifetime of the transistor, its presence can lead to the accumulation of electrons along the sides of the gate 15, under the passivation layer 17. This phenomenon is for example accentuated by the damage to the sides of the gate caused by the etching of the gate 15. This results in the appearance of leakage currents between the gate contact metallization 27 and the source 29 and / or drain 31 metallizations, passing through the sides of the gate.

[0053] In order to reduce this phenomenon, it is proposed to modify the doping of an upper part of the semiconductor gate 15, so as to obtain an N-type doping in this upper part, and thus define a PN junction between this upper part and a lower part of the gate. The contact metallization 27 then forms an ohmic contact with the N-type upper part of the semiconductor gate 15. Thus, the Schottky diode formed, in the example of [Fig.l], between the semiconductor gate 15 and the metallization 27, is replaced by a PN diode formed between the lower part and the upper part of the semiconductor gate 15.

[0054] [Fig.2] is a partial, schematic, sectional view of a HEMT transistor 41 according to a first embodiment.

[0055] More particularly, [Fig.2] illustrates a HEMT transistor 41 similar to the transistor 11 illustrated in [Fig.l] with the difference that the gate 15 of the transistor 41 comprises, in an upper part 151 and in a peripheral part 155 of the gate, oxygen atoms compensating for the P-type doping so as to obtain an N-type doping and thus define a PN junction at the interface between a central part 153 and the upper 151 and peripheral 155 parts of the gate.

[0056] By way of example, the upper part of type N 151 has a thickness of between 10 nm and 100 nm, for example between 30 nm and 70 nm, for example of the order of 50 nm. By way of example, the peripheral part of type N 155 has a thickness of between 10 nm and 100 nm, for example between 30 nm and 70 nm, for example of the order of 50 nm.

[0057] For example, the grid 15 is made of aluminum-gallium nitride. For example, the grid 15 is made of an aluminum-gallium nitride whose chemical formula corresponds to AlxGax |N, in which x is a positive integer. The grid 15 comprises P-type doping elements, for example magnesium atoms.

[0058] By way of example, the semiconductor layer 13 comprises a non-homogeneous percentage of aluminum throughout its thickness. The layer 13 has, for example, an increasing percentage of aluminum from its lower face, that is to say that it has a percentage of aluminum in the vicinity of the gate 15 greater than that in the vicinity of the semiconductor layer 23.

[0059] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D], [Fig.3E] and [Fig.3F] are sectional views illustrating steps of an example of a method of manufacturing the HEMT transistor 41 illustrated in [Fig.2].

[0060] [Fig.3A] illustrates a starting structure comprising, in order, from the lower face of the structure, the substrate 21, the second semiconductor layer 23 and the first semiconductor layer 13. The starting structure further comprises a gate layer 15 in which the gate 15 of the transistor 41 will be formed. In the starting structure illustrated in [Fig.3A], the layers 23, 13 and 15 each extend continuously and with a substantially uniform thickness over the entire upper surface of the substrate 21.

[0061] For example, the gate layer 15 is formed on the upper face of the layer 13, by a vapor deposition process, for example an organometallic vapor phase epitaxy process also called a chemical deposition process. in organometallic vapor phase or MOCVD (from the English "Metalorganic Chemical vapor deposition"). For example, the deposition of the gate layer 15 is carried out under at least a partial vacuum. The gate layer 15 is, for example, doped during its deposition. Alternatively, the gate layer 15 is doped after its deposition by a dopant implantation step. In this example, the gate layer 15 is P-type doped, for example by magnesium atoms.

[0062] [Fig.3B] illustrates a structure obtained at the end of a first step of compensation for the doping of the gate layer 15 by oxygen atoms, in an upper part of the gate layer (15).

[0063] More particularly, during this step, an annealing under oxygen, and for example under nitrogen, of the structure illustrated in [Fig.3A] is carried out so that the P-type doping of an upper part of the gate layer 15 is compensated by oxygen atoms. The upper part of the gate layer 15 then changes doping type, this is called doping compensation. Here, an upper part of the gate layer 15 changes from a P-type doping to an N-type doping.

[0064] In practice, annealing under oxygen, for example under nitrogen, allows, in a first step, to debond hydrogen atoms bound to the doping elements present in the gate layer, for example magnesium atoms. In a second step, annealing under oxygen, and for example under nitrogen, allows the implantation of oxygen atoms, which are N-type doping elements, in the structure and more particularly in the upper part of the gate layer 15.

[0065] For example, the oxygen annealing comprises a percentage of oxygen of between 1% and 20%, for example of between 2% and 10%, for example of the order of 5%. The oxygen annealing is for example carried out at a temperature of between 600°C and 1000°C, for example of between 750°C and 900°C, for example of the order of 820°C.

[0066] At the end of this step, the gate layer 15 comprises an upper part 151 and a central part 153 whose interface defines a PN junction.

[0067] [Fig.3C] illustrates a structure obtained at the end of a first step of etching the gate layer 15.

[0068] More particularly, during this step, a masking layer 25 is firstly formed, for example, on and, for example, in contact with, the structure illustrated in [Fig. 3B]. The masking layer 25 is, for example, made of a material resistant to the etching described below, for example, an oxide, for example tetraethyl orthosilicate or TEOS (from the English "Tetraethyl orthosilicate"). For example, the masking layer 25 is not made of a resin. The masking layer 25 has, for example, a thickness of between 50 nm and 200 nm, for example of the order of 100 nm. For example, the masking layer 25 is formed so that it covers the structure illustrated in [Fig.3B] at the location of the future grid 15.

[0069] During this step, the grid layer 15 is then etched through the masking layer 25, for example by a plasma etching process, for example by a chlorine-based plasma etching process, for example by plasma etching in boron trichloride (BC13) and dichlorine (Cl2).

[0070] The gate layer 15 and more precisely the part of the gate layer 15 located outside the masking layer 25 is, during this step, partially etched, that is to say it is etched over only a part of its thickness. For example, during this step, the gate layer 15 is etched over 50% to 90% of its thickness, for example over 80% of its thickness.

[0071] At the end of this step, the grid layer 15 remains opposite the masking layer 25 and outside the masking layer 25 only over a portion of its thickness.

[0072] [Fig.3D] illustrates a structure obtained at the end of a second step of compensation for the doping of the gate layer 15 by oxygen atoms.

[0073] More particularly, during this step, an oxygen annealing of the structure illustrated in [Fig.3C] is carried out similarly to what has been described in relation to [Fig.3B]. This step is for example carried out while the masking layer 25 is still present on the surface of the structure. The sides of the part of the gate layer 15 located under the masking layer 25 and an upper part of what remains of the gate layer 15 outside the masking layer 25 are then compensated by oxygen atoms.

[0074] At the end of this step, the gate layer 15 comprises the upper part 151 and a peripheral part 155 doped with the N type and the central part 153 doped with the P type. By way of example, the peripheral part 155 of the gate layer 15 has a thickness of between 10 nm and 100 nm, for example of between 30 nm and 70 nm, for example of the order of 50 nm.

[0075] Leaving a part of the gate layer 15 outside the masking layer 25 makes it possible, during this step, to protect the semiconductor layer 13 and to compensate for the doping of the gate layer 15 without modifying the doping of the semiconductor layer 13.

[0076] [Fig.3E] illustrates a structure obtained at the end of a second step of etching the gate layer 15 through the masking layer 25 so as to form the gate 15.

[0077] During this step, for example, what remains of the grid layer 15 is etched away from the masking layer 25, for example by a plasma etching process, for example by a chlorine-based plasma etching process, for example by a plasma etching based on dichlorine (Cl2) and dioxygen (O2) or by a plasma etching based on boron trichloride (BC13) and sulfur hexafluoride (SF6).

[0078] By way of example, the etching step is continued until the upper face of the semiconductor layer 13 is revealed and the gate layer 15 remains only opposite the masking layer 25 so as to form the gate 15 of the transistor.

[0079] This etching step is, for example, followed by a step of removing the masking layer 25. By way of example, the removal of the etching mask is carried out using hydrogen fluoride (HF).

[0080] [Fig.3F] illustrates a structure obtained at the end of a step of forming the passivation layer 17, the insulating layer 33, the metallization 27 and the region 37 on the upper face of the structure illustrated in [Fig.3E].

[0081] During this step, the full plate passivation layer 17 is first formed, so that it covers the entire upper face of the structure illustrated in [Fig.3E].

[0082] The passivation layer 17 is, for example, formed in contact with the upper face of the semiconductor layer 13 and the sides and the upper face of the gate 15. The passivation layer 17 is, for example, formed by a thin-film deposition method, for example by ALD. For example, the method for deposition of the passivation layer 17 is plasma-assisted or thermally assisted. For example, the passivation layer 17 has a thickness of between 1 nm and 10 nm, for example between 3 nm and 7 nm, for example of the order of 5 nm.

[0083] In a second step, during this step, the full-plate insulating layer 33 is formed, so that it covers the entire upper face of the passivation layer 17. The insulating layer 33 is for example formed in contact with the passivation layer 17. The insulating layer 33 is for example formed by a plasma-enhanced chemical vapor deposition (PECVD) process. At the end of this step, the insulating layer 33 has a thickness for example between 150 nm and 400 nm, for example between 200 nm and 350 nm, for example of the order of 300 nm.

[0084] By way of example, the steps of depositing the passivation layer 17 and the insulating layer 33 are preceded by one or more steps of preparing the surface of the structure illustrated in [Fig.3E]. The preparation of the surface of the structure illustrated in [Fig.3E] may comprise cleaning consisting, for example, of chemical cleaning using acid, for example hydrogen chloride (HCl) and hydrogen fluoride (HF). The preparation of the surface of the structure illustrated in [Fig.3E] may, in addition, comprise cleaning consisting, for example, of surface oxidation. The passivation layer 17 will thus be formed in contact with an oxide film, itself formed in contact with the upper face of the layer 13.

[0085] During this step, in a third step, the passivation layer 17 and the insulating layer 33 opposite a central part of the upper face of the gate 15 are removed and the gate contact metallization 27 is formed in the opening formed. For example, this step comprises the removal of the layer 33 then the removal of the layer 17. For example, the removal of the layer 33 is carried out by plasma etching, for example based on fluorine, for example based on carbon tetrafluoride (CF4). For example, the removal of the layer 17 is carried out by plasma etching, for example based on chlorine, for example based on boron trichloride (BC13). In this example, the layer 17 is etched so as to reveal the upper face of the gate 15.

[0086] The above-mentioned etchings are for example followed by a step of cleaning the upper face of the structure so as to remove for example the residues from the masking layer 25 and the impurities from the etching of the gate layer 15. The cleaning of the structure comprises for example a stripping step using oxygen and nitrogen (N2) plasma. The cleaning of the structure may further comprise a step of removing organic residues using a solvent.

[0087] During this step, for example, the gate contact metallization 27 is formed in the opening formed in the layers 17 and 33 opposite the central part of the gate 15. By way of example, the gate contact metallization 27 is formed on and in contact with the upper face of the gate 15 and more precisely on and in contact with the upper part 151 of the gate 15.

[0088] By way of example, during this step, the region 37 is also formed on a portion of the surface of the first insulating layer 33. The gate contact metallization 27 and the region 37 are, for example, formed by deposition of one or more layers of a metallic material followed by an etching step.

[0089] By way of example, the step of forming the gate contact metallization 27 and the region 37 is preceded by a step of preparing the surface of the structure, consisting for example of chemical cleaning using acid, for example hydrogen chloride (HCl).

[0090] At the end of this step, the insulating layer 39 is for example formed on the upper face of the structure illustrated in [Fig.3F]. During this step, for example, the full-plate insulating layer 39 is formed, so that it covers the entire upper face of the structure illustrated in [Fig.3F], that is to say the upper face and the sides of the gate contact metallization 27 and of the region 37 and a part of the layer 33. The insulating layer 39 is for example formed by a method identical to the method for forming the layer 33 described in relation to [Fig.3F]. At the end of this step, the insulating layer 39 has a thickness for example between 150 nm and 400 nm, for example between 200 nm and 350 nm, for example of the order of 300 nm.

[0091] Finally, we come, for example, to form the ohmic contacts and more particularly the source 29 and drain 31 contact metallizations so as to form the structure illustrated in [Fig.2].

[0092] For this, openings intended to receive the source 29 and drain 31 contact metallizations are, in a first step, created in the layers 17, 33 and 39. The openings are for example formed by a plasma etching process, for example based on fluorine, for example based on carbon tetrafluoride (CF4). The aforementioned etching is for example selective and does not etch the gallium nitride semiconductor layer 13. The etching of the layers 17, 33 and 39 thus stops when the upper face of the layer 13 is revealed. The step of forming the openings intended to receive the contact metallizations 29 and 31 is for example followed by a step of cleaning the upper face of the structure, for example similarly to what was described above for the gate contact metallization 27 and the region 37.For example, a step of preparing the surface of the upper face of the layer 13 in the openings, in order to accommodate the contact metallizations 29 and 31, can be provided. This step consists for example of chemical cleaning using acid, for example hydrogen chloride (HCl).

[0093] In a second step, the source 29 and drain 31 contact metallizations are, for example, formed in the previously made openings. The metallizations 29, 31 and a region 47 are, for example, formed by deposition of one or more layers of a metallic material on the entire upper face of the structure, here the upper face of the layers 13 and 39, followed by an etching step.

[0094] [Fig.4] is a partial and schematic sectional view of a HEMT transistor 43 according to a second embodiment.

[0095] The transistor 43 illustrated in [Fig. 4] is similar to the HEMT transistor 41 illustrated in [Fig. 2] except that the peripheral portions of the gate 15 are not N-type doped. The method of manufacturing the transistor 43 differs from the method of manufacturing the transistor 41 in that, in the method of manufacturing the transistor 43, the second compensation step is omitted. Furthermore, the transistor 43 illustrated in [Fig. 4] is similar to the HEMT transistor 41 illustrated in [Fig. 2] except that the etching step described in connection with [Fig. 3C] is a complete etch and the step of continuing the etching of the gate layer 15 is omitted.

[0096] Thus, in the method for manufacturing the transistor 43, the etching of the gate layer 15 is carried out in a single step, that is to say that the gate layer 15 is removed from the opposite of the masking layer 25 in its entire thickness during a single etching step. The method for manufacturing the transistor 43 comprises, following the step of etching the gate layer 15 so as to form the gate 15, the step of forming the layers 17 and 33 similarly to what has been described in relation with [Fig.3F].

[0097] More particularly, in this example, transistor 43 is different from transistor 41 in that gate 15 does not include N-type doped peripheral portions 155.

[0098] [Fig.5] is a partial and schematic sectional view of a HEMT transistor 45 according to a third embodiment.

[0099] Transistor 45 illustrated in [Fig.5] is similar to HEMT transistor 41 illustrated in [Fig.2] except that in the manufacturing process of transistor 45, source 29 and drain 31 contact metallizations were formed before the formation of gate contact metallization 27 whereas in the manufacturing process of transistor 41, source 29 and drain 31 contact metallizations were formed after the formation of gate contact metallization 27.

[0100] More particularly, in this example, transistor 45 is different from transistor 41 in that gate contact metallization 27 passes through layer 39 and in that layer 39 covers contact metallizations 29 and 31.

[0101] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the second and third embodiments described in Figures 4 and 5, respectively, may be combined.

[0102] Furthermore, although an exemplary embodiment has been described above in which the gate 15 of the transistor is in contact with the upper face of the upper semiconductor layer 13, as a variant, the gate 15 may be separated from the semiconductor layer 13 by a gate insulator layer.

[0103] Furthermore, the embodiments are not limited to the examples of numerical values or to the examples of materials mentioned in the present description.

[0104] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A method of forming a HEMT transistor (41) comprising the following successive steps: a) providing a stack comprising a channel semiconductor layer (23), a barrier semiconductor layer (13) on and in contact with the channel semiconductor layer (23) and a gate semiconductor layer (15) arranged on and in contact with the barrier semiconductor layer (13), the gate semiconductor layer (15) comprising P-type doping elements; and b) compensating the P-type doping with oxygen atoms, in an upper portion (151) of the gate semiconductor layer (15), by annealing under oxygen, so as to define a PN junction at the interface between the upper portion (151) and a central portion (153) of the gate semiconductor layer (15).

2. Method according to claim 1, comprising a step c) of etching the gate semiconductor layer (15).

3. A method according to claim 2, wherein the etching of step c) is carried out after step b).

4. Method according to claim 3, in which: - the etching of step c) is partial, a part of the thickness of the gate semiconductor layer (15) remaining at the end of the etching step; and - the etching of step c) is followed by another step of compensating for the P-type doping by oxygen atoms in a peripheral part of the etched semiconductor layer (15) and another etching step making it possible to remove what remains of the gate semiconductor layer (15) at the end of the etching step of step c).

5. HEMT transistor (11) comprising: - a channel semiconductor layer (23); - a barrier semiconductor layer (13) on and in contact with the channel semiconductor layer (23); and - a semiconductor gate (15) arranged on and in contact with a first face of the barrier semiconductor layer (13), opposite the channel semiconductor layer (23), wherein the gate (15) comprises an upper portion (151) and a central portion (153), the upper portion (151) and the central portion (153) comprising P-type doping elements, and the upper portion (151) comprising oxygen atoms compensating for the P-type doping so as to define a PN junction at the interface between the central portion (153) and the upper portion (151), wherein the gate (15) further comprises a peripheral portion (155) extending along the flanks of the gate (15), the peripheral portion comprising P-type doping elements and comprising oxygen atoms compensating for the P-type doping so as to define a PN junction at the interface between the central portion (153) and the peripheral portion (155).

6. Transistor according to claim 5, comprising a passivation layer (17) extending over the first face of the first semiconductor layer (13) and the sides of the gate (15) and a peripheral part of a face of the gate (15) opposite the first semiconductor layer (13).

7. A transistor according to claim 6, wherein the first passivation layer (17) is made of alumina.

8. A transistor according to any one of claims 5 to 7, wherein the first semiconductor layer (13) is based on gallium nitride.

9. A transistor according to claim 8, wherein the first semiconductor layer (13) is made of aluminum gallium nitride.

10. A transistor according to claim 9, wherein the first semiconductor layer comprises a decreasing percentage of aluminum from its first face.

11. Transistor according to any one of claims 5 to 10, comprising a second semiconductor layer (23) in contact with a second face of the first semiconductor layer (13), opposite the first face.

12. A transistor according to claim 11, wherein the second semiconductor layer (23) is gallium nitride.

13. A transistor according to any one of claims 5 to 12, wherein the semiconductor gate (15) is made of gallium nitride.

14. Power conversion or adaptation circuit comprising at least one transistor according to any one of claims 5 to 13.

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