HEMT transistor

Abstract

HEMT Transistor This description relates to a HEMT transistor (11) comprising: - a first semiconductor layer (13); - a gate (15) disposed on a first face of the first semiconductor layer (13); and - a first passivation layer (17) of a first dielectric material extending over said first face of the first semiconductor layer, the sides of the gate (15), and at least a peripheral portion of a gate face opposite the first semiconductor layer, wherein a second passivation layer (25) of a second dielectric material extends between said gate face and the first passivation layer, the sides of the gate (15) not being coated by said second passivation layer (25). Figure for the abbreviation: Fig. 1

Description

Title of the invention: HEMT Transistor technical field

[0001] This description relates generally to the field of transistors and more particularly to the field of high electron mobility transistors also called HEMTs (from the English "High Electron Mobility Transistor"). Previous technique

[0002] HEMT transistors are based on a heterojunction on the surface of which a two-dimensional electron gas called 2DEG is formed.

[0003] There is a need for improvement of HEMT transistors and their manufacturing processes. Summary of the invention

[0004] To this end, one embodiment provides a HEMT transistor comprising: - a first semiconductor layer; - a grid arranged on one face of the first semiconductor layer; And - a first passivation layer in a first dielectric material extending over said first face of the first semiconductor layer, the sides of the grid and at least a peripheral part of a face of the grid opposite the first semiconductor layer, in which a second passivation layer in a second dielectric material extends between said face of the grid and the first passivation layer, the sides of the grid not being coated by said second passivation layer.

[0005] According to one embodiment, the first semiconductor layer is based on gallium nitride.

[0006] According to one embodiment, the first semiconductor layer is made of aluminum-gallium nitride.

[0007] According to one embodiment, the first passivation layer is made of alumina.

[0008] According to one embodiment, the second passivation layer is made of nitride.

[0009] According to one embodiment, the second passivation layer is made of nitride silicon, in silicon carbonitride or in aluminium nitride.

[0010] According to one embodiment, the second passivation layer is made of oxide, for example alumina or silicon dioxide.

[0011] According to one embodiment, the transistor comprises a second semiconductor layer in contact with a second face of the first semiconductor layer, opposite to the first face.

[0012] According to one embodiment, the second semiconductor layer is made of gallium nitride.

[0013] According to one embodiment, the transistor comprises a source contact metallization and a drain contact metallization, arranged respectively on either side of the gate.

[0014] Another embodiment provides for a power conversion or adaptation circuit comprising at least one transistor as defined above.

[0015] Another embodiment provides a method for forming a HEMT transistor comprising the following steps: a) form a first semiconductor layer; b) form a grid arranged on one face of the first semiconductor layer; and (c) form a first passivation layer in a first dielectric material extending over said first face of the first semiconductor layer, the sides of the grid and at least a peripheral part of a face of the grid opposite the first semiconductor layer, and wherein a second passivation layer in a second dielectric material is formed between said face of the grid and the first passivation layer, the sides of the grid not being coated by said second passivation layer.

[0016] According to one embodiment, the process comprises the following successive steps: - deposition of a layer of grid material on the first face of the first semiconductor layer; - deposition of a layer in the second dielectric material over the entire surface of the layer in the grid material; - localized etching, through the same etching mask, of the layer in the grid material and of the layer in the second dielectric material so as to form respectively the grid and the second passivation layer. Brief description of the drawings

[0017] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0018] [Fig.1] is a partial and schematic cross-sectional view of an example of a HEMT transistor according to a first embodiment;

[0019] the [Fig.2A], the [Fig.2B], the [Fig.2C], the [Fig.2D], the [Fig.2E], the [Fig.2F] and the [Fig. 2G] are cross-sectional views illustrating steps in an example of a manufacturing process for the HEMT transistor shown in [Fig. 1]; and

[0020] [Fig. 3] is a partial, schematic cross-sectional view of an example of a transistor HEMT according to a second embodiment. Description of the implementation methods

[0021] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0022] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the applications of the described HEMT transistors are not detailed, as the embodiments are compatible with the usual applications of HEMT transistors. The focus here is particularly on so-called power HEMT transistors, capable of withstanding relatively high voltages in the off state, for example, voltages on the order of 100 to 650 volts. The described transistors can, for example, be used in various power conversion or adaptation circuits, for example in industrial equipment, display or lighting devices, telecommunications equipment, automotive devices, etc.

[0023] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0024] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0025] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0026] Fig. 1 is a partial, schematic cross-sectional view of an example of a HEMT 11 transistor according to one embodiment.

[0027] The HEMT transistor 11 comprises a first semiconductor layer 13 disposed on a second conductive layer 23. The semiconductor layer 23 is, for example, in contact, by its lower face, with the upper face of the conductive layer 23. By way of example, the stack comprising the semiconductor layer 13 and the semiconductor layer 23 rests on a substrate 21. The semiconductor layer 23 is, for example, in contact, by its lower face, with the upper face of the substrate 21. The interface between the semiconductor layer 13 and the semi- miconductrice 23 defines a heterojunction on the surface of which a two-dimensional electron gas 2DEG also called an electron channel is formed.

[0028] The semiconductor layers 13 and 23 are, for example, made of type III-V semiconductor materials, for example gallium nitride (GaN) based. The semiconductor layer 13 is, for example, made of gallium aluminum nitride (AlGaN). The semiconductor layer 23 is, for example, made of gallium nitride (GaN).

[0029] By way of example, the substrate 21 is made of a semiconductor material. The substrate 21 is, for example, made of silicon or silicon carbide. Alternatively, the substrate 21 is made of aluminum nitride. The substrate 21 includes, for example, on its upper face, a buffer layer, not detailed in the figures, for example made of gallium nitride. The buffer layer is, for example, in contact, via its upper face, with the lower face of the semiconductor layer 23.

[0030] The HEMT transistor 11 has a gate 15 on the upper face of the semiconductor layer 13. The gate 15 is, for example, in contact, by its lower face, with the upper face of the semiconductor layer 13.

[0031] The grid 15 is for example made of a semiconductor material, for example a type III-V semiconductor material, for example gallium nitride, for example P-type doped.

[0032] By way of example, the HEMT transistor 11 further comprises a source contact metallization 29 and a drain contact metallization 31. By way of example, the contact metallizations 29 and 31 are based on titanium, titanium nitride, and / or an aluminum-copper alloy. The source contact metallizations 29 and drain contact metallizations 31 each define, for example, an ohmic contact with the semiconductor layer 13. The contact metallizations 29 and 31 are, for example, located on and in contact with the semiconductor layer 13, on either side of the gate 15.

[0033] The HEMT transistor 11 further comprises a passivation layer 25, made of a dielectric material, extending over the upper face of the gate 15 but not over the sides of the gate. The passivation layer 25 is, for example, in contact, by its lower face, with the upper face of the gate 15.

[0034] The passivation layer 25 has, for example, a thickness between 1 nm and 20 nm, for example between 1 nm and 10 nm, for example on the order of 2 nm.

[0035] The passivation layer 25 is, for example, made of nitride, for example silicon nitride (Si3N4), silicon carbonitride (SiOxNy), or aluminum nitride (Ni). The passivation layer 25 is, for example, made of oxide, for example alumina (Al12O3) or silicon dioxide (SiO2).

[0036] The HEMT transistor 11 further comprises a passivation layer 17 covering the sides and at least part of the upper face of the passivation layer 25, the sides of the gate 15 and extending over part of the upper face of the Semiconductor layer 13 not covered by the grid 15. By way of example, the passivation layer 17 is in contact, by its lower face, with the upper face of the semiconductor layer 13. The passivation layer 17 is, for example, also in contact with the sides of the grid 15. The passivation layer 17 is, for example, also in contact, by its lower face, with the upper face of the semiconductor layer 13. In the embodiment of [Fig. 1], the passivation layer 17 extends laterally between the contact metallizations of source 29 and drain 31.

[0037] The passivation layer 17 has, for example, a thickness of between 2 nm and 20 nm, for example between 2 nm and 10 nm, for example on the order of 5 nm. The passivation layer 17 is, for example, made of a dielectric material, for example alumina (Al₂O₃), silicon dioxide (SiO₂), aluminum nitride (Ni) or hafnium acid (HfO₂).

[0038] The grid 15 is for example surmounted by a grid contact metallization 27.

[0039] By way of example, the grid contact metallization 27 is in contact, by its lower face, with the upper face of the grid 15. The grid contact metallization 27 then extends through the layers 17 and 25 which only cover the upper face of the grid 15 on its periphery.

[0040] Alternatively, the grid contact metallization 27 is in contact, via its lower face, with the upper face of the passivation layer 25, which extends over the entire surface of the upper face of the grid 15. The grid contact metallization 27 then extends through the layer 17, which only covers the periphery of the passivation layer 25. This alternative is illustrated, for example, by [Fig. 3] described below.

[0041] By way of example, the grid contact metallization 27 is based on titanium nitride and / or titanium, and / or tantalum, and / or a tungsten and tantalum alloy and / or a tungsten and titanium alloy and / or an aluminum and copper alloy.

[0042] The HEMT 11 transistor comprises, for example, several levels of insulating layers in, and for example on, which metallizations are formed.

[0043] By way of example, the HEMT transistor 11 includes an insulating layer 33 on and in contact with the upper face of the passivation layer 17. By way of example, the insulating layer 33 covers the entire surface of the passivation layer 17. The insulating layer 33 is, for example, open opposite a central part of the upper face of the gate 15 so as to be traversed by the gate contact metallization 27. The insulating layer 33 is, for example, made of a dielectric material, for example an oxide, for example silicon dioxide (SiO2).

[0044] By way of example, the HEMT transistor 11 includes a metallic region 37 extending over a portion of the surface of the insulating layer 33. By way of example, the metallic region 37 is based on titanium nitride and / or titanium, and / or tantalum, and / or a tungsten-tantalum alloy and / or a tungsten-titanium alloy and / or of an aluminum and copper alloy. The metallic region 37 is, for example, made of the same material as the grid contact metallization 27.

[0045] The HEMT transistor 11 may include a second insulating layer 39 covering the entire structure except for the source 29 and drain 31 contact metallizations. The second insulating layer 39 is, for example, made of the same material as the insulating layer 33.

[0046] By way of example, the source contact metallization 29 extends over the upper face of the insulating layer 39 towards the drain contact metallization 31, without reaching the drain contact metallization 31.

[0047] In the transistor of [Fig. 1], the 2DEG channel is, for example, normally closed (blocked) ("normally-off"), that is, it is interrupted below the gate 15, which prevents current from flowing between the source and the drain of the transistor. The transistor is said to be in the blocked state. The channel can be restored (that is, made conducting) by biasing the gate 15. In this case, a current can flow between the source and the drain of the transistor. The embodiments described can also be applied to normally open (conducting) ("normally-on") transistors.

[0048] The presence of the passivation layer 17 protects the upper surface of the semiconductor layer 13, on which dangling bonds may be present and capable of generating leakage currents and / or reducing the voltage rating of the transistor. The passivation layer 17 bridges these bonds to render the surface of the semiconductor layer 13 electrically inactive.

[0049] The passivation layer 17 also helps to protect the semiconductor layer 13 against oxidation and to improve its surface condition to which the 2DEG channel is sensitive.

[0050] While the passivation layer 17 plays an important role in the quality and lifespan of the transistor, its presence can lead to the accumulation of electrons along the sides of the gate 15, under the passivation layer 17. This phenomenon is, for example, accentuated by damage to the sides of the gate caused by the etching of the gate 15. The presence of the passivation layer 25 on the top face of the gate 15 allows the reduction of the lateral leakage current originating from the top face of the gate 15 and carried by these electrons.

[0051] The grid 15, preferentially formed by epitaxy, has, for example, a gallium polarity, that is to say, in its atomic arrangement, the grid 15 terminates at its upper face with gallium atoms, thus leaving nitrogen vacancies on the surface of this face. An advantage of forming a second passivation layer 25 in nitride on the surface of the upper face of the grid 15 is that it makes it possible to fill the nitrogen vacancies present on the surface of the upper face of grid 15, which can generate leakage currents.

[0052] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F and Fig. 2G are cross-sectional views illustrating successive stages of an example of a manufacturing process for the HEMT transistor illustrated in Fig. 1.

[0053] [Fig. 2A] illustrates a starting structure comprising, in order, from the lower face of the structure, the substrate 21, the second semiconductor layer 23 and the first semiconductor layer 13. The starting structure further comprises a grid layer 15 surmounted by the passivation layer 25. In the starting structure illustrated in [Fig. 2A], the layers 23, 13, 15 and 25 each extend continuously and with a substantially uniform thickness over the entire upper surface of the substrate 21.

[0054] By way of example, the grid 15 is formed on the upper face of the layer 13 by a vapor deposition process, for example a metal-organic chemical vapor deposition (MOCVD) process. For example, the deposition of the grid 15 is carried out under at least a partial vacuum.

[0055] By way of example, the passivation layer 25 is formed on the upper face of the grid 15 by MOCVD, for example under at least a partial vacuum. In this example, the passivation layer 25 and the grid 15 are formed in the same chamber without any break in the vacuum between the two depositions. Such a deposition process is used, for example, for the formation of a nitride passivation layer 25, for example, silicon nitride or aluminum nitride.

[0056] Alternatively, the passivation layer 25 is formed on the upper face of the grid 15 by an atomic layer deposition (ALD) process. For example, the deposition process for the passivation layer 25 is plasma-assisted. Such a deposition process is used, for instance, for the formation of a nitride passivation layer 25, for example, silicon nitride, aluminum nitride, or silicon carbonitride.

[0057] [Fig.2B] illustrates a structure obtained after a localized etching step of the gate layer 15 and the passivation layer 25 so as to retain only a portion of each layer forming the gate stack of the transistor of [Fig.1].

[0058] During this step, the passivation layer 25 is etched, for example by a plasma etching process, for example by a chlorine-based plasma etching process, for example by a boron trichloride (BC13) plasma etching process.

[0059] During this step, the grid 15 is also engraved, for example by a plasma etching process, for example by a chlorine-based plasma etching process, for example by a plasma etching in dichlorine (Cl2) and dioxygen (O2).

[0060] By way of example, the grid 15 and the passivation layer 25 are etched through the same mask. At the end of this step, the grid 15 and the passivation layer 25 are thus aligned, that is to say, their sides are aligned.

[0061] The etching steps of the grid 15 and the passivation layer 25 are, for example, carried out simultaneously, i.e., they are carried out within the same etching chamber. Alternatively, the etching steps of the grid 15 and the passivation layer 25 are carried out successively, one after the other.

[0062] These etching steps are, for example, followed by a cleaning step of the upper surface of the structure to remove, for example, residues from the etching mask(s) and impurities from the etching of the passivation layer 25 and the grid 15. The cleaning of the structure includes, for example, a stripping step using a plasma of oxygen and nitrogen (N2). The cleaning of the structure may also include a step of removing organic residues using a solvent.

[0063] Fig. 2C illustrates a structure obtained after a step of forming the passivation layer 17 and the insulating layer 33 on the upper face of the structure illustrated in Fig. 2B.

[0064] During this step, the full plate passivation layer 17 is first formed so that it covers the entire upper face of the structure illustrated in [Fig.2B].

[0065] The passivation layer 17 is, for example, formed in contact with the upper face of the semiconductor layer 13, the sides of the gate 15 and the sides and the upper face of the passivation layer 25.

[0066] The passivation layer 17 is, for example, formed by a thin-film deposition process, for example by ALD. As an example, the deposition process of the passivation layer 17 is plasma-assisted.

[0067] In a second step, in this example, the full-plate insulating layer 33 is formed so that it covers the entire upper surface of the passivation layer 17. The insulating layer 33 is formed, for example, in contact with the passivation layer 17. The insulating layer 33 is formed, for example, by a plasma-enhanced chemical vapor deposition (PECVD) process. After this step, the insulating layer 33 has a thickness, for example, between 150 nm and 400 nm, for example, between 200 nm and 350 nm, for example, on the order of 260 nm.

[0068] By way of example, the steps of depositing the passivation layer 17 and the insulating layer 33 are preceded by one or more surface preparation steps for the structure illustrated in [Fig. 2B]. The surface preparation of the structure illustrated in [Fig. 2B] may include cleaning, for example, by cleaning Chemical preparation using an acid, for example hydrogen chloride (HCl) and hydrogen fluoride (HF). Surface preparation of the structure illustrated in [Fig. 2B] may also include cleaning, for example, by surface oxidation. The passivation layer 17 will thus be formed in contact with a film of a dielectric material, for example an oxide, itself formed in contact with the upper face of the layer 13.

[0069] Fig. 2D illustrates a structure obtained after an opening step of layers 17, 25 and 33 opposite the grid 15 of the structure illustrated in Fig. 2C.

[0070] More specifically, during this step, the passivation layers 17 and 25 and the insulating layer 33 opposite a central part of the upper face of the grid 15 are removed.

[0071] By way of example, this step includes firstly the removal of layer 33 and secondly the removal of layers 17 and 25. By way of example, the removal of layer 33 is carried out by plasma etching, for example based on fluorine, for example based on carbon tetrafluoride (CF4).

[0072] By way of example, the removal of layers 17 and 25 is carried out by plasma etching, for example using chlorine-based plasma, for example using boron trichloride (BC13). In this example, layers 17 and 25 are etched so as to expose the upper face of the grid 15.

[0073] Alternatively, during this step, the passivation layer 25 is not removed opposite the central part of the upper face of the grid 15, the etching of the passivation layer 17 being interrupted when the upper face of the passivation layer 25 is revealed.

[0074] The aforementioned engravings are followed, for example, by a cleaning step of the upper face of the structure, for example similarly to what has been described in relation to [Fig.2B].

[0075] [Fig.2E] illustrates a structure obtained after a metallization formation step of region 27 and region 37 on the upper face of the structure illustrated in [Fig.2D],

[0076] During this step, for example, the contact metallization of grid 27 is formed in the opening formed in the layers 17 and 33 opposite the central part of the grid 15. As an example, the contact metallization of grid 27 is formed on and in contact with the upper face of the grid 15. Alternatively, the contact metallization of grid 27 is formed on and in contact with the upper face of the passivation layer 25.

[0077] By way of example, during this step, region 37 is further formed on a portion of the surface of the first insulating layer 33. The grid contact metallization 27 and region 37 are, for example, formed by deposition of one or more layers in a metallic material followed by an engraving step.

[0078] By way of example, the step of forming the contact metallization of grid 27 and region 37 is preceded by a step of preparing the surface of the structure illustrated in [Fig.2D], consisting for example of chemical cleaning with acid, for example hydrogen chloride (HCl).

[0079] Fig. 2F illustrates a structure obtained after a step of forming the insulating layer 39 on the upper face of the structure illustrated in Fig. 2E.

[0080] In this step, for example, the full-plate insulating layer 39 is formed so that it covers the entire upper surface of the structure illustrated in [Fig. 2E], that is, the upper surface and the sides of the grid contact metallization 27 and region 37, and part of layer 33. The insulating layer 39 is formed, for example, by a process identical to the process for forming layer 33 described in relation to [Fig. 2C]. At the end of this step, the insulating layer 39 has a thickness, for example, between 150 nm and 400 nm, for example, between 200 nm and 350 nm, for example, on the order of 260 nm.

[0081] Figure 2G illustrates the structure obtained after a step of forming localized openings in the stack of dielectric layers 39, 33 and 17 so as to expose the upper face of the semiconductor layer 13 opposite the source and drain contact regions of the transistor, followed by a step of forming the source 29 and drain 31 contact metallizations in said openings. The structure thus obtained is, for example, identical or similar to the structure illustrated in Figure 1.

[0082] The openings for receiving the source contact metallizations 29 and drain contact metallizations 31 are, for example, formed by a plasma etching process, for example, fluorine-based or carbon tetrafluoride (CF4)-based. The aforementioned etching is, for example, selective and does not etch the gallium nitride semiconductor layer 13. The etching of layers 17, 33, and 39 thus stops when the upper surface of layer 13 is exposed. The step of forming the openings for receiving the contact metallizations 29 and 31 is, for example, followed by a step of cleaning the upper surface of the structure, for example, similarly to what has been described in relation to [Fig. 2B]. By way of example, a step of preparing the surface of the upper face of layer 13 in the openings, in order to receive the contact metallizations 29 and 31, may be provided.This step involves, for example, chemical cleaning using acid, such as hydrogen chloride (HCl).

[0083] In a second step, the contact metallizations of source 29 and drain 31 are, for example, formed in the previously made openings. The metallizations 29, 31 and region 41 are, for example, formed by depositing one or more layers of a metallic material over the entire upper face of the structure, here the top face of layers 13 and 39, followed by an etching step to laterally delimit the contact metallizations of source 29 and drain 31.

[0084] Fig. 3 is a partial, schematic cross-sectional view of an example of an 11' HEMT transistor according to a second embodiment.

[0085] The transistor 11' illustrated in [Fig.3] is similar to the transistor 11 illustrated in [Fig.1] except that, in the manufacturing process of the transistor 11', the source 29 and drain 31 contact metallizations were formed before the formation of the gate 27 contact metallization, whereas in the manufacturing process of the transistor 11, the source 29 and drain 31 contact metallizations were formed after the formation of the gate 27 contact metallization.

[0086] More particularly, in this example, transistor 11' differs from transistor 11 in that the gate contact metallization 27 passes through layer 39 and in that layer 39 covers the contact metallizations 29 and 31.

[0087] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0088] In addition, although an example of an embodiment has been described above in which the gate 15 of the transistor is in contact with the upper face of the upper semiconductor layer 13, as an alternative, the gate 15 can be separated from the semiconductor layer 13 by a gate insulator layer.

[0089] Finally, the embodiments are not limited to the examples of numerical values ​​or the examples of materials mentioned in this description.

[0090] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. HEMT transistor (11) comprising: - a first semiconductor layer (13); - a grid (15) disposed on a first face of the first semiconductor layer (13);and - a first passivation layer (17) in a first dielectric material extending over said first face of the first semiconducting layer, the sides of the grid (15) and at least a peripheral part of a face of the grid opposite the first semiconducting layer, wherein a second passivation layer (25) in a second dielectric material extends between said face of the grid and the first passivation layer, the sides of the grid (15) not being coated by said second passivation layer (25), wherein the second passivation layer (25) extends over the entire surface of the upper face of the grid (15), a grid contact metallization (27) being in contact, by its lower face, with the upper face of the second passivation layer (25).

2. Transistor according to claim 1, wherein the first semiconductor layer (13) is gallium nitride based.

3. Transistor according to claim 2, wherein the first semiconductor layer (13) is made of aluminum-gallium nitride.

4. Transistor according to any one of claims 1 to 3, wherein the first passivation layer (17) is made of alumina.

5. Transistor according to any one of claims 1 to 4, wherein the second passivation layer (25) is nitride.

6. Transistor according to claim 5, wherein the second passivation layer (25) is made of silicon nitride, silicon carbonitride or aluminium nitride.

7. Transistor according to any one of claims 1 to 4, wherein the second passivation layer (25) is made of oxide, for example alumina (Al2O3) or silicon dioxide (SiO2).

8. Transistor according to any one of claims 1 to 7, comprising a second semiconductor layer (23) in contact with a second face of the first semiconductor layer (13), opposite to the first face.

9. Transistor according to claim 8, wherein the second layer se- miconductrice (23) is gallium nitride.

10. Transistor according to any one of claims 1 to 9, comprising a source contact metallization (29) and a drain contact metallization (31), arranged respectively on either side of the grid (15).

11. Power conversion or adaptation circuit comprising at least one transistor according to any one of claims 1 to 10.

12. Method for forming a HEMT transistor comprising the following steps: a) forming a first semiconductor layer (13); b) forming a gate (15) disposed on a first face of the first semiconductor layer (13);and c) forming a first passivation layer (17) in a first dielectric material extending over said first face of the first semiconducting layer, the sides of the grid (15) and at least a peripheral part of a face of the grid opposite the first semiconducting layer, and wherein a second passivation layer (25) in a second dielectric material is formed between said face of the grid and the first passivation layer, the sides of the grid (15) not being coated by said second passivation layer (25), wherein the second passivation layer (25) extends over the entire surface of the upper face of the grid (15), a grid contact metallization (27) being formed in contact, by its lower face, with the upper face of the second passivation layer (25).

13. A method according to claim 12, comprising the following successive steps: - deposition of a layer of the grid material (15) on the first face of the first semiconducting layer (13); - deposition of a layer of the second dielectric material over the entire surface of the layer of the grid material (15); - localized etching, through the same etching mask, of the layer of the grid material (15) and of the layer of the second dielectric material so as to form respectively the grid (15) and the second passivation layer (25).

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