Method for automatically generating a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor

Abstract

The invention relates to a method for automatically generating a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor, comprising the steps of: initializing the registers of the processor, then choosing a first instruction of the predetermined sequence, possibly at random; andchoosing an N+1th instruction, from among a reading instruction in a memory connected to the cores of the processor by a memory bus, an instruction to write in said memory, and a local instruction using only the registers of the processors, according to rules and priorities between said rules, said rules using respective deviations of statistical metric values of a memory access profile (P) of the sequence of the N preceding instructions comprising statistical metric values, with setpoint values. Figure for abstract: [Fig.4]

Description

Title of the invention: Method for automatically generating a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor

[0001] The invention relates to a method for automatically generating a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor.

[0002] The technical field of the invention is that of software in general and more particularly the generation of software stubs or "stubs" in English. A stub is a software module simulating at least the presence of another. In the case of a more sophisticated imitation, in particular simulating a part of the functional exchanges, we speak of simulators or models. In the present invention, we are limited to simulating the impact of the execution of the software on the activity of a memory bus; we are not seeking to simulate the functional aspect of the application.

[0003] The invention also relates to the performance testing of embedded software (Worst Case Execution Time or WCET), and the analysis of the problem of processor or multi-core memory contention or interference and the behavior of software in relation to this: in particular the notions of aggressiveness and sensitivity.

[0004] The present invention is a means for automatically and rapidly generating software bottlenecks with targeted characteristics and controlled behavior with respect to memory contention.

[0005] Currently, to build a software plug, a sequence of code is developed by a programmer, in assembler or high-level language, and it is executed in a loop.

[0006] It is known to generate, by a software engineer, a sequence of code in assembly machine language or in a high-level language such as C language, which is executed in a loop. The characteristics of this sequence are determined by analysis by a software engineer, based on his expertise in the assembly code and the impact of each instruction on memory contention.

[0007] Such a "manual" construction of an assembler code sequence comes up against the intrinsic limitations of a manual activity of this type, such as a long time for large sequences, of the order of several tens of minutes, or even several hours to construct a sequence of several thousand assembler instructions, or the fine skills necessary to secure the execution on target of each sequence requiring compliance with the constraints linked to each ins- instruction (value of operands, memory addressing, register management).

[0008] Therefore, the size of manually constructed sequences is often limited to a few instructions (at most a few dozen). However, the size of the generated sequences is important to obtain a large diversity of Memory Access Profiles (sequences of a few dozen instructions will end up having similar profiles).

[0009] It is also known to construct a code sequence automatically, for example by choosing instructions at random from the instruction dictionary of the microprocessor.

[0010] The automatic construction of sequences of several hundred instructions by random drawing from the microprocessor's instruction dictionary amounts to making multiple successive random drawings, and therefore sees the law of large numbers apply.

[0011] Also, we obtain statistically very similar instruction sequences, which reflect the statistical distribution in the dictionary of instructions of the read R, write W and local type (i.e.: only working on registers), as well as an average Shannon entropy E.

[0012] Consequently, it is currently very difficult to quickly construct sequences of instructions with varied and precisely chosen characteristics, whether with a view to making them a learning base of several thousand items or to construct a single software plug with the chosen characteristics.

[0013] Often, the behavior of such sequences with respect to memory contention is difficult to anticipate: it is difficult to quantify its capacities to generate and / or undergo memory contention, called respectively its aggressiveness and its sensitivity.

[0014] In the use of multi-core microprocessors, several resources can be shared by the different software running in parallel on the different cores. In particular, the memory or RAM for acronym of "Random Access Memory" in English, is accessible by a bus common to all the cores.

[0015] Like any shared resource, this bus is managed by a controller which manages simultaneous and concurrent access according to its own arbitration logic, causing the slowing down of one or other of the software running on the different cores.

[0016] Depending on the activity of these software programs and especially their way of accessing memory (we speak of Memory Access Profile or "Memory Access Pattern" in English), there is a slowdown in their execution (linked to the wait during the execution of assembler instructions accessing memory in the event of concurrent access). This slowdown depends on: - memory bus controller arbitration logic, - software memory access profile, and - profiles of software running in parallel on other cores.

[0017] This phenomenon is known as memory interference or contention.

[0018] In the context of critical embedded software, it is necessary (and sometimes required by certification authorities) to provide the worst case value of the software execution time or WCET, in order to verify that it has time to execute in the time allocated to it.

[0019] This characterization, already difficult for complex software on single-core microprocessors, becomes even more problematic on multi-core microprocessors, due to this contention phenomenon involving all the software running in parallel.

[0020] We define the notions of aggressiveness, or capacity to generate memory contentions, and of sensitivity or propensity to undergo them, by measurement in the face of reference applications that we give ourselves: a sensible reference application is built, executing a loop of assembler instructions identified, by analysis, as having lower priority in the memory bus arbitration mechanisms. A counter is incremented each time the loop is executed, and An aggressive benchmark application is built on the same principle with a high-priority instruction loop.

[0021] To measure the aggressiveness and sensitivity of an assembler code sequence, it is executed in a loop over the same period of time in the following configurations: Execution of the sensitive application alone: the number of loops executed over the period is noted; Execution of the sequence alone: we note the number of loops executed over the period; Execution of the sequence in parallel with the sensitive application: we measure the slowdown of the sensitive application when it executes in parallel with the code sequence, compared to its execution alone; Execution of the sequence in parallel with the aggressive application: we measure the slowdown of the tested sequence when it is executed in parallel with the aggressive application, compared to its execution alone.

[0022] Aggressiveness, as illustrated in [Fig.l], is the ratio of the number of loops executed by the reference sensitive application over the same period of time when executed alone and in parallel with the sequence under test.

[0023] Sensitivity, as illustrated in [Fig.2], is the ratio of the number of loops executed by the reference aggressive application over the same period of time when executed alone and in parallel with the tested sequence.

[0024] Sensitivity and aggressiveness are ratios and are therefore expressed as percentages.

[0025] The phenomenon of memory contention or interference being intrinsically linked to requests of the memory bus by software, we seek to characterize these requests.

[0026] For this, it is known to define a memory access profile P of an assembler code sequence by a sequential list of assembler instructions accessing the memory (extract from this code sequence), as well as the memory addresses which are accessed, as illustrated in [Fig.3].

[0027] This memory access profile P is supplemented by statistical characteristics calculated on this list, in particular, in a non-exhaustive manner by: - a memory intensity that is not representative of the number of read access instructions R for Read in English or write access instructions W for Write in English, vs the total number of instructions; - a read / read-write ratio or read / memory ratio Rwr representing the number of read access instructions R vs. the number of memory access instructions (read and write). We will subsequently call the number of read-write accesses by the term the number of memory accesses; - a Shannon entropy E of the memory access profile P representing the random aspect of the addresses accessed in memory; and - an interleaving Iv, for interleaving in English, of read access instructions R and write access instructions W.

[0028] The document "Improving Prediction Accuracy of Memory Interferences for Multicore Platforms", by C.Courtaud et al, hal-02401625, details these statistical characteristics and demonstrates their relevance for characterizing the sensitivity of software to contention.

[0029] One aim of the invention is to overcome the problems mentioned above, and in particular to propose a solution enabling assembly code sequences to be generated automatically and quickly: - executable without error (i.e.: without stopping execution following a software exception); - having memory access profiles P with chosen and varied characteristics, and therefore a priori: - more or less aggressive (generating more or less memory contention); - More or less sensitive (undergoing more or less restraints).

[0030] Another object of the invention is to use these assembler code sequences to construct: - a database of several thousand software traffic jams with known memory access profiles, the aggressiveness and sensitivity of which are measured. This database can be used to train (by machine learning) a model capable of estimating the aggressiveness and

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[0034]

[0035] sensitivity of memory access profiles extracted from real critical embedded applications; and - software caps with characterized memory access profiles allowing to simulate the aggressiveness and sensitivity of concurrent embedded applications to carry out WCET performance tests of a given embedded application. According to one aspect of the invention, there is proposed a method for automatically generating a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor, comprising the steps of: - initialization of the processor registers, then choice of a first instruction from the predetermined sequence, possibly at random; and - choice of an N+1th instruction, from among a read instruction in a memory connected to the processor cores by a memory bus, a write instruction in said memory, and a local instruction using only the registers of the processors, according to rules and priorities between said rules, said rules using respective deviations of statistical metric values of a memory access profile of the sequence of the N preceding instructions comprising statistical metric values, with setpoint values. In one embodiment, the statistical metrics of the memory access profile of the sequence of the preceding N instructions comprise: - a memory intensity corresponding to the ratio of the number of read or write access instructions and the total number of instructions N; - a read / memory ratio corresponding to the ratio of read access instructions and memory access instructions (read and write); and - a Shannon entropy E of the memory access profile representing the random aspect of the addresses accessed in memory. According to one embodiment, the statistical metrics of the memory access profile of the sequence of the N preceding instructions further comprise an interleaving of the read access instructions and the write access instructions. In one embodiment, the rules include a first test rule if the memory intensity is greater than a memory intensity setpoint, in which case the choice of the N+1th instruction is a local instruction, and otherwise, the choice of the N+1th instruction is a read access instruction or a write access instruction. According to one embodiment, the rules include rules applied after the first rule, in any order: - a second test rule if the read / memory ratio is greater than a read / memory ratio instruction, in which case the choice of the N+1th instruction is an ins read access instruction, and otherwise the choice of the N+1th instruction is a write access instruction; - a third test rule if the Shannon entropy E of the memory access profile is greater than a Shannon entropy E setpoint, in which case the choice of the memory address of the N+1th instruction is chosen so as to lower the entropy E, by taking an address already used or an address whose distance to the previous one is already known, and otherwise the choice of the memory address of the N+1th instruction is chosen at random; and - a fourth test rule if the interleaving is greater than an interleaving instruction, in which case the choice of the N+1th instruction is a read access or write access instruction of the same type as the Nth instruction, and otherwise the choice of the N+1th instruction is a read access or write access instruction of the opposite type to that of the Nth instruction.

[0036] In one embodiment, the method further comprises integrating the sequence of Nmax assembly language instructions into an execution loop to generate executable software or software stub.

[0037] The invention will be better understood by studying some embodiments described as non-limiting examples and illustrated by the appended drawings in which:

[0038] [Fig.l] schematically illustrates the aggressiveness of an assembler code sequence, according to the state of the art;

[0039] [Fig.2] schematically illustrates the sensitivity of an assembler code sequence, according to the state of the art;

[0040] [Fig.3] schematically illustrates a sequential list of assembler instructions accessing memory (excerpt from this code sequence), as well as the memory addresses that are accessed from a memory access profile, according to the state of the art;

[0041] [Fig.4] schematically illustrates a method for automatically generating a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor, according to one aspect of the invention;

[0042] [Fig.5] schematically illustrates an example of instruction selection rules of the method of [Fig.4], according to one aspect of the invention;

[0043] [Fig.6] schematically illustrates an automation of the selection process of assembler instructions for rapidly constructing sequences, according to one aspect of the invention.

[0044] Throughout the figures, elements having identical references are similar.

[0045] As illustrated in [Fig.4], the invention proposes a method for automatically generating a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor, comprising the steps of: - initialization of the processor registers, then choice of a first instruction from the predetermined sequence, possibly at random; and - choice of an N+1th instruction, from among a read instruction in a memory connected to the processor cores by a memory bus, a write instruction in said memory, and a local instruction using only the registers of the processors, according to rules and priorities between said rules, said rules using respective deviations of statistical metric values of a memory access profile P of the sequence of the N preceding instructions comprising statistical metric values, with setpoint values.

[0046] The statistical metrics of the memory access profile of the sequence of the previous N instructions include: - a memory intensity Im corresponding to the ratio of the number of read access instructions R or write access instructions W and the total number of instructions N; - a read / memory ratio Rwr corresponding to the ratio of read access instructions R and memory access instructions (read R and write W); and - a Shannon entropy E of the memory access profile P representing the random aspect of the addresses accessed in memory.

[0047] The statistical metrics of the memory access profile of the sequence of the N preceding instructions may further comprise an interleaving Iv of the read access instructions R and the write access instructions W.

[0048] [Fig.5] represents an example of instruction selection rules.

[0049] The rules include a first test rule if the memory intensity Im is su greater than a memory intensity instruction hn_c, in which case the choice of the N+1th instruction is a local instruction, and otherwise, the choice of the N+1th instruction is a read access instruction R or a write access instruction W. Rules include rules applied after the first rule, in any order: - a second test rule if the read / memory ratio Rwr is greater than a read / memory ratio setpoint Rwr_c, in which case the choice of the N+1st instruction is a read access instruction R, and otherwise the choice of the N+1st instruction is a write access instruction W; - a third test rule if the Shannon entropy E Ep of the memory access profile P is greater than a Shannon entropy E Ep_c setpoint, in which case the choice of the memory address of the N+lth instruction is chosen so as to lower the entropy E, by taking an address already used or an address whose distance to the previous one is already known, and otherwise the choice of the memory address of the N+lth instruction is chosen at random; and - a fourth test rule if the interleaving Iv is greater than an interleaving instruction Iv_c, in which case the choice of the N+1th instruction is a read access instruction R or write access instruction W of the same type as the Nth instruction, and otherwise the choice of the N+1th instruction is a read access instruction R or write access instruction W of the opposite type to that of the Nth instruction. Alternatively, other metrics can be considered, and other rules defined based on these to influence the choice of instructions, registers used, and memory addresses targeted.

[0050] The method further comprises integrating the sequence of Nmax assembly language instructions into an execution loop to generate executable software or software stub.

[0051] The invention makes it possible, as illustrated in [Fig.6], to automate the process of selecting assembler instructions to quickly construct sequences: - of variable size, potentially very long (thousands of instructions), - coherent and with guaranteed execution on target (no execution errors), and - with memory access profiles close to the target values or instructions chosen.

[0052] In addition, automation makes it possible to quickly generate multiple sequences, with varied memory access profiles (depending on the multiple target values chosen), and therefore to construct a relevant learning base for machine learning, according to the following steps: - generation of the assembler instruction sequence according to the principles previously described; - integration into a C skeleton and construction of the binary; - measurements of A aggression and S sensitivity on target; - extraction of the memory access pattern and associated metrics; and - capitalization of sequences, memory access patterns and measures for to build a learning base; An additional step may consist of using the learning base for supervised training of an estimator for sensitivity and aggressiveness (machine learning).

Claims

Claims

1. Method for automatic iterative generation of a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor, comprising the steps of: - initialization of the processor registers, then choice of a first instruction from the predetermined sequence, possibly at random; and - choice of an N+1th instruction, as long as N <Nmax, parmi une instruction de lecture dans une mémoire connectée aux cœurs du processeur par un bus mémoire, une instruction d'écriture dans ladite mémoire, et une instruction locale utilisant uniquement les registres des processeurs, en fonction de règles et de priorités entre lesdites règles, lesdites règles utilisant des écarts respectifs de valeurs de métriques statistiques d'un profil (P) d'accès mémoire d’une séquence de N instructions précédentes comprenant des valeurs de métriques statistiques, avec des valeurs de consignes : the rules including a first test rule if the memory intensity (Im) is greater than a memory intensity setpoint (Im_c), in which case the choice of the N+1th instruction is a local instruction, and otherwise, the choice of the N+1th instruction is a read access instruction (R) or a write access instruction (W).

2. The method of claim 1, wherein the statistical metrics of the memory access profile of the sequence of the N preceding instructions comprise: - a memory intensity (Im) corresponding to the ratio of the number of read (R) or write (W) access instructions and the total number of instructions N; - a read / memory ratio (Rwr) corresponding to the ratio of read access instructions (W) and memory access instructions (R, W); and - a Shannon access entropy (E) of the memory access profile (P) representing the randomness of the addresses accessed in memory.

3. The method of claim 2, wherein the statistical metrics of the memory access profile of the sequence of the N preceding instructions further comprise an interleaving (Iv) of the read access instructions (R) and the write access instructions (W).

4. Method according to one of the preceding claims, in which the rules comprise rules applied after the first rule, in any order: - a second test rule if the read / memory ratio (Rwr) is greater than a read / memory ratio setpoint (Rwr_c), in which case the choice of the N+1th instruction is a read access instruction (R), and otherwise the choice of the N+1th instruction is a write access instruction (W); - a third test rule if the Shannon entropy E (Ep) of the memory access profile (P) is greater than a Shannon entropy E (Ep) setpoint (Ep_c), in which case the choice of the memory address of the N+1th instruction is chosen so as to lower the entropy E, by taking an address already in use or an address whose distance to the previous one is already known, and otherwise the choice of the memory address of the N+1th instruction is chosen at random;and - a fourth test rule if the interleaving (Iv) is greater than an interleaving instruction (Iv_c), in which case the choice of the N+1th instruction is a read access (R) or write access (W) instruction of the same type as the Nth instruction, and otherwise the choice of the N+1th instruction is a read access (R) or write access (W) instruction of the opposite type to that of the Nth instruction.;

5. Method according to one of the preceding claims further comprising integrating the sequence of Nmax assembly language instructions into an execution loop to generate executable software or software stub.

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