METHOD FOR CUTTING A SEMICONDUCTOR WAVELENGTH
Patent Information
- Application Number
- FR2023002754
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2023-03-23
- Publication Date
- 2026-07-31
- Estimated Expiration
- 2043-03-23
AI Technical Summary
Existing methods for cutting semiconductor wafers with ultra-low dielectric layers face issues such as delamination and moisture penetration, leading to performance degradation, due to prolonged etching and chemical treatments that expose these layers to contamination and corrosion.
A method involving the formation of a hard mask with a vertical dielectric layer to protect ultra-low dielectric layers during cutting, using etching techniques like reactive ion plasma to define cutting paths independently of contact zones, followed by a chemical treatment to clean metal contacts without damaging the dielectric layers.
The method effectively prevents delamination and moisture penetration, ensuring the integrity of ultra-low dielectric layers by protecting them during etching and chemical treatment, thereby maintaining the performance and reliability of semiconductor devices.
Abstract
Description
Title of the invention: METHOD FOR CUTTING A SEMICONDUCTOR WAFER
[0001] Embodiments and implementations relate to microelectronics, in particular the cutting in a semiconductor wafer of semiconductor devices comprising layers of dielectric with ultra-low dielectric constant (better known by the English term “ultra low-k”).
[0002] Semiconductor devices are typically manufactured from a semiconductor wafer, usually referred to as a "wafer", and are separated (usually "singulated" in English) during a cutting step.
[0003] Semiconductor devices typically comprise in particular an interconnection network (usually referred to by the acronym “BEOL” for “Back-End Of Line” in English) on a semiconductor part comprising in particular electronic components such as transistors (also referred to as “Front-End Of Line” in English).
[0004] The interconnection network typically comprises layers of metals and may advantageously comprise layers of dielectric with ultra-low dielectric constant.
[0005] Usually, "ultra-low dielectric constant dielectric material" refers to dielectrics which have a dielectric constant "k" or "kappa" less than 95% of the value of the dielectric constant of silicon oxide.
[0006] The cutting step, during which the semiconductor devices are separated, is typically preceded by a step of forming a hard mask making it possible to expose cutting paths on the semiconductor wafer, i.e. the areas of the wafer in which the cutting is to be carried out.
[0007] The hard mask protects the interconnection network on the rest of the semiconductor wafer from etching. Metal pads of the semiconductor device are exposed by forming an opening in the hard mask, but do not react or react extremely little to the etching of the semiconductor device separation step.
[0008] The cutting paths and the opening in the hard mask to expose the metal pads may be etched simultaneously in the hard mask. However, the etch time to form the cutting paths may be longer than the time sufficient to expose the metal pads, since layers of the interconnect network are also etched in the cutting paths in addition to the hard mask layer. The etching of the opening, when performed at the same time as that forming the cutting paths, can therefore extend onto the exposed metal pads and produce a spraying of the metal ("sputtering" in English) contaminating the vacuum chambers in which the engravings are carried out.
[0009] The etchings to form the cutting paths and expose the metal pads can also be carried out independently. In this case, a thick mask of photosensitive resin is used to delimit the openings exposing the metal pads. However, the mask may have poor adhesion to the wafer, and during the steps of removing this temporary mask, delaminations may appear in the dielectric layers of the interconnection network located at the edge of the cutting paths. In addition, a step of chemical treatment of the metal pads typically takes place after removal of this temporary mask and also risks causing these delaminations. These delaminations, in addition to damaging the dielectric layers of the interconnection network, can cause moisture penetration into these layers which can lead to a drift in the characteristics and performances of the semiconductor devices.The risk of delamination is even more likely when the dielectric layers of the interconnect network are of the "ultra-low dielectric constant" type.
[0010] Thus, there is a need to limit the risk of degradation of dielectric layers with ultra-low dielectric constant.
[0011] According to one aspect, there is provided a method of cutting a semiconductor wafer comprising a semiconductor substrate, an interconnection network provided with layers of metals and at least one dielectric layer with an ultra-low dielectric constant, at least one contact zone and at least one cutting zone, having for example a width of less than 100 pm, the method comprising a formation of a hard mask whose pattern defines the cutting path, the formation of the hard mask comprising: - a step of forming dielectric layers on the wafer in the contact zone and in the cutting zone, - a first step of etching an opening in the cutting area, through said layers of the interconnection network, - a second step of etching an opening in the contact zone revealing a metal contact of the interconnection network, - a chemical treatment step to clean the exposed surface of the metal contact.
[0012] The method further comprises a step of depositing a vertical dielectric layer covering the sides of the opening defining the cutting path, before said chemical treatment for cleaning the metal contact.
[0013] Thus, it is proposed according to this aspect to protect the dielectric layer(s) with ultra-low dielectric constant, which is exposed at the edge of the cutting path of the wafer, in particular during the chemical cleaning treatment of the metal contact. By "forming a hard mask", is meant an implementation of several steps making it possible to shape a mask including a dielectric layer, generally made of silicon nitride, having a role of hard mask itself, but also including one or more passivation layers, generally made of silicon oxide, making it possible to protect the wafer against corrosion for example. The hard mask thus formed by the method according to this aspect makes it possible to avoid, during the chemical treatment of the metal contact, a deterioration of the dielectric layer with ultra-low dielectric constant by delaminations which can allow moisture to penetrate into this layer.
[0014] According to one embodiment, said first etching step is carried out after said step of forming the dielectric layers, and through said dielectric layers and said layers of the interconnection network until the semiconductor substrate is uncovered, so as to shape said pattern of the hard mask defining the cutting path.
[0015] The first etching step is advantageously configured so as not to produce delaminations in the dielectric layers with ultra-low dielectric constant of the interconnection network. In this regard, the etching and masking techniques used to carry out this first etching step may be the same techniques as those provided for the formation of the layers of the interconnection network, and in particular for the formation of the dielectric layers with ultra-low dielectric constant.
[0016] According to one embodiment, the first etching step comprises forming a first dedicated temporary mask, the first temporary mask covering the dielectric layers in the contact zone and uncovering the dielectric layers in the cutting zone, and removing the dielectric layers and said layers of the interconnection network in the cutting zone until the semiconductor substrate is uncovered in the pattern of the hard mask.
[0017] The formation of the first temporary mask, for example conventionally made of photosensitive lithography resin, makes it possible to carry out the etching in the cutting zone independently of the etching in the contact zone. Indeed, the method according to this aspect has made it possible to etch the hard mask in two stages, making it possible to avoid the phenomenon of metal dispersion, without causing the deterioration of the dielectric layers of the interconnection network caused in the opening step uncovering the contact, given that the latter are protected by the vertical dielectric layer.
[0018] According to one embodiment, the step of depositing the vertical dielectric layer comprises depositing a conformal layer of a material chosen from silicon nitride or silicon oxide over the entire wafer.
[0019] The deposition of a conformal layer of silicon nitride or silicon oxide makes it possible to uniformly cover the surface of the wafer, in particular in the cutting zone so that a vertical portion of the layer laterally covers the layers of the interconnection network of the cutting zone. Silicon nitride, in addition to protecting the dielectric layers with ultra-low dielectric constant from the risk of delamination, also offers better adhesion to the temporary mask.
[0020] According to one embodiment, the second etching step comprises: formation of a second dedicated temporary mask covering the cutting area and uncovering the dielectric layers in the contact area, and removal of the dielectric layers until a surface of the metal contact is uncovered.
[0021] The formation of the second temporary mask, for example conventionally made of photosensitive lithography resin, makes it possible to carry out the etching in the contact zone independently of the etching in the cutting zone. The second etching being carried out independently of the first etching according to this aspect, can thus be optimized and parameterized specifically for the manufacture of the metal contact, without causing deterioration of the dielectric layers of the interconnection network, given that the latter are protected by the vertical dielectric layer.
[0022] According to one embodiment, said first etching step is carried out before said step of forming the dielectric layers.
[0023] Thus, the dielectric layers of the hard mask will have the same structure formed inside the etched part during the first etching step as well as above the contact.
[0024] According to one embodiment, the first etching step comprises: forming a third dedicated temporary mask covering the interconnection network in the contact zone and uncovering the interconnection network in the cutting zone, and removing said layers of the interconnection network in the cutting zone until the semiconductor substrate is uncovered in the cutting zone.
[0025] The formation of the third temporary mask, for example conventionally in photosensitive lithography resin, makes it possible to carry out a “pre-etching” in the cutting zone, independently of the etching in the contact zone, removing in advance the layers of the interconnection network in the cutting zone, before the actual formation of the opening of the cutting path.
[0026] According to one embodiment, the step of depositing the vertical dielectric layer is made during said step of forming the dielectric layers.
[0027] Indeed, when said first etching step is carried out before, the formation of the dielectric layers comprises the deposition of the vertical dielectric layer covering the sides of the opening defining the cutting path.
[0028] According to one embodiment, the second etching step simultaneously comprises: - removal of the dielectric layers in the contact zone until said metallic contact is exposed, and - removal of the dielectric layers in the cutting area until the semiconductor substrate is exposed, so as to shape the said pattern of the hard mask defining the cutting path.
[0029] The second etching step makes it possible to simultaneously remove the same thickness of dielectric layers in the contact zone and in the cutting zone in a single step. The second etching can then be completed when the metal contact in the contact zone and the substrate in the cutting zone are uncovered, without exposing the contact zone to prolonged etching and thus not causing metal dispersion in the vacuum chambers.
[0030] According to one embodiment, the second etching step comprises forming a fourth temporary mask having an opening in the contact area defining the uncovered region of the metal contact, and an opening in the cutting area defining the pattern of the hard mask such that a vertical portion of the dielectric layers laterally covers the interconnection network on a flank of the cutting area, in the pattern of the hard mask.
[0031] The dimensions of the opening of the fourth temporary mask in the cutting zone (smaller and located inside the location of the opening of the third temporary mask) make it possible to preserve, at the end of the removal of the dielectric layers, a vertical portion of dielectric layers protecting the interconnection network in the cutting path.
[0032] According to one embodiment, the first etching step is carried out by a reactive ionic type plasma.
[0033] Reactive ion plasma etching, usually referred to by the acronym "RIE" from the English terms "Reactive Ion Etching", is a typical etching method using a chemical reaction between the material to be removed, i.e. that of the interconnection network layers and possibly the dielectric layers, and simultaneously with a bombardment of ions projected in a precise direction, usually perpendicular to the attacked surface. RIE makes it possible in particular to remove material precisely and without risk of damaging the surrounding material layers.
[0034] According to one embodiment, the method further comprises a step of plasma cutting of the semiconductor wafer into semiconductor chip devices separated from each other, in the cutting path defined by the pattern of the hard mask.
[0035] According to another aspect, there is provided a semiconductor chip device delimited by an outer edge, comprising a semiconductor substrate, an interconnection network provided with layers of metals and at least one dielectric layer with an ultra-low dielectric constant, dielectric layers covering the interconnection network and having an opening exposing a metal contact in a contact zone, the interconnection network being covered by a vertical dielectric layer on the outer edge of the chip.
[0036] According to one embodiment, the vertical dielectric layer is adapted to cover the interconnection network on the outer edge of the chip around the entire periphery of the semiconductor device.
[0037] According to one embodiment, the vertical dielectric layer comprises a material chosen from silicon nitride or silicon oxide.
[0038] According to one embodiment, the vertical dielectric layer comprises a vertical portion of the dielectric layers covering the interconnection network on the outer edge of the chip.
[0039] According to another aspect, there is provided a semiconductor wafer, capable of being cut into mutually separate semiconductor chip devices, comprising a semiconductor substrate, an interconnection network provided with metal layers and at least one dielectric layer with an ultra-low dielectric constant, at least one contact area and at least one cutting area, the wafer comprising a hard mask whose pattern defines the cutting path, the hard mask comprising: - dielectric layers arranged on the wafer in the contact area, - an opening in the cutting area defining the cutting path, - an opening in the contact area exposing a metal contact of the interconnection network, the exposed surface of the metal contact, the wafer further comprising a vertical dielectric layer covering the sides of the opening defining the cutting path.
[0040] Other advantages and characteristics of the invention will appear on examining the detailed description of the embodiment and implementation, which is in no way limiting, and the appended drawings in which:
[0041] [Fig.l] ;
[0042] [Fig.2] ;
[0043] [Fig.3] ;
[0044] [Fig.4] ;
[0045] [Fig.5] ;
[0046] [Fig.6] ;
[0047] [Fig.7] ;
[0048] [Fig.8] ;
[0049] [Fig.9];
[0050] [Fig. 10];
[0051] [Fig. 11]; and
[0052] [Fig. 12] schematically illustrate embodiments and implementations of the invention.
[0053] [Fig.l] schematically illustrates the result of a step 100 of a method of cutting a WF semiconductor wafer.
[0054] Step 100 comprises obtaining a WF semiconductor wafer comprising a SUB semiconductor substrate and an INTRCX interconnection network. The INTRCX interconnection network typically comprises at least one ultra-low dielectric constant dielectric layer formed from an “ultra-low dielectric constant dielectric material”, i.e. a material having a “k” or “kappa” dielectric constant less than 95% of the value of the dielectric constant of silicon oxide.
[0055] Furthermore, the WF semiconductor wafer comprises several SL_REG cutting zones and several BOND_REG contact zones. The SL_REG cutting zones may have a width of less than 100 pm and may be distributed over the wafer so as to form a matrix of semiconductor chip devices in which each cutting zone represents a “row” or a “column” of the matrix. In particular, the SL_REG cutting zones are the zones of the wafer where the cutting is carried out to separate the chips from the wafer and the BOND_REG contact zones are the zones of the wafer where electrical connections can be established, for example with a probe. For the sake of simplification, only one SL_REG cutting zone and one BOND_REG contact zone have been shown in [Fig. 1] and the following figures.Without limitation, the WF semiconductor wafer may also include sealing ring formation areas SR_REG1 and SR_REG2.
[0056] The INTRCX interconnection network covers the SUB substrate of the WF wafer. In particular, the INTRCX interconnection network covering the SUB substrate in the BOND_REG, SR_REG1, SR_REG2 areas is provided with metal levels separated by inter-metal dielectric layers having an ultra-low dielectric constant. The INTRCX interconnection network covering the SUB substrate in the SL_REG cutting area comprises at least one dielectric layer with an ultra-low dielectric constant and is free of metal layers.
[0057] The WF semiconductor wafer also includes a PAD metal contact located above the INTRCX interconnection network in the BOND_REG contact area.
[0058] Figures 2 to 6 illustrate steps for forming a hard HM mask suitable for plasma cutting of the WF wafer, according to a first alternative.
[0059] [Fig. 2] schematically illustrates the result of a step 101 of forming dielectric layers D1, D2 and D3. These dielectric layers include in particular two so-called “passivation” layers referenced D1 and D2 but may also include several additional passivation layers. The passivation layers D1 and D2 typically make it possible to protect the layers of materials that they cover against degradation that may be caused by the etching steps or corrosion. In particular, the dielectric layers D1, D2 and D3 are deposited uniformly and successively in the order of the references on the semiconductor wafer WF and more particularly on the interconnection network INTRCX in the cutting zone SL_REG and on the metal contact PAD in the contact zone BOND_REG.
[0060] For example, the material of the dielectric layers D1 and D3 is silicon oxide (SiO2) and the material of the dielectric layer D2 is silicon nitride (SiN). The dielectric layers D1, D2 and D3 together have a thickness Ed.
[0061] [Fig. 3] schematically illustrates the result of a first etching step 102. Step 102 is an etching of an opening in the cutting zone SL_REG through the dielectric layers D1, D2, D3 and through the layers of the interconnection network INTRCX.
[0062] The first etching step 102 more particularly comprises a formation of a first temporary mask RES1 and a removal of the dielectric layers D1, D2, D3 and the layers of the interconnection network INTRCX in the cutting zone SL_REG.
[0063] The temporary mask RES1, which is typically made of photosensitive resin, covers the dielectric layers D1, D2, D3 in the contact zone BOND_REG and uncovers the dielectric layers D1, D2, D3 in the cutting zone SL_REG.
[0064] The dielectric layers D1, D2, D3 and the layers of the interconnection network INTRCX are then removed until the semiconductor substrate SUB is exposed. Advantageously, the removal of these layers is carried out by etching with a reactive ion plasma.
[0065] Reactive ion plasma etching, usually “RIE”, is an etching method, known to those skilled in the art, which makes it possible to remove material precisely and without risk of damaging the surrounding layers of material. In other words, this etching method makes it possible in particular to remove the layers of the network INTRCX interconnects without risk of forming delaminations in the layers of the INTRCX interconnect network located on the sides of the opening in the SL_REG cutting area.
[0066] Indeed, the etching of the layers of the INTRCX interconnection network of step 102 can for example be identical or adjusted in the same way as the etchings made in the inter-metal dielectric regions with ultra-low dielectric constant, during the manufacture of said interconnection network.
[0067] Furthermore, plasma etching has the advantage of forming a cutting path that is narrower than a cutting path that would have been produced indirectly by laser etching (“laser grooving” in English) beforehand.
[0068] The hard mask HM thus has a pattern resulting from the first etching step 102 and defining the cutting path in the cutting zone SL_REG.
[0069] [Fig.4] schematically illustrates the result of a step 103 of depositing a conformal layer of silicon nitride (SiN) over the entire semiconductor wafer WF. In particular, the layer of silicon nitride deposited during step 103 covers the dielectric layer D3 in the contact zone BOND_REG and covers the semiconductor substrate SUB in the cutting zone SL_REG. Such a deposition 103 makes it possible in particular to deposit the layer of silicon nitride in the cutting zone so that a portion of the layer of silicon nitride, corresponding to a vertical dielectric layer BUFF1, covers the sides of the opening defining the cutting path.
[0070] Alternatively, step 103 is a step of depositing a conformal layer of silicon oxide over the entire WF semiconductor wafer.
[0071] The additional layer of silicon nitride or silicon oxide therefore makes it possible to protect an outer edge FL of the layers of the INTRCX interconnection network located on the sides of the cutting path.
[0072] [Fig.5] schematically illustrates the result of a second etching step 104. Step 104 is more particularly an etching of an opening in the BOND_REG contact zone revealing the PAD metal contact.
[0073] The second etching step 104 comprises a formation of a second temporary mask RES2 and a removal of the dielectric layers D1, D2, D3.
[0074] The second temporary mask RES2, typically made of photosensitive resin, covers the cutting area SL_REG and is notably formed on the layer of silicon nitride or silicon oxide deposited in step 103. The layer of silicon nitride is typically a material which offers better adhesion to the second temporary mask RES2 than other types of dielectric material such as silicon oxide or monocrystalline silicon of the substrate SUB. The second temporary mask RES2 further uncovers the dielectric layers D1, D2, D3 as well as the silicon nitride layer in the BOND_REG contact area.
[0075] The dielectric layers D1, D2, D3, the silicon nitride or silicon oxide layer and the layers of the INTRCX interconnection network are then removed until a surface S_PAD of the metal contact PAD is revealed.
[0076] The cutting method also comprises an intermediate step of removing the second temporary mask RES2 (not shown). The second temporary mask RES2 can be removed by wet chemistry not constrained by the risk of damaging the dielectric layers with ultra-low dielectric constant. Indeed, the uniform layer of silicon nitride or silicon oxide which covers the sides of the cutting path makes it possible to protect the outer edge FL of the layers of the INTRCX interconnection network, and therefore makes it possible to prevent delaminations in the layers of the INTRCX interconnection network.
[0077] The second etching, carried out independently of the first etching, can thus be optimized and parameterized specifically for the manufacture of the PAD metal contact, without causing deterioration of the ultra-low constant dielectric layers, given that the latter are protected by the vertical dielectric layer BUFF1.
[0078] [Fig.6] schematically illustrates the result of a chemical treatment step 105. The chemical treatment is carried out after the removal of the second temporary mask RES2 and typically uses a dioxygen (O2) plasma adapted for cleaning the surface S_PAD of the metal contact PAD.
[0079] Figures 7 to 10 illustrate steps of forming the HM hard mask of the plasma wafer cutting process, according to a second alternative.
[0080] [Fig.7] schematically illustrates the result of a first etching step 201 carried out from the WF wafer described previously in relation to [Fig.l]. Step 201 is an etching of an opening in the SL_REG cutting zone through the layers of the INTRCX interconnection network.
[0081] The first etching step 201 comprises a formation of a third temporary mask RES3 and a removal of the layers of the interconnection network INTRCX.
[0082] The third temporary mask RES3, typically made of photosensitive resin, covers the INTRCX interconnection network in the BOND_REG contact area and uncovers the INTRCX interconnection network in the SL_REG cutting area.
[0083] The layers of the INTRCX interconnection network are then removed until the SUB substrate is exposed in the SL_REG cutting zone. Advantageously, the removal of these layers is carried out by etching with a reactive ion plasma.
[0084] [Fig. 8] illustrates the result of a step 202 of forming the dielectric layers D1, D2 and D3. The dielectric layers D1 and D2 represent the so-called “passivation” layers previously described with the same references in relation to the Figures 2 to 6 without however being limiting in terms of the number of dielectric layers. The dielectric layers D1, D2, D3 may have materials and a common thickness Ed identical to those described previously in relation to [Fig.2]. More particularly, the dielectric layers D1, D2, D3 are formed uniformly on the semiconductor wafer so that the thickness Ed is equivalent, or even equal in the cutting zone SL_REG and in the contact zone BOND_REG.
[0085] In particular, a vertical portion of the dielectric layers D1, D2 and D3 covers the edge FL of the layers of the interconnection network INTRCX located on the sides of the opening of the cutting path made in step 201. The vertical portion of the dielectric layers D1, D2, D3 corresponds to the vertical dielectric layer BUFF2, which will have the same function of protecting the outer edge FL of the layers of the interconnection network INTRCX described previously in relation to [Fig.4].
[0086] The dielectric layers D1, D2, D3 of the hard mask HM will have the same structure formed inside the part etched during the first etching step 201 as well as above the PAD contact.
[0087] [Fig.9] schematically illustrates the result of a second etching step 203.
[0088] The second etching step 203 comprises forming a fourth temporary mask RES4 on the dielectric layers D1, D2, D3 of the wafer. The fourth temporary mask RES4, typically made of resin, has an opening in the contact area BOND_REG and an opening in the cutting area SL_REG. More particularly, the fourth temporary mask RES4 covers the vertical portion of the dielectric layers D1, D2 and D3 in the cutting area SL_REG.
[0089] The second etching step 203 comprises a removal of the dielectric layers D1, D2, D3 in the contact area BOND_REG and in the cutting area SL_REG. The dielectric layers D1, D2, D3 under the opening of the mask RES4 in the contact area BOND_REG are removed until the metal contact PAD is exposed and those under the opening of the mask RES4 in the cutting area SL_REG are removed until the substrate SUB is exposed.
[0090] Thus, an equal thickness Ed of dielectric layers D1, D2, D3 is removed, in the same etching step, in the cutting zone SL_REG and in the contact zone BOND_REG while preserving the vertical portion of dielectric layers D1, D2, D3 corresponding to the vertical dielectric layer BUFF2.
[0091] The second etching step 203 therefore ends when the metal contact PAD in the BOND_REG contact zone and the substrate SUB in the SL_REG cutting zone are uncovered without exposing the BOND_REG contact zone to prolonged etching and thus not causing metal dispersion in the vacuum chambers.
[0092] In addition, the dimensions of the opening of the fourth temporary mask RES4 in the cutting zone SL_REG (smaller and located inside the location of the opening of the third temporary mask RES3) make it possible to preserve, at the end of the removal of the dielectric layers, a vertical portion of dielectric layers protecting the interconnection network INTRCX in the cutting path.
[0093] The hard mask HM thus has a pattern resulting from the second etching step 203 and defining the cutting path in the cutting zone SL_REG.
[0094] [Fig. 10] schematically illustrates a result of a chemical treatment step 204. Step 204 is identical to the chemical treatment step described previously in relation to [Fig. 6]. The vertical part CDV2 of the dielectric layers D1, D2, D3 protects the outer edge FL of the interconnection network INTRCX from the dioxygen plasma used for cleaning the surface S_PAD of the metal contact PAD.
[0095] [Fig. 11] illustrates an example of a DISP semiconductor chip device obtained after implementing the cutting method according to the first alternative described previously in relation to Figures 2 to 6.
[0096] [Fig. 12] illustrates an example of a DISP semiconductor chip device obtained after implementing the cutting method according to the second alternative described previously in relation to Figures 7 to 11.
[0097] In both alternatives, the cutting method further comprises a step of plasma dicing the semiconductor wafer WF into semiconductor chip devices DISP separated from each other in the cutting path SL_REG defined by the pattern of the hard mask HM.
[0098] The semiconductor chip device DISP, as shown in [Fig. 11], is delimited by an outer edge FL of the chip. The semiconductor chip device DISP comprises a semiconductor substrate SUB and an interconnection network INTRCX provided with metal levels separated by intermetal dielectric layers having an ultra-low dielectric constant. The interconnection network INTRCX is disposed on the semiconductor substrate SUB. The semiconductor chip device DISP also comprises dielectric layers D1, D2, D3 covering the interconnection network INTRCX and exposing a metal contact PAD in a contact area BOND_REG.
[0099] The interconnection network INTRCX is covered by a vertical dielectric layer CDV1, for example by a layer of silicon nitride (or a layer of silicon oxide depending on the material used during step 103 previously described in relation to [Fig.4]), on the outer edge FL of the chip.
[0100] In an alternative illustrated in [Fig. 12], the vertical dielectric layer CDV2 is a vertical portion of the dielectric layers D1, D2, D3 covering the interconnection network INTRCX on the outer edge FL of the chip.
[0101] Furthermore, the vertical dielectric layer CDV1, CDV2 extends over the outer edge FL of the chip from the level of the substrate SUB, preferably along the entire length of the interconnection network INTRCX, and has an arc-shaped external face. Advantageously, the vertical dielectric layer CDV1, CDV2 is adapted to cover the interconnection network INTRCX on the outer edge FL of the chip, around the entire periphery of the semiconductor device DISP.
Claims
Claims
1. Method for cutting a semiconductor wafer comprising a semiconductor substrate (SUB), an interconnection network (INTRCX) provided with metal layers and at least one dielectric layer with ultra-low dielectric constant, at least one contact area (BOND_REG) and at least one cutting area (SL_REG), the method comprising forming a hard mask (HM) whose pattern defines the cutting path, the formation of the hard mask (HM) comprising: - a step of forming (101, 202) dielectric layers (D1, D2, D3) on the wafer in the contact area (BOND_REG) and in the cutting area (SL_REG), - a first step of etching (102, 201) an opening in the cutting area (SL_REG), through said layers of the interconnection network (INTRCX), - a second step of etching (104, 203) an opening in the contact area (BOND_REG) revealing a metal contact (PAD) of the interconnection network (INTRCX),- a chemical treatment step (105, 204) for cleaning the exposed surface of the metal contact (PAD), the method further comprising: - a step of depositing (103, 202) a vertical dielectric layer (BUFF1, BUFF2) covering the sides of the opening defining the cutting path (SL_REG), before said chemical treatment for cleaning the metal contact (PAD).,
2. Method according to claim 1, wherein said first etching step (102) is done after said step of forming the dielectric layers (101), and through said dielectric layers (D1, D2, D3) and said layers of the interconnection network (INTRCX) until exposing the semiconductor substrate (SUB), so as to shape said pattern of the hard mask (HM) defining the cutting path.
3. Method according to claim 2, in which the first etching step (102) comprises: - a formation of a first dedicated temporary mask (RES1), the first temporary mask covering the dielectric layers (D1, D2, D3) in the contact zone (BOND_REG) and uncovering the dielectric layers (D1, D2, D3) in the cutting zone (SL_REG), and - removal of the dielectric layers (Dl, D2, D3) and said layers of the interconnection network (INTRCX) in the cutting zone (SL_REG) until the semiconductor substrate (SUB) is discovered in the pattern of the hard mask.
4. Method according to one of claims 1 to 3, in which the step of depositing (103) the vertical dielectric layer (BUFF1) comprises depositing a conformal layer of a material chosen from silicon nitride or silicon oxide over the entire wafer.
5. Method according to claims 1 to 4, in which the second etching step (104) comprises: - a formation of a second dedicated temporary mask (RES2) covering the cutting zone (SL_REG) and uncovering the dielectric layers (Dl, D2, D3) in the contact zone (BOND_REG) and - a removal of the dielectric layers (Dl, D2, D3) until a surface of the metal contact (S_PAD) is uncovered.
6. The method of claim 1, wherein said first etching step (201) is performed before said dielectric layer forming step (202).
7. Method according to claim 6, in which the first etching step (201) comprises: - a formation of a third dedicated temporary mask (RES3) covering the interconnection network (INTRCX) in the contact zone (BOND_REG) and uncovering the interconnection network (INTRCX) in the cutting zone (SL_REG), and - a removal of said layers of the interconnection network (INTRCX) in the cutting zone (SL_REG) until uncovering the semiconductor substrate (SUB) in the cutting zone (SL_REG).
8. Method according to claims 6 or 7, wherein the step of depositing the vertical dielectric layer (BUFF2) is done during said step of forming the dielectric layers (202).
9. Method according to claims 6 to 8, in which the second etching step (203) simultaneously comprises: - a removal of the dielectric layers (Dl, D2, D3) in the contact zone (BOND_REG) until said metal contact (PAD) is uncovered, and - a removal of the dielectric layers (Dl, D2, D3) in the cutting zone (SL_REG) until the semiconductor substrate (SUB) is uncovered, so as to shape said pattern of the hard mask (HM) de- finishing the cutting path.
10. Method according to claims 8 and 9 taken in combination, in which the second etching step (203) comprises a formation of a fourth temporary mask (RES4) having an opening in the contact area (BOND_REG) defining the uncovered region of the metal contact (PAD), and an opening in the cutting area (SL_REG) defining the pattern of the hard mask (HM) so that a vertical portion of the dielectric layers (Dl, D2, D3) laterally covers (FL) the interconnection network (INTRCX) on a flank of the cutting area (SL_REG), in the pattern of the hard mask (HM).
11. Method according to one of the preceding claims, in which the first etching step (102, 201) is carried out by a reactive ion type plasma.
12. A method according to any one of claims 1 to 11, further comprising a step of plasma cutting the semiconductor wafer into separate semiconductor chip devices (DISP), in the cutting path (SL_REG) defined by the hard mask pattern.
13. Method according to any one of the preceding claims, in which said at least one cutting zone (SL_REG) has a width (Lsl) less than 100 pm.
14. Semiconductor chip device (DISP) delimited by an outer edge, comprising a semiconductor substrate (SUB), an interconnection network (INTRCX) provided with metal layers and at least one dielectric layer with ultra-low dielectric constant, dielectric layers (Dl, D2, D3) covering the interconnection network (INTRCX) and having an opening revealing a metal contact (PAD) in a contact area (BOND_REG), the interconnection network (INTRCX) being covered by a vertical dielectric layer (CDV1, CDV2) on the outer edge (FL) of the chip.
15. Device according to claim 14, wherein the vertical dielectric layer (CDV1, CDV2) is adapted to cover the interconnection network (INTRCX) on the outer edge (FL) of the chip around the entire periphery of the semiconductor chip device (DISP).
16. Device according to claim 14 or 15, wherein the vertical dielectric layer (CDV1) comprises a material selected from silicon nitride or silicon oxide.
17. Device according to claim 14 or 15, wherein the vertical dielectric layer (CDV2) comprises a vertical portion of the dielectric layers (D1, D2, D3) covering the interconnection network (INTRCX) on the outer edge (FL) of the chip.
18. Semiconductor wafer, capable of being cut into mutually separate semiconductor chip devices (DISP), comprising a semiconductor substrate (SUB), an interconnection network (INTRCX) provided with metal layers and at least one dielectric layer with ultra-low dielectric constant, at least one contact area (BOND_REG) and at least one cutting area (SL_REG), the wafer comprising a hard mask (HM) whose pattern defines the cutting path, the hard mask (HM) comprising: - dielectric layers (Dl, D2, D3) arranged on the wafer in the contact zone (BOND_REG), - an opening in the cutting area (SL_REG) defining the cutting path, - an opening in the contact zone (BOND_REG) revealing a metal contact (PAD) of the interconnection network (INTRCX), the exposed surface of the metal contact (PAD), the wafer further comprising a vertical dielectric layer (CDV1, CDV2) covering the sides of the opening defining the cutting path.