Electronic device

Abstract

Electronic Device This description relates to a device comprising trenches (44), each trench (44) comprising a conductive element configured to electrically connect the gate fingers (35) of transistors (26), located on the side of a first face of a first layer, to a second layer extending along the side of a second face of the first layer. Figure for the abstract: Fig. 3

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and more particularly to electronic devices comprising transistors. Prior art

[0002] Many electronic devices comprise transistors and more particularly common-gate transistors. Common-gate transistors are understood to mean transistors whose gates are connected, preferably connected, together, in such a way that the transistors are controlled by the same control voltage. For example, such transistors may be elementary transistors, that is to say small transistors, all having the same dimensions, connected together so as to form the equivalent of a transistor of larger dimensions. Thus, the gates of the elementary transistors are connected, preferably connected, together, the drains of the elementary transistors are connected, preferably connected, together, and the sources of the elementary transistors are connected, preferably connected, together.

[0003] There is thus a need to ensure that the transistors receive the same control voltage and receive said control voltage simultaneously. Summary of the invention

[0004] One embodiment provides a device comprising trenches, the trenches each comprising a conductive element configured to electrically connect the transistor gate fingers, located on the side of a first face of a first layer, to a second layer extending on the side of a second face of the first layer.

[0005] Another embodiment provides a method of manufacturing a device comprising forming trenches, the trenches each comprising a conductive element configured to electrically connect the transistor gate fingers, located on the side of a first face of a first layer, to a second layer extending on the side of a second face of the first layer.

[0006] According to one embodiment, the second layer is configured to be biased at the control voltage of the transistors.

[0007] According to one embodiment, the transistors are arranged in rows, the transistors of the same row being connected together by their gate by the same finger, the rows being arranged in columns, the columns being separated two by two by a trench, the conductive element of each trench separating two columns being connected to a end of each of the fingers of the two columns.

[0008] According to one embodiment, each column is located between two trenches, each finger being connected, by one end, to the conductive element of one of the two trenches, and, by another end, to the conductive element of the other of the two trenches.

[0009] According to one embodiment, the first layer is made of GaN, AIN or AlGaN.

[0010] According to one embodiment, the device comprises a semiconductor substrate of the side of the second face of the first layer, the substrate constituting the second layer.

[0011] According to one embodiment, each trench comprises a cavity passing through the first layer, the bottom of the cavity being formed by the substrate, and the conductive element comprising a third conductive layer extending over the walls and the bottom of the cavity.

[0012] According to one embodiment, the device comprises a semiconductor substrate on the side of the second face of the first layer, the face of the substrate furthest from the first layer being covered with a fourth conductive layer, the fourth layer constituting the second layer.

[0013] According to one embodiment, the third layer is made of metal.

[0014] According to one embodiment, each trench comprises a cavity passing through the first layer, the bottom of the cavity being located at the face of the substrate closest to the first layer, the conductive element comprising a third conductive layer extending over the walls and the bottom of the cavity and a portion located in the substrate, in contact with the third layer and in contact with the fourth layer.

[0015] According to one embodiment, the third layer is separated from the first layer by a fifth insulating layer.

[0016] According to one embodiment, the substrate is made of silicon or carbon-based silicon.

[0017] According to one embodiment, each conductive element is connected to the fingers by tracks and vias of an interconnection network. Brief description of the drawings

[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0019] [Fig.l] schematically represents an example of a transistor;

[0020] [Fig.2] schematically represents an example of an electronic device;

[0021] [Fig.3] schematically represents an embodiment of an electronic device electronics;

[0022] [Fig.4] shows in more detail a part of an embodiment of an electronic device;

[0023] [Fig.5] shows in more detail another part of the embodiment of the [Fig.4] ;

[0024] [Fig.6] shows in more detail a part of another embodiment of an electronic device; and

[0025] [Fig.7] shows in more detail another part of the embodiment of [Fig.6]. Description of the embodiments

[0026] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0027] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0028] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0030] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0031] [Fig.l] schematically represents an example of a transistor 10 of an electronic device. The electronic device comprises for example a chip in which the transistor is formed.

[0032] Transistor 10 is a gallium nitride (GaN) based transistor. Transistor 10 is preferably an insulated gate field effect transistor (MOSFET or Metal Oxide Semiconductor Field Effect Transistor). Transistor 10 may alternatively be a Schottky gate transistor.

[0033] The device comprises a substrate 12. The transistor 10 is formed on the substrate 12. The substrate 12 is made of a semiconductor material, for example silicon.

[0034] The device comprises a layer 14, made of gallium nitride. The layer 14 rests on, and is preferably in contact with, an upper face of the substrate 12. The layer 14 is for example formed by epitaxy from the substrate 12. The layer 14 can alter natively correspond to a stack of layers comprising a GaN layer and layers of AIN and AlGaN.

[0035] Layer 14 comprises for example the source and drain regions of transistor 10. The different regions of transistor 10 are not shown in [Fig.l].

[0036] The device comprises a contact element 16, for example made of metal, resting on, and preferably in contact with, the source region of the transistor 10. The element 16 rests for example on, for example in contact with, the layer 14, more precisely with the source region located in the layer 14. The element 16 preferably rests on, preferably in contact with, the upper face of the layer 14.

[0037] Similarly, the device comprises a contact element 18, for example made of metal, resting on, and preferably in contact with, the drain region of the transistor 10. The element 18 rests for example on, for example in contact with, the layer 14, more precisely with the drain region located in the layer 14. The element 18 preferably rests on, preferably in contact with, the upper face of the layer 14.

[0038] The transistor 10 further comprises a gate region 20. The region 20 is preferably made of a semiconductor material, for example gallium nitride, for a Schottky gate, or of an insulating material, for example SiO2, SiN or Al2O3, for an insulated gate. The region 20 preferably rests on, and is in contact with, the upper face of the layer 14. The gate region is for example located between the elements 16 and 18.

[0039] The device further comprises a contact element 22, for example made of metal, resting on, and preferably in contact with, the gate region 20 of the transistor 10.

[0040] The lower face of the substrate 12, that is to say the face opposite the upper face, is for example covered by, preferably in contact with, a conductive layer not shown, for example a metal layer.

[0041] The device further comprises an interconnection network, not shown. In other words, the device comprises insulating layers, not shown, covering the upper face of the device, and therefore covering the upper face of the layer 14, the region 20 and the elements 16, 18, 22. Said layers, not shown, comprise conductive tracks and conductive vias, not shown, making it possible to provide connections between the elements of the device or between the device and an external device.

[0042] [Fig. 2] schematically represents an example of an electronic device 24. More specifically, [Fig. 2] schematically represents a top view of a set of transistors 26. [Fig. 2] represents an example of an arrangement of transistors in an electronic device 24, and more specifically illustrates the connections of the transistor gates.

[0043] The device 24 comprises a plurality of transistors 26. The transistors 26 cor correspond for example to transistors such as transistor 10 of [Fig.l]. However, transistors 26 may be of another type of gallium nitride-based transistors, i.e. another type of transistors whose drain and source regions are located in a gallium nitride layer. Thus, transistor 26 is for example a MOSFET transistor or a p-GaN gate transistor, i.e. a Schottky gate transistor.

[0044] The transistors 26 are, for example, elementary transistors. The transistors 26 are, for example, all identical. The transistors 26 have a common gate. In other words, the gates of all the transistors 26 are connected, preferably connected, to each other. The drains of all the transistors are, for example, connected, preferably connected, to each other. The sources of all the transistors are, for example, connected, preferably connected, to each other.

[0045] In [Fig.2], each transistor 26 is represented by a source contact element 28, a drain contact element 30 and a gate contact element 32. The elements 28 and 30 correspond for example respectively to the element 16 of [Fig.l] and to the element 18 of [Fig.l]. The element 32 corresponds for example to the element 22 of [Fig.l],

[0046] The transistors 26 of the device are arranged in lines 34. More precisely, the transistors 26 of a line 34 are arranged in such a way that the pads 28 and 30 respectively form parallel lines. The different lines 34 are arranged so as to be parallel to each other.

[0047] The contact elements 32 of the transistors 26 of the same row 34 are constituted by portions of the same conductive track 35, in other words of the same finger 35. In other words, the device comprises, for each row 34, a conductive track 35, corresponding for example to a conductive track of the interconnection network of the device. The track 35 extends opposite each transistor and is connected, preferably connected, to the gate regions of each transistor 26 of the corresponding row 34. The transistors of the same row 34 are thus connected, preferably connected, together by the gate.

[0048] In the example of [Fig.2], the device 24 comprises a pad 36 for applying the control voltage, i.e. the voltage supplied to all the gates of the transistors 26. Thus, the pad 36 receives the control voltage from a voltage source not shown.

[0049] The device 24 further comprises a conductive track 38. The track 38 is connected, preferably connected, to the pad 36. For example, the track 38 is a conductive track, or metallization, of the interconnection network of the device. Thus, the track 38 is for example connected to the pad 36 by conductive vias. The track 38 is thus polarized by the control voltage.

[0050] The track 38 extends in a first direction. The fingers extend in another direction, for example a direction perpendicular to the direction of the track 38 in the plane of [Fig.2]. The lines 34 of transistors 26 extend in the second direction.

[0051] Track 38 is connected, preferably connected, to all tracks 35, so as to provide the control voltage to all transistors 26.

[0052] During operation of the device, the biasing of the gates of the transistors 26 is provided by the pad 36 and the tracks 35 and 38. However, in devices having a large number of transistors and a large number of fingers, there is a significant delay between the moment of application of the control voltage to the pad 36, and thus to the end of the track 38 close to the pad 36 and the moment when the other end of the track 38 is biased. Such a delay, caused by the resistivity of the track 38, can be problematic, particularly during current peaks which can then be concentrated on a small number of lines 34 instead of being distributed over all the transistors.

[0053] [Fig. 3] schematically represents an embodiment of an electronic device 40. More specifically, [Fig. 3] schematically represents a top view of a set of transistors 26. [Fig. 3] represents an example of arrangement of transistors in an electronic device, and more specifically illustrates the connections of the transistor gates.

[0054] Like the device 24 of [Fig. 2], the device 40 comprises a plurality of transistors 26. The transistors 26 correspond for example to transistors such as the transistor 10 of [Fig. 1]. However, the transistors 26 may be of another type of transistor based on gallium nitride or a type of transistor based on AlGaN or aluminum nitride (AIN), that is to say of another type of transistor whose drain and source regions are located in a layer of gallium nitride.

[0055] As in [Fig.2], the transistors 26 are for example elementary transistors. The transistors 26 are for example all identical. The transistors 26 have a common gate. In other words, the gates of all the transistors 26 are connected, preferably connected, to each other.

[0056] In [Fig. 3], as in [Fig. 2], each transistor 26 is represented by a source contact element 28, a drain contact element 30 and a gate contact element 32. The elements 28 and 30 correspond for example respectively to the element 16 of [Fig. 1] and to the element 18 of [Fig. 1]. The element 32 corresponds for example to the element 22 of [Fig. 1].

[0057] The device 40 comprises, like the device 24 of [Fig. 2], lines 34 of transistors 26. As in [Fig. 2], the transistors 26 of a line 34 are arranged in such a way that the pads 28 and 30 respectively form parallel lines. different lines 34 are arranged so as to be parallel to each other.

[0058] The contact elements of the transistors 26 of the same line 34 are constituted by portions of the same conductive track 35, in other words of the same finger 35. In other words, the device comprises, for each line 34, a conductive track 35, corresponding for example to a conductive track of the interconnection network of the device. The track 35 extends opposite each transistor and is connected, preferably connected, to the gate regions of each transistor 26 of the corresponding line 34. The transistors of the same line 34 are thus connected, preferably connected, together by the gate.

[0059] In the example of [Fig. 3], each row 34 comprises three transistors so as to clarify the representation. The rows may comprise any number of transistors 26, for example at least ten transistors. The drains of all the transistors of a row are for example connected, preferably connected, to each other. The sources of all the transistors of a row are for example connected, preferably connected, to each other.

[0060] In the example of [Fig. 3], the lines 34 of transistors are arranged in columns 4L. The columns 41 extend, for example, in a direction perpendicular to the direction in which the line extends. Thus, the tracks 35 of the lines of the same column 41 are parallel to each other and are separated from each other by the lines of elements 28 or the lines of elements 30. The columns 41 are parallel to each other. The device comprises at least one column, for example at least three columns.

[0061] In the example of [Fig. 3], the device 40 comprises a pad 42 for applying the control voltage, i.e. the voltage supplied to all the gates of the transistors 26. Thus, the pad 42 receives the control voltage from a voltage source not shown. The pad 42 is preferably located outside the region in which the transistors 26 are located. More generally, the device may comprise several pads 42, for example located at different locations around the transistors 26.

[0062] The device comprises a conductive or semiconductive layer, not shown in [Fig. 3], extending on the lower side of the gallium nitride layer in which the source and drain regions are located. Thus, the gate region, i.e. region 20 in the example of [Fig. 1], is preferably separated from said conductive or semiconductive layer by said gallium nitride layer. Track 35 is also preferably separated from said conductive or semiconductive layer by said gallium nitride layer.

[0063] The conductive or semiconductive layer not shown preferably extends opposite the entire region of the device in which the transistors are located. Thus, all the transistors are located opposite said layer.

[0064] The conductive or semiconductive layer, not shown, is biased to the control voltage. The conductive or semiconductive layer is, for example, connected, preferably to the pad 42, more precisely to a lower end of the pad 42. Thus, the pad 42 preferably extends from the upper side of the chip in which the transistors are formed to the lower side of the chip. The upper end of the pad 42 is, for example, connected, preferably to the interconnection network so as to receive the control voltage. The lower end of the pad 42 is connected, preferably connected, to the conductive or semiconductive layer, which is thus biased to the control voltage.

[0065] According to another embodiment, the device 40 does not comprise a pad 42. The conductive or semiconductive layer not shown is then connected to the source of the control voltage without passing through the substrate 12, for example by contact with another device. The conductive or semiconductive layer not shown is for example connected to the source of the control voltage through the layer 54 via the cavity 56.

[0066] The device 40 comprises trenches 44. Each column 41 is separated from the neighboring column 41 by a trench 44. Preferably, each column is located between two trenches 44. Each trench 44 preferably extends along all the sets 34 of transistors 26. In other words, each trench 44 extends from the track 35 of the first set 34 of the column to the track 35 of the last set 34 of the column.

[0067] Each trench 44 passes through at least the gallium nitride layer in which the source and drain regions are located. Each trench 44 reaches the conductive or semiconductor layer.

[0068] Each trench 44 comprises a conductive element extending to the semiconductor or conductive layer and being connected, directly or by conductive tracks and conductive vias of the interconnection network, to the tracks 35 of the sets 34 of the columns 41 located on either side of the trench 44. Thus, at least one end of each track 34 is connected, preferably connected, to the conductive or semiconductor layer by a conductive element of a trench 44.

[0069] Preferably, each column is located between two trenches 44. Thus, the two ends of each track 35 are preferably connected, preferably connected, to the conductive or semiconductive layer by conductive elements of the trenches 44 located on either side of the column 4L.

[0070] The conductive element of each trench 44 is electrically insulated from the gallium nitride layer.

[0071] The polarization of the conductive or semiconductive layer is preferably carried out by several pads 42. Thus, the whole of said layer is polarized at the control voltage. The set of transistors 26 is thus closer to a trench 44, providing the control voltage, than the transistors 26 of [Fig. 2] are to pad 36. Although there may be a short delay between the transistors on the same row 34, this delay is much less than the delay in [Fig. 2]. In addition, the transistors 26 located at the same locations on different rows are at the same distance from the conductive or semiconducting layer.

[0072] [Fig. 4] shows in more detail a part of an embodiment of an electronic device 50. More specifically, [Fig. 4] shows a sectional view of a trench 44 as described in [Fig. 3], for example along a plane AA of [Fig. 3], located in a chip of the device 50.

[0073] The device 50, and more precisely the chip, comprises a substrate 52. The substrate 52 corresponds for example to the substrate 12 of [Fig.l]. The substrate 12 is preferably made of a semiconductor material, for example silicon or carbon silicon. The substrate 52 is made of a material different from the layer 54.

[0074] The device 50 comprises for example a conductive layer not shown extending on a lower face of the substrate 52.

[0075] The device 50 comprises a layer 54 of gallium nitride. The layer 54 has, for example, a thickness greater than 4 μm. The layer 54 corresponds, for example, to the layer 14 of [Fig. 1]. Thus, the source and drain regions of the transistors 26 of [Fig. 3] are preferably located in the layer 54. The layer 54 extends over an upper face of the substrate 52. The layer 54 is, for example, in contact with the substrate 52.

[0076] The layer 54 comprises a cavity 56 extending at least from an upper face of the layer 54 to a lower face of the layer 54. The cavity 56 reaches the upper face of the substrate 52. The bottom of the cavity 56 is thus constituted by a portion of the upper face of the substrate 52.

[0077] The device 50 comprises an insulating layer 58. The layer 58 covers the side walls of the cavity 56. The layer 58 covers, for example, a peripheral part of the portion of the substrate 52 constituting the bottom of the cavity. A central part of the portion of the substrate 52 constituting the bottom of the cavity is not covered by the layer 58. The layer 58 covers, for example, at least partially the upper face of the layer 54, for example at least the portion of the upper face of the layer 54 surrounding the cavity 56.

[0078] The device 50 comprises an interconnection network. In other words, the device 50 comprises a stack 60 of insulating layers covering the upper face of the chip. The insulating layers of the stack 60 comprise conductive tracks and conductive vias making it possible to provide connections between the elements of the device 50 or between the device 50 and an external device.

[0079] The device 50 comprises a conductive element 62, for example made of metal. The conductive element 62 corresponds for example to a metallization level MO of an interconnection network, that is to say corresponds for example to the level of conductive tracks closest to the layer 54.

[0080] The element 62 extends at least over the entire height of the trench 56. More precisely, the element 62 reaches the bottom of the cavity 56 and is in contact with the substrate 52 via the central part of the portion of the substrate 52 constituting the bottom of the cavity. The element 62 extends over the walls of the cavity, and more precisely, over the layer 58 covering the walls of the cavity. Furthermore, the element 62 extends for example over a portion of the upper face of the layer 54 around the cavity 56, more precisely over the layer 58 covering a portion of the upper face of the layer 54 around the cavity 56, preferably on either side of the trench 44. The element 62 is preferably not in contact with the layer 54. Preferably, the element 62 is entirely separated from the layer 54 by the insulating layer 58.

[0081] In the example of [Fig.4], the element 62 does not fill the cavity 56, the element 62 being covered, in the cavity 56, by an insulating material. Alternatively, the element 62 can fill the cavity 56 above the layer 58.

[0082] The device 50 further comprises a track 64. The track 64 is for example located in a metallization level higher than the level of the element 62, for example the level ML. The track 64 preferably extends over the entire length of the trench 44. Preferably, the entire trench 44 is thus covered by the track 64. The element 62 and the track 64 are connected by vias 66. For example, the element 62 and the track 64 are connected by vias located on either side of the trench, for example, by substantially as many vias 66 on one side of the trench as on the other side of the trench.

[0083] In [Fig.4], the device 50 comprises for example a conductive track 68. The track 68 corresponds for example to a finger 35 of [Fig.3]. The track 38 is for example located in the metallization level MO. The track 68 extends for example over, and for example in contact with, the layer 58.

[0084] In the example of [Fig.4], only one track 68 is shown. In practice, there are as many tracks 68 as there are fingers 35, that is to say as many as there are lines 34. For the trenches 44 located between two lines 34, the track 64 is connected, by vias 66, to the fingers 35 on either side of the trench.

[0085] Alternatively, element 62 may not be connected to track 68 by track 64 and vias 66. Track 68 may be a continuation of element 62 and therefore be in contact with element 62.

[0086] The method of manufacturing the device 50 comprises for example: - the formation of substrate 52; - the possible formation of the conductive layer not shown on the in- face lower part of the substrate 52; - the formation, for example by epitaxy, of layer 54; - etching the layer 54 so as to form the cavity 56; - the formation of layer 58 over the entire structure; - etching the portion of layer 58 located in the center of the bottom of cavity 56; - the deposit of the conductive element 62; - annealing so as to form an electrical connection between the element 62 and the substrate 52; and - the formation of the interconnection network.

[0087] [Fig. 5] shows in more detail another part of the device 50 of the embodiment of [Fig. 4]. More precisely, [Fig. 5] shows a pad 42 of [Fig. 3] and a pad 70 for applying the drain voltage. The pad 70 is not shown in [Fig. 3]. The pads 42 and 70 are located on the same chip, and in the same device 50 as the structure of [Fig. 4]. Thus, the structure of [Fig. 5] includes elements of [Fig. 4]. The structure of [Fig. 5] thus includes the substrate 52, the layer 54, and the layer 58. The structure of [Fig. 5] further includes the interconnection network, not shown. In other words, the structure of [Fig.5] comprises the stack 60 of insulating layers, not shown in [Fig.5], the stack comprising conductive tracks and conductive vias.

[0088] The device 50 comprises a cavity 72 in the layer 54. The cavity 72 extends at least from an upper face of the layer 54 to a lower face of the layer 54. The cavity 72 reaches the upper face of the substrate 52. The bottom of the cavity 72 is thus constituted by a portion of the upper face of the substrate 52.

[0089] The layer 58 covers the side walls of the cavity 72. The layer 58 covers, for example, a peripheral part of the portion of the substrate 52 constituting the bottom of the cavity. At least a central part of the portion of the substrate 52 constituting the bottom of the cavity 72 is not covered by the layer 58. The layer 58 covers, for example, at least partially the upper face of the layer 54, for example, at least the portion of the upper face of the layer 54 surrounding the cavity 72.

[0090] The device 50 comprises, in [Fig. 5], a pad 42, as described in relation to [Fig. 3]. The pad 42 is preferably made of a conductive material, for example metal, for example the same material as the element 62 of [Fig. 4]. The pad 42 preferably fills the cavity 72 entirely. The pad 42 preferably covers the portions of the layer 58 located in the cavity 72. The pad 42 is in contact with the substrate 52, more precisely with the portion of the substrate 52 forming the bottom of the cavity 72. The pad preferably extends from the upper face of the substrate 52 to at least the level of the opening of the cavity 72, preferably up to a level higher than the opening of the cavity 72. Thus, the pad 42 comprises a portion located outside the cavity 72.

[0091] The pad 42 is connected, preferably connected, to a voltage source providing the control voltage for the transistors 26 of the lines 34 of [Fig. 3]. The pad 42 is for example connected, preferably connected, to said voltage source by the interconnection network not shown, more precisely by conductive tracks and conductive vias of the interconnection network not shown.

[0092] The device 50 further comprises the pad 70. The pad 70 is made of a conductive material, for example metal, for example the same material as the pad 42, for example the same material as the element 62 of [Fig. 4]. The pad 70 passes through the layer 58 to reach the layer 54. The pad 70 is thus in contact with the layer 54, preferably with the upper face of the layer 54.

[0093] The pad 70 is connected, preferably connected, to a voltage source providing the drain voltage of the transistors 26 of the lines 34 of [Fig. 3]. The pad 70 is for example connected, preferably connected, to said voltage source by the interconnection network not shown, more precisely by conductive tracks and conductive vias of the interconnection network not shown.

[0094] The device 50 comprises, for example, several pads 42 as described in relation to [Fig. 5]. The pads 42 are preferably located around the plurality of transistors 26 of [Fig. 3]. Similarly, the device 50 comprises, for example, several pads 70 as described in relation to [Fig. 5]. The pads 70 are preferably located around the plurality of transistors 26 of [Fig. 3].

[0095] [Fig. 6] shows in more detail a part of another embodiment of an electronic device 74. More specifically, [Fig. 6] shows a sectional view of a trench 44 as described in [Fig. 3], for example along a plane AA of [Fig. 3], located in a chip of the device 74.

[0096] The device 74 comprises elements identical to elements of the device 50. These elements will not be described again in detail. Thus, the device 74 comprises the substrate 52, the layer 54, the cavity 56, the insulating layer 58, the conductive element 62 and the interconnection network comprising the stack 60 of insulating layers, the conductive tracks 64, 68 and the conductive vias 66.

[0097] The device 74 further comprises a conductive layer 76, for example made of metal, covering the lower face of the substrate 52. The layer 76 is for example in contact with the lower face of the substrate 52. The layer 76 extends at least opposite each trench 44.

[0098] The device 74 further comprises a layer 77. The layer 77 is an insulating layer. The layer 77 separates the layer 76 and the substrate 52. The layer 77 is for example in contact, by its upper face, with the substrate 52 and, by its lower face, with the layer 76. Thus, the layer 76 and the substrate 52 are not in contact.

[0099] The device 74 comprises, for each trench 44, a conductive element 78, by example made of metal, in the substrate 52. The element 78 passes through the substrate 52 and the layer 77. The element 78 extends from the upper face of the substrate 52 to the lower face of the layer 77. The lower face of the element 78 is in contact with the layer 76. Element 78 is located opposite, and in contact with, the corresponding trench 44. More specifically, the upper face of the element 78 is at least partially in contact with the element 62. The upper face of the element 78 is for example in contact with the layer 58, for example with the portions of the layer 58 extending over the bottom of the cavity 56. The dimensions of the element 78 are such that the element 62 is not in contact with the substrate 52 and that the element 78 is not in contact with the layer 54. In other words, the dimensions of the element 78 at the plane of the upper face of the substrate 52 are less than or equal to the dimensions of the bottom of the cavity 56. In addition, the dimensions of the layer 58, and more specifically the dimensions of the portions of the layer 58 covering the bottom of the cavity 56, are such that the central part of the bottom of the cavity 56 not covered by the layer 58 is entirely made up of the element 78.

[0100] The device further comprises a layer 79. The layer 79 laterally surrounds the element 78. The layer 79 therefore separates the element 78 from the substrate 52. The element 78 is therefore not in contact with the substrate 52.

[0101] In the embodiment of [Fig. 6], the layer 76 is biased to the control voltage of the transistors 26 of [Fig. 3]. Thus, the fingers 35 of [Fig. 3], corresponding for example to the track 68 of [Fig. 6], are biased via the conductive elements 78 and 62. The substrate 52 is for example biased to the source voltage and the layer 54 is for example biased to the drain voltage.

[0102] As a variant, the embodiment of [Fig.6] may not include the element 78. The cavity 56 is then formed so as to pass through the layer 54 and the substrate 52. The upper face of the layer 76 then constitutes the bottom of the cavity 56.

[0103] An example of a method for manufacturing the device 74 is identical to the method described in relation to [Fig.4], with the exception of the step of forming the substrate 52 which then comprises the formation of the element 78.

[0104] [Fig.7] shows in more detail another part of the embodiment of the device 74 of [Fig.6]. More precisely, [Fig.7] shows a pad 42 for applying the control voltage, a pad 80 for applying the source voltage and a pad 70 for applying the drain voltage.

[0105] The pads 42, 70 and 80 are located on the same chip, and in the same device 74 as the structure of [Fig.6]. Thus, the structure of [Fig.7] comprises elements of [Fig.6]. The structure of [Fig.7] thus comprises the substrate 52, the layer 54, the layer 58, the layer 77 and the layer 76. The structure of [Fig.7] further comprises the interconnection network, not shown. In other words, the structure of [Fig.7] comprises the stack 60 of insulating layers, not shown in [Fig.7], the stack comprising conductive tracks and conductive vias.

[0106] The pad 70 is identical to the pad 70 of [Fig. 5]. Thus, the pad 70 passes through the layer 58 and is in contact with the layer 54. The pad 70 is connected, preferably connected, to a voltage source providing the drain voltage of the transistors 26 of the lines 34 of [Fig. 3]. The pad 70 is for example connected, preferably connected, to said voltage source by the interconnection network not shown, more precisely by conductive tracks and conductive vias of the interconnection network not shown.

[0107] The pad 80 is identical to the pad 42 of [Fig. 5]. Thus, the pad 80 is located in a cavity passing through the layer 54 so as to reach the substrate 52. The pad 80 is separated from the layer 54 by the insulating layer 58. The pad 80 is in contact with the substrate 52. The pad 80 differs from the pad 42 of [Fig. 5] in that the pad 80 receives the source voltage. In other words, the pad 80 is connected, preferably connected, to a voltage source providing the source voltage of the transistors 26 of the lines 34 of [Fig. 3]. The pad 80 is for example connected, preferably connected, to said voltage source by the interconnection network not shown, more precisely by conductive tracks and conductive vias of the interconnection network not shown.

[0108] The pad 42 of [Fig.7] comprises, like the pad 80 and the pad 42 of [Fig.5], a conductive part 42a, for example made of metal, filling a cavity passing through the layer 54 and the layer 77 so as to reach the level of the lower face of the layer 54. The pad 42 comprises a conductive part 42b, for example made of metal, located in the substrate 52. The part 42b is for example identical to the element 78 of [Fig.6]. The portion 42b extends from the upper face of the substrate 52 to the lower face of the substrate 52. The upper face of the portion 42b is in contact with the portion 42a and the lower face of the portion 42b is in contact with the layer 76. The upper face of the portion 42b is for example in contact with the layer 58. The dimensions of the portion 42b are for example such that the portion 42b is not in contact with the layer 54, only with the portion 42a and possibly with the layer 58.The dimensions of the part 42b are for example such that the part 42a is not in contact with the substrate 52.

[0109] The pad 42 is connected, preferably connected, to a voltage source providing the control voltage for the transistors 26 of the lines 34 of [Fig. 3]. The pad 42 is for example connected, preferably connected, to said voltage source by the interconnection network not shown, more precisely by conductive tracks and conductive vias of the interconnection network not shown.

[0110] The device further comprises a layer 82. The layer 82 laterally surrounds the element 42b. The layer 82 therefore separates the element 42b from the substrate 52. The element 42b is therefore not in contact with the substrate 52.

[0111] The embodiments described in relation to figures 3 to 7 are for example intended to be present in power conversion circuits, for example in vehicles, for example cars.

[0112] An advantage of the described embodiments is that the delay between the application of the control voltage, or a variation of the control voltage, and the reception of the control voltage, or the control variation, is less significant.

[0113] Another advantage of the described embodiments is that a current spike in the control voltage is less likely to damage the transistors, since the spike is shared more quickly over a larger number of transistors.

[0114] Another advantage of the described embodiments is that they do not involve any modification of the transistors.

[0115] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0116] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Electronic device (50, 74) comprising trenches (44), the trenches (44) each comprising a conductive element (62, 78) configured to electrically connect the fingers (35) of transistor gates (26), located on the side of a first face of a first layer (54), to a second layer (52, 76) extending on the side of a second face of the first layer (54).

2. The device of claim 1, wherein the second layer (52, 76) is configured to be biased to the control voltage of the transistors (26).

3. Device according to claim 1 or 2, in which the transistors (26) are arranged in rows (34), the transistors (26) of the same row (34) being connected together by their gate by the same finger (35), the rows (34) being arranged in columns (41), the columns (41) being separated two by two by a trench (44), the conductive element (62, 78) of each trench (44) separating two columns (41) being connected to one end of each of the fingers (35) of the two columns.

4. Device according to claim 3, in which each column (41) is located between two trenches (44), each finger (35) being connected, by one end, to the conductive element (62, 78) of one of the two trenches (44), and, by another end, to the conductive element (62, 78) of the other of the two trenches (44).

5. A device according to any one of claims 1 to 4, wherein the first layer (54) is GaN, AIN or AlGaN.

6. A device according to any one of claims 1 to 5, wherein the device (50, 74) comprises a semiconductor substrate (52) on the second face side of the first layer (54), the substrate (52) constituting the second layer.

7. A device according to claim 6, wherein each trench (44) comprises a cavity (56) passing through the first layer (54), the bottom of the cavity (56) being formed by the substrate (52), and the conductive element (62) comprising a third conductive layer (62) extending over the walls and the bottom of the cavity (56).

8. Device according to any one of claims 1 to 7, in which the device (50, 74) comprises a semiconductor substrate (52) on the side of the second face of the first layer (54), the face of the substrate (52) furthest from the first layer (54) being covered with a fourth conductive layer (76), the fourth layer (76) constituting the second layer.

9. A device according to claim 8, wherein the fourth layer (76) is made of metal.

10. A device according to claim 8 or 9, wherein each trench (44) comprises a cavity (56) passing through the first layer (54), the bottom of the cavity (56) being located at the face of the substrate (52) closest to the first layer (54), the conductive element (62, 78) comprising a third conductive layer (62) extending over the walls and the bottom of the cavity and a portion (78) located in the substrate (52), in contact with the third layer (62) and in contact with the fourth layer (76).

11. A device according to claim 7 or 10, wherein the third layer (62) is separated from the first layer (54) by a fifth insulating layer (58).

12. A device according to any one of claims 6 to 11, wherein the substrate (52) is made of silicon or carbonaceous silicon.

13. A device according to any one of claims 1 to 12, wherein each conductive element (62, 78) is connected to the fingers (35) by tracks and vias of an interconnection network.

14. A method of manufacturing an electronic device (50, 74) comprising forming trenches (44), the trenches (44) each comprising a conductive element (62, 78) configured to electrically connect the fingers (35) of transistor gates (26), located on the side of a first face of a first layer (54), to a second layer (52, 76) extending on the side of a second face of the first layer (54).

15. A method according to claim 14 applied to the manufacture of a device according to any one of claims 1 to 13.

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