Electronic device

Abstract

Electronic Device This description concerns a device comprising a pixel (10), the pixel comprising a first region (16, 24) doped with a first type of conductivity and a second region (26) doped with a second type of conductivity, the first region comprising first (16) and second (24) layers forming a heterojunction, the first layer (16) being made of a semiconductor material and the second layer (24) comprising quantum dots, the second region (26) being in contact with the second layer (24), the first layer (16) being laterally surrounded by an insulated conductive wall (18), the dopant concentration of the first layer (16) being greater than that of the second layer (24). Figure for the abstract: Fig. 1

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and more specifically to optoelectronic devices comprising photodiodes. Prior art

[0002] A photodiode is a semiconductor component having the capacity to capture radiation from the optical domain and transform it into an electrical signal.

[0003] In a common type of photodiode, the space charge region is located in a semiconductor material, usually silicon. However, silicon is poorly reactive at near infrared (NIR) and short-wave infrared (SWIR) wavelengths. Summary of the invention

[0004] One embodiment provides a device comprising a pixel, the pixel comprising a first region doped with a first conductivity type and a second region doped with a second conductivity type, the first region comprising first and second layers forming a heterojunction, the first layer being made of a semiconductor material and the second layer comprising quantum dots, the second region being in contact with the second layer, the first layer being laterally surrounded by an insulated conductive wall, the dopant concentration of the first layer being greater than that of the second layer.

[0005] Another embodiment provides a method of controlling a device comprising a pixel, the pixel comprising a first region doped with a first conductivity type and a second region doped with a second conductivity type, the first region comprising first and second layers forming a heterojunction, the first layer being made of a semiconductor material and the second layer comprising quantum dots, the second region being in contact with the second layer, the first layer being laterally surrounded by an insulated conductive wall, the dopant concentration of the first layer being greater than that of the second layer, the method comprising biasing the wall to a negative voltage.

[0006] According to one embodiment, the first type of conductivity is the N type and the second type of conductivity is the P type.

[0007] According to one embodiment, the first layer is flush with a first face of a semiconductor substrate, an interconnection network covering a second face of the substrate.

[0008] According to one embodiment, the interface between the first layer and the second layer is treated so as to allow the passage of charges.

[0009] According to one embodiment, the second region covers the second layer, the second layer separating the first layer and the second region.

[0010] According to one embodiment, the pixel comprises at least two first layers, the interface between each first layer and the second layer being surrounded by a third conductive layer.

[0011] According to one embodiment, each third conductive layer is separated from the corresponding first layer by a fourth insulating layer comprising an opening at each interface.

[0012] According to one embodiment, the pixel comprises four first layers, each first layer being surrounded by the wall.

[0013] According to one embodiment, the method comprises a repetition of a cycle of steps, the cycle comprising as many steps as there are first layers in the pixel, in each step, one of the third layers being biased by a first voltage, the other third layers being biased to a zero voltage, the third biased layer being different at each step of a cycle.

[0014] According to one embodiment, the first voltage is a negative voltage.

[0015] According to one embodiment, the second region laterally surrounds the first layer.

[0016] According to one embodiment, the second region is between the first layer and the wall.

[0017] According to one embodiment, the device comprises two pixels having a second region and a second layer in common, the second region being located between the walls surrounding the first layers of the two pixels.

[0018] Time of flight measuring device comprising the device as described above. Brief description of the drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [Fig.l] represents an embodiment of a pixel;

[0021] [Fig.2] illustrates the operation of the pixel of [Fig.l];

[0022] [Fig.3] represents another embodiment of a pixel;

[0023] [Fig.4] illustrates the operation of the pixel of [Fig.3];

[0024] [Fig.5] represents another embodiment of a pixel;

[0025] [Fig.6] represents a sectional view of another embodiment of a pixel;

[0026] [Fig.7] represents a sectional view along a plane AA of the pixel of [Fig.6];

[0027] [Fig.8] represents a sectional view along a plane BB of the pixel of [Fig.6]; and

[0028] [Fig.9] illustrates the operation of the pixel of figures 6, 7 and 8. Description of the embodiments

[0029] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0031] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0034] [Fig.l] represents an embodiment of a pixel 10, of an optoelectronic device. The device is for example a sensor, for example a time-of-flight sensor. The device comprises at least one pixel, for example at least one hundred pixels, for example at least a thousand pixels.

[0035] The pixel 10 is located in and on a substrate 12. The substrate 12 is made of a semiconductor material, for example silicon. The substrate 12 comprises a first face 12a, or lower face, and a second face 12b, or upper face, opposite the first face 12a. Electronic components are located in and on the substrate 12 on the side of the first face 12a. Thus, transistors 14 are shown in [Fig.l]. The transistors 14 are each represented by a source region and a drain region flush with the face 12a and a gate located on the face 12a. An interconnection network not shown, i.e. a stack of insulating layers comprising conductive tracks and conductive vias so as to allow electrical connections, is for example located on the face 12a of the substrate.

[0036] The pixel 10 comprises a photodiode. The photodiode comprises a region 16 of the substrate. More precisely, the region 16 corresponds to a doped well of the substrate 12. The well 16 is located on the side of the face 12b. Preferably, the well 16 is flush with the face 12b of the substrate 12. The well 16 is made of a semiconductor material, for example the same material as the substrate 12, for example silicon. The well 16 is N-type doped and forms a portion of the cathode of the photodiode. The well 16 is for example made of a single material, for example homogeneous. The concentration of dopants in the well 16 is for example substantially equal to 1016 dopants per cm 3.

[0037] The pixel comprises a wall 18. The wall 18 is conductive and insulated. In other words, the wall 18 comprises a conductive core, for example made of metal, and an insulating outer sheath surrounding at least laterally the conductive core. The wall 18 laterally surrounds the box 16. The side walls of the box 16 are for example in contact with the side walls of the sheath of the wall 18.

[0038] The wall 18 extends at least over the height of the box 16. In other words, the wall 18 extends at least along the side walls of the box 16. Preferably, the wall 18 extends over the entire height of the substrate 12.

[0039] The electronic components located in the region of the substrate 12 surrounded by the wall 18 are for example components associated with the pixel, for example the components forming the control circuit of the pixel or components of the circuit for processing the information obtained by the pixel.

[0040] The conductive core of the wall 18 is configured to receive a voltage. The core of the wall 18 is for example connected to a node for applying said voltage by conductive tracks and conductive vias of the interconnection network not shown.

[0041] The pixel comprises for example an insulating layer 20. The layer 20 covers for example the face 12b. The layer 20 then comprises an opening 22 facing the box 16. The opening 22 is for example located only facing the box 16. The opening 22 preferably has horizontal dimensions smaller than the dimensions of the upper face of the box 16. Thus, a portion, preferably a central portion, of the upper face of the box 16 is not covered by the layer 20. Preferably, a peripheral portion of the upper face is covered by the layer 20. Preferably, the wall 18 is covered by the layer 20. The opening 22 corresponds for example to the illumination window of the pixel.

[0042] The pixel 10 further comprises a layer 24. The layer 24 covers the upper face of the substrate 12. More precisely, the layer 24 covers at least the portion of the box 16 uncovered by the opening 22. The layer 24 preferably covers the insulating layer 20. The layer 24 is preferably in contact with the box 16, more precisely with the portion of the upper face of the box uncovered by the opening 22.

[0043] Layer 24 constitutes another part of the cathode of the photodiode of the pixel. Layer 24 comprises quantum dots of the same conductivity type as well 16, for example of type N. Layer 24 constitutes the photosensitive layer of the photodiode.

[0044] A quantum dot or semiconductor nanoparticle is a nanoscopic material structure that produces electron-hole pairs in the presence of the incidence of photons on the nanoscopic material structure.

[0045] A quantum dot comprises a semiconductor core. A quantum dot may also comprise a shell, preferably of a semiconductor material, surrounding the core to protect and passivate the core. A quantum dot further comprises ligands, organic aliphatic compounds, organometallic or inorganic molecules that extend from the shell and passivate, protect, and functionalize the semiconductor surface.

[0046] The composition of a quantum dot can be chosen from the following materials. The core is, for example, made of a material from among the following materials or from an alloy of the following materials: CdSe, CdS, CdTe, CdSeS, CdTeSe, AgS, ZnO, ZnS, ZnSe, CuInS, CuInSe, CuInGaS, CuInGaSe, PbS, PbSe, PbSeS, PbTe, InAsSb, InAs, InSb, InGaAs, InP, InGaP, InAlP, InGaAlP, InZnS, InZnSe, InZnSeS, HgTe, HgSe, HgSeTe, Ge, Si. The shell is, for example, made of a material from among the following materials or from an alloy of the following materials: CdSe, CdS, CdTe, CdSeS, CdTeSe, AgS, ZnO, ZnS, ZnSe, CuInS, CuInSe, CuInGaS, CuInGaSe, PbS, PbSe, PbSeS, PbTe, InAsSb, InAs, InSb, InGaAs, InP, InGaP, InAlP, InGaAlP, InZnS, InZnSe, InZnSeS, HgTe, HgSe, HgSeTe, Ge, Si.

[0047] Preferably, all dimensions of the core are less than 20 nm, for example in the range from 2 to 15 nm. In particular, the diameter of each quantum dot is preferably in the range from 2 to 15 nm. By diameter is meant the diameter of the smallest sphere in which the quantum dot can be inscribed.

[0048] It is possible to choose a size and dimension of quantum dots capable of absorbing, with significant absorption, any wavelength in a wide range of wavelengths. For example, it is possible to find a size and dimension of the quantum dots having an operating wavelength greater than 300 nm, for example between 300 nm and 3000 nm, which includes the visible, the infrared, the near infrared and the short infrared. For example, the layer 24 comprises quantum dots made of lead sulfide, for example quantum dots having a radius of less than 10 nm, to obtain an absorption peak linked to quantum confinement in the infrared, while allowing the absorption of wavelengths in the visible.

[0049] The layer 24 has for example a thickness between 100 nm and 500 nm. The box 16 has for example a thickness between 2 pm and 10 pm.

[0050] The doping of layer 24, for example between 1015 dopants per cm3 and 1016 dopants per cm3, is lower than the doping of well 16, i.e. the concentration of dopants in well 16, so as to allow layer 24 to be entirely depleted by layer 16 and the voltage applied to layer 28.

[0051] The interface between the well 16 and the layer 24 forms a heterojunction. Preferably, the upper face of the well 16 is treated, for example before the formation of the layer 24, so as to ensure the formation of the heterojunction. The upper face of the well 16 is for example treated with a self-assembled monolayer (SAM), for example made of Ch3I or one or more other halogenated compounds. The monolayer is for example replaced by a thin layer of metal oxide, for example made of ZnO. The upper face of the well 16 is for example treated with a halogen treatment.

[0052] The pixel 10 further comprises a layer 26. The layer 26 is a hole extraction layer. The layer 26 is of the conductivity type opposite to the conductivity type of the well 16 and the layer 24, for example of the P type. The layer 26 is for example made of a P type doped metal oxide or comprises for example quantum dots behaving like a P type material due to the position of its Fermi level relative to the Fermi level of the material of the layer 24. The layer 26 corresponds to the anode of the photodiode. The layer 26 is transparent to the operating wavelengths of the pixel.

[0053] Layer 26 covers the upper face of layer 24. Preferably, layer 26 covers at least the portion of layer 24 located opposite well 16. Layer 26 is preferably in contact with layer 24, for example at least with the portion of layer 24 located opposite well 16. The interface between layer 24 and layer 26 opposite well 16 corresponds to a PN junction of the photodiode making it possible to extract the generated photocarriers not stored in well 16, the generated photocarriers being holes in the case of an N-doped well 16.

[0054] The pixel 10 further comprises a layer 28. The layer 28 is a conductive layer, for example made of metal oxide. The layer 28 is transparent to the operating wavelengths of the pixel. The layer 28 is for example made of sub-stoichiometric MoO3, ITO, Va2O5, NiO, CuO, WO3. The layer 28 is part of the anode of the photodiode in the case where it is used to collect holes.

[0055] The layer 28 covers the upper face of the layer 26. Preferably, the layer 28 covers at least the portion of the layer 26 located opposite the box 16. The layer 28 is preferably in contact with the layer 26, for example at least with the portion of the layer 26 located opposite the box 16.

[0056] [Fig.2] illustrates the operation of pixel 10 of [Fig.l]. More precisely, the [Fig.2] illustrates the operation of two pixels 10 of the device.

[0057] In the example of [Fig.2], the adjacent pixels 10 have a common portion of wall 18. Thus, the wells 16 of two neighboring pixels 10 are separated only by a wall 18. The cores of the walls 18 are then biased at the same voltage. Alternatively, the walls 18 of two neighboring pixels may be separated from each other by a substrate region or an insulating region.

[0058] During operation of the device, and during operation of the pixels 10, negative voltages are applied to the cores of the walls 18 and to the layer 28. The cores of the walls 18 are preferably biased at the same voltage. The cores of the walls 18 and the layer 28 are for example biased at different negative voltages. For example, the cores of the walls 18 are biased at a voltage between -1 V and -3 V. For example, the layer 28 is biased at a voltage between -2 V and -5 V.

[0059] When a light ray (represented by an arrow 30) reaches a pixel, the part of the radiation having wavelengths included in the operating wavelengths of the pixel passes through the layers 26 and 28. When said part of the radiation reaches the layer 24, the photons are absorbed in the photosensitive layer 24. Pairs of electrons (-) and holes (+) are thus generated in the layer 24.

[0060] The negative voltage applied to the cores of the walls 18 makes it possible to deplete the boxes 16, which makes it possible to attract the electrons. The electrons are thus displaced and stored in the box 16.

[0061] The negative voltage applied to layer 28 allows holes to be attracted into the hole extraction layer 28. The holes are thus extracted by layer 26.

[0062] The polarization of the walls 18 also makes it possible to limit the movement of electrons from one box 16 to another and from a portion of the layer 24 corresponding to a pixel to another portion of the layer 24 corresponding to another pixel.

[0063] [Fig. 3] represents another embodiment of a pixel 32, of an optoelectronic device. The device is for example a sensor, for example a time-of-flight sensor. The device comprises at least one pixel, for example at least one hundred pixels, for example at least a thousand pixels.

[0064] As in pixel 10 of [Fig.l], pixel 32 is formed in substrate 12. Pixel 32 comprises well 16, wall 18, layer 24 and the interconnection network not shown. Well 16 and layer 24 form a heterojunction, as in pixel 10 of [Fig.l].

[0065] Pixel 32 differs from pixel 10 in that pixel 32 does not include layers 26 and 28. Pixel 32 includes a layer 34. Layer 34 is an insulating layer, for example a passivation layer. Layer 34 is transparent to wavelengths pixel operating wavelength. Layer 34 is for example made of Si3N4 or SiO2. Layer 34 has no electrical function.

[0066] The layer 34 covers the upper face of the layer 24. Preferably, the layer 34 covers at least the portion of the layer 24 located opposite the box 16. The layer 34 is preferably in contact with the layer 24, for example at least with the portion of the layer 24 located opposite the box 16.

[0067] The pixel 32 further comprises a box 36. The box 36 is located in the substrate 12. The box 36 preferably laterally surrounds the box 16. The upper face of the box 36 is flush with the upper face of the substrate 12 and is thus coplanar with the upper face of the box 16. Thus, the upper face of the box 16 is surrounded by the upper face of the box 36. The layer 24 is thus in contact with the boxes 16 and 36.

[0068] The box 36 extends for example at least over the height of the box 16. Thus, the box 36 preferably extends along the entire length of the box 16. For example, the box 36 extends over the entire height of the substrate 12. The box 36 extends for example from the face 12a to the face 12b of the substrate 12.

[0069] The box 36 is located between the box 16 and the wall 18. Preferably, the box 36 is in lateral contact with the wall 18, more precisely with the side walls of the insulating sheath of the wall 18, and with the side walls of the box 16. The box 16 is thus separated from the wall 18 by, for example only by, the box 36. In a device comprising more than one pixel 32, each box 16 is for example separated from the neighboring box 16 by two boxes 36 and at least one wall 18, for example only two boxes 36 and one wall 18.

[0070] The well 36 is for example made of the material of the substrate 12, for example silicon. The well 36 is doped with the conductivity type opposite to the conductivity type of the well 16, for example P type. The well 36 constitutes the hole extraction region. The dopant concentration of the well 36 is for example between 1017 and 1018 dopants per cm3.

[0071] The pixel 32 comprises for example a region 38, in contact with the well 16 and flush with the face 12a of the substrate. The region 38 is for example made of the same material as the substrate 12, for example silicon, for example doped with the same type of conductivity as the well 16. The concentration of dopants in the well 16 is lower than the concentration of dopants in the region 38. The region 38 is for example separated from the rest of the substrate 12 by walls 40, for example insulated conductive walls. The region 38 makes it possible for example to collect electrons. The region 38 is preferably connected to the interconnection network not shown.

[0072] [Fig.4] illustrates the operation of the pixel of [Fig.3]. More precisely, the [Fig.4] illustrates the operation of two pixels 32 of the device.

[0073] In the example of [Fig.4], the adjacent pixels 32 have a common portion of wall 18. Thus, the wells 16 of two neighboring pixels 32 are separated only by one wall 18 and two wells 36. The cores of the walls 18 are then biased at the same voltage. Alternatively, the walls 18 of two neighboring pixels may be separated from each other by a substrate region or an insulating region.

[0074] During operation of the device, and during operation of the pixels 32, negative voltages are applied to the cores of the walls 18. The cores of the walls 18 are preferably biased to the same negative voltage. For example, the cores of the walls 18 are biased to a voltage between -1 V and -3 V.

[0075] When a light ray (represented by an arrow 42) reaches a pixel, the part of the radiation having wavelengths included in the operating wavelengths of the pixel passes through the layer 34. When said part of the radiation reaches the layer 24, the photons are absorbed in the photosensitive layer 24. Pairs of electrons and holes are thus generated in the layer 24.

[0076] The negative voltage applied to the cores of the walls 18 makes it possible to deplete the boxes 16, which makes it possible to attract the electrons. The electrons are thus displaced and stored in the box 16. The holes are extracted by the box 36.

[0077] The polarization of the walls 18 also makes it possible to limit the movement of electrons from one box 16 to another and from a portion of the layer 24 corresponding to a pixel to another portion of the layer 24 corresponding to another pixel.

[0078] [Fig. 5] represents another embodiment of pixels 44, of an optoelectronic device. The device is for example a sensor, for example a time-of-flight sensor. The device comprises at least two pixels, for example at least one hundred pixels, for example at least one thousand pixels.

[0079] As in pixel 32 of [Fig. 3], pixel 44 is formed in substrate 12. Pixel 44 comprises well 16, wall 18, layer 24, layer 34, well 36 and the interconnection network not shown. Well 16 and layer 24 form a heterojunction, as in pixel 32 of [Fig. 3].

[0080] Pixels 44 differ from pixel 32 of [Fig.3] in that box 36 is not located inside wall 18 by one pixel.

[0081] In the embodiment of [Fig. 5], the adjacent pixels do not comprise a common wall 18. In other words, the walls 18 of different pixels are separated from each other. More precisely, the walls 18 of two neighboring pixels 44 are separated from each other by the box 36. Thus, the boxes 16 of two neighboring pixels are separated by two portions of walls 18 and a box 36. Each wall 18 is for example surrounded by the box 36. The box 36 is thus common to several pixels 44, for example to all the pixels 44.

[0082] The box 36 is preferably in lateral contact with the side walls of the walls 18, that is to say with the side walls of the insulating sheaths of the walls 18. The box 36 preferably extends over the entire height of the substrate 36, so as to be able to be connected to the interconnection network not shown. In addition, an upper face of the box 36 is flush with the face 12b of the substrate and is therefore coplanar with the upper face of the box 16. The layer 24 is thus in contact with the upper faces of the boxes 16 and 36.

[0083] The operation of the pixels 44 of [Fig.5] differs from the operation of the pixels 32 of [Fig.4] in that the holes are extracted by the box 36 located outside the walls 18.

[0084] Figures 6 to 8 represent an embodiment of pixels 46, of an optoelectronic device. The device is for example a sensor, for example a time-of-flight sensor. The device comprises at least one pixel, for example at least one hundred pixels, for example at least a thousand pixels.

[0085] More specifically, [Fig.6] represents a sectional view of the pixel 46 along a plane CC of figures 7 and 8. [Fig.7] represents a sectional view along a plane AA of the pixel of [Fig.6]. [Fig.8] represents a sectional view along a plane BB of the pixel of [Fig.6].

[0086] Pixel 46 comprises elements common to pixel 10 of Figures 1 and 2. These elements will not be described again in detail. Thus, pixel 46, located in substrate 12, comprises layer 20, layer 24, layer 26, layer 28 and the interconnection network not shown.

[0087] Furthermore, the pixel 46 comprises at least two boxes 16. In the example of FIGS. 6, 7, 8, the pixel 46 comprises four boxes 16a, 16b, 16c and 16d. The four boxes are arranged in a matrix, i.e. in two rows and two columns. Each box 16a, 16b, 16c and 16d comprises, for example, as in [Fig. 3], a region 38 surrounded by a wall 40.

[0088] As in Figures 1 and 2, the boxes 16a, 16b, 16c and 16d are surrounded by a wall 18, comprising, as in [Fig.l] and 2, a conductive core and an insulating sheath. Preferably, the boxes 16a, 16b, 16c and 16d are surrounded by the same wall 18. The wall 18 thus extends between the boxes 16a, 16b, 16c and 16d and around the boxes 16a, 16b, 16c and 16d.

[0089] The layer 28 is for example covered with a layer 47. The layer 47 is preferably in contact with the layer 28. The layer 47 comprises an opening 48. The opening 48 preferably extends at least partially opposite each well 16a, 16b, 16c and 16d. Preferably, the layer 47 extends opposite a portion of the wells 16a, 16b, 16c and 16d. The layer 47 is made of a material opaque to the operating wavelengths of the pixel 46. The opening 48 thus defines the illumination window 50 of the pixel 46, that is to say the portion of the layers 24, 26, 28 reached by the light rays. The portion of the layer 24 located in the window 50, that is to say located opposite opening 48, corresponds to the location of generation of electron-hole pairs.

[0090] The layer 20 partially covers, as in the embodiments of FIGS. 1 and 2, the boxes 16a, 16b, 16c and 16d. Preferably, the layer 20 covers the portions of the boxes 16a, 16b, 16c and 16d located opposite the opening 48. The layer 20 further covers the wall 18. The layer 20 comprises an opening 52a, 52b, 52c, 52d opposite each box 16a, 16b, 16c and 16d. More precisely, the opening 52a, respectively 52b, respectively 52c, respectively 52d, is located opposite the box 16a, respectively 16b, respectively 16c, respectively 16d. Thus, the portions of the boxes 16a, 16b, 16c and 16d uncovered by the openings 52a, 52b, 52c, 52d connected, for example in contact, with the layer 24. The openings 52a, 52b, 52c, 52d constitute the paths of the electrons heading towards the boxes.

[0091] The pixel 46 comprises, for each well 16a, 16b, 16c and 16d, a conductive layer 54a, 54b, 54c, 54d. The layer 54a, respectively 54b, respectively 54c, respectively 54d surrounds the opening 52a, respectively 52b, respectively 52c, respectively 52d. Each layer 54a, 54b, 54c, 54d rests on the layer 20. Thus, the portions of the layers 54a, 54b, 54c, 54d located opposite the boxes 16a, 16b, 16c and 16d are separated from the boxes 16a, 16b, 16c and 16d by the layer 20. The layers 54a, 54b, 54c, 54d are for example in contact with the layer 24. The different layers 54a, 54b, 54c, 54d are not in contact with each other.

[0092] The layers 54a, 54b, 54c, 54d are configured to be biased at control voltages, preferably different voltages. Thus, each layer 54a, 54b, 54c, 54d is for example connected to the interconnection network not shown by an insulated conductive via 56. The pixel 46 thus comprises as many vias 56 as there are layers 54a, 54b, 54c, 54d, i.e. four vias 56 in the embodiment of FIGS. 6 to 8. Each via 56 comprises a conductive core 56a and an insulating sheath 56b. The conductive core 56a of each via 56 is connected, by one end to one of the layers 54a, 54b, 54c, 54d and by another end to vias or conductive tracks of the interconnection network so as to be connected to a source for applying a control voltage. Each via 56 thus preferably passes entirely through the substrate 12, that is to say extends from the face 12a to the face 12b. Each via 56 is for example separated from the wall 18 by a portion 58 of substrate 12.Each via 56 is for example separated from the boxes by a portion 58 and by the wall 18.

[0093] [Fig. 9] illustrates the operation of the pixels 46 of Figures 6, 7 and 8. [Fig. 9] comprises two views 9A and 9B each representing a step of operation of the pixel 46.

[0094] The operation of pixel 46 comprises, for example, as many steps as there are boxes 16. Thus, the operation of pixel 46 as described in relation to FIGS. 6 to 8 comprises four steps. In [Fig.9], only two of the four steps are shown. More specifically, view 9A represents a storage step in box 16a and view 9B represents a storage step in box 16b.

[0095] The pixel 46 is for example configured to perform a demodulation of the signal generated by the received light. For example, the pixel 46 is present in a time-of-flight measuring device.

[0096] During the step of view 9A of the operation of pixel 46, negative voltages are applied to the core of wall 18 and to layer 28. For example, the core of wall 18 is biased to a voltage between -1 V and -3 V. For example, layer 28 is biased to a voltage between -2 V and -5 V.

[0097] When a light ray (represented by an arrow 60) reaches a pixel 46, more precisely reaches the window 50, the part of the radiation having wavelengths included in the operating wavelengths of the pixel passes through the layers 26 and 28. When said part of the radiation reaches the layer 24, the photons are absorbed in the photosensitive layer 24. Pairs of electrons (-) and holes (+) are thus generated in the layer 24.

[0098] Layer 54a is biased to a negative voltage and layers 54b, 54c and 54d are biased to zero voltages. Said negative voltage is for example between -1 V and -4 V.

[0099] The negative voltage applied to the cores of the walls 18 makes it possible to deplete the boxes 16. The voltages of the layers 54a, 54b, 54c and 54d make it possible to ensure that a major part, for example more than 75%, of the electrons generated are thus displaced and stored in the box 16a.

[0100] The negative voltage applied to layer 26 allows holes to be attracted into the hole extraction layer 26. The holes are thus extracted by layer 26.

[0101] The step of view 9B is similar to the step of view 9A. The step of view 9B differs from the step of view 9A in that the electrons are predominantly, for example at least 75%, stored in the well 16b. To do this, the layer 54b is biased to a negative voltage and the layers 54a, 54c and 54d are biased to zero voltages. Said negative voltage is for example between -1 V and -4 V.

[0102] In other words, the pixel 46 comprises as many steps as there are wells 16 and comprises, for each step, the polarization of the layer 54 corresponding to one of the wells at a negative voltage and the polarization of the other layers 54 at a zero voltage, the core of the wall 18 and the layer 26 being polarized at negative voltages.

[0103] During the operation of pixels 46, for example in a time-of-flight measuring device, the different steps are carried out alternately, for preferably equal durations. Thus, the operation of the pixels comprises the repetition of a cycle comprising the four stages preferably carried out over the same duration.

[0104] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. For example, the embodiment of Figures 1 and 2 may include region 38 and walls 40.

[0105] Furthermore, the charges (electrons and holes) can be exchanged. Thus, according to another embodiment, the conductivity types can be exchanged, the layer 26 then being an electron extraction layer.

[0106] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A device comprising a pixel (10, 44, 46), the pixel comprising a first region (16, 16a, 16b, 16c, 16d, 24) doped with a first conductivity type and a second region (26, 36) doped with a second conductivity type, the first region comprising first (16, 16a, 16b, 16c, 16d) and second (24) layers forming a heterojunction, the first layer (16, 16a, 16b, 16c, 16d) being made of a semiconductor material and the second layer (24) comprising quantum dots, the second region (26, 36) being in contact with the second layer (24), the first layer (16, 16a, 16b, 16c, 16d) being laterally surrounded by an insulated conductive wall (18), the concentration of dopants of the first layer (16, 16a, 16b, 16c, 16d) being higher than that of the second layer (24).

2. The device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

3. r. Device according to claim 1 or 2, in which the first layer (16, 16a, 16b, 16c, 16d) is flush with a first face (12b) of a semiconductor substrate (12), an interconnection network covering a second face (12a) of the substrate.

4. Device according to any one of claims 1 to 3, in which the interface between the first layer (16, 16a, 16b, 16c, 16d) and the second layer (24) is treated so as to allow the passage of charges.

5. A device according to any one of claims 1 to 4, wherein the second region (26) overlies the second layer (24), the second layer (24) separating the first layer (16, 16a, 16b, 16c, 16d) and the second region (26).

6. A device according to claim 5, wherein the pixel comprises at least two first layers (16a, 16b, 16c, 16d), the interface between each first layer (16a, 16b, 16c, 16d) and the second layer (24) being surrounded by a third conductive layer (54a, 54b, 54c, 54d).

7. Device according to claim 6, in which each third conductive layer (54a, 54b, 54c, 54d) is separated from the corresponding first layer (16a, 16b, 16c, 16d) by a fourth insulating layer (20) comprising an opening at each interface.

8. A device according to claim 6 or 7, wherein the pixel comprises four first layers (16a, 16b, 16c, 16d), each first layer (16a, 16b, 16c, 16d) being surrounded by the wall (18).

9. A device according to any one of claims 1 to 4, wherein the second region (36) laterally surrounds the first layer (16).

10. The device of claim 10, wherein the second region (36) is between the first layer (16) and the wall (18).

11. A device according to any one of claims 1 to 4, wherein the device comprises two pixels (44) having a second region (36) and a second layer (24) in common, the second region (36) being located between the walls surrounding the first layers (16) of the two pixels (44).

12. A time-of-flight measuring device comprising the device according to any one of claims 1 to 12.

13. A method of controlling a device comprising a pixel (10, 44, 46), the pixel comprising a first region (16, 16a, 16b, 16c, 16d, 24) doped with a first conductivity type and a second region (26, 36) doped with a second conductivity type, the first region comprising first (16, 16a, 16b, 16c, 16d) and second (24) layers forming a heterojunction, the first layer (16, 16a, 16b, 16c, 16d) being made of a semiconductor material and the second layer (24) comprising quantum dots, the second region (26, 36) being in contact with the second layer (24), the first layer (16, 16a, 16b, 16c, 16d) being laterally surrounded by an insulated conductive wall (18), the dopant concentration of the first layer (16, 16a, 16b, 16c, 16d) being higher than that of the second layer (24), the method comprising biasing the wall to a negative voltage.

14. A method according to claim 13 applied to the formation of a device according to any one of claims 1 to 12.

15. A method according to claim 14, as attached to claim 8, wherein the method comprises repeating a cycle of steps, the cycle comprising as many steps as there are first layers (16a, 16b, 16c, 16d) in the pixel (46), in each step, one of the third layers (54a, 54b, 54c, 54d) being biased by a first voltage, the other third layers being biased to a zero voltage, the biased third layer being different at each step of a cycle.

16. A method according to claim 15, as it relates to the resale- indication 2, in which the first voltage is a negative voltage.

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