Manufacturing process of a bipolar transistor

Abstract

Method of manufacturing a bipolar transistor The present description relates to a method of manufacturing a bipolar transistor (10) comprising: a. forming, on a substrate (12), a first stack of layers comprising a first layer (18) of the material of the base of the bipolar transistor between second (16) and third (20) insulating layers; b. forming a first cavity (22) passing through the first stack so as to reach the substrate (12), the step of forming the first cavity (22) does not include etching any layer covering the first layer (18) other than the third layer (20); and c. forming a first portion (26) of the collector of the bipolar transistor and a second portion (28) of the base of the bipolar transistor in the first cavity. Figure for abstract: Fig. 3

Description

Title of the invention: Method for manufacturing a bipolar transistor Technical field

[0001] The present description relates generally to electronic devices and their manufacturing methods and more specifically to bipolar transistors and their manufacturing methods. Prior art

[0002] A bipolar transistor is a semiconductor-based electronic device from the transistor family. Its operating principle is based on two PN junctions, one forward and the other reverse.

[0003] Manufacturing processes for bipolar transistors can be problematic. For example, etching a thick stack of layers during emitter formation can result in the formation of non-planar layers. Such layers can cause problems when forming contacts. Summary of the invention

[0004] One embodiment provides a method for manufacturing a bipolar transistor comprising: a. forming, on a substrate, a first stack of layers comprising a first layer of the material of the base of the bipolar transistor between second and third insulating layers; b. forming a first cavity passing through the first stack so as to reach the substrate, the step of forming the first cavity does not include etching any layer covering the first layer other than the third layer; etc. forming a first portion of the collector of the bipolar transistor and a second portion of the base of the bipolar transistor in the first cavity.

[0005] According to one embodiment, the first and second portions are formed by epitaxial growth.

[0006] According to one embodiment, the first portion is closer to the bottom of the first cavity than the second portion.

[0007] According to one embodiment, the method comprises, after step c., a step d. of forming a fourth insulating layer covering an upper face of the third layer and an upper face of the second portion, the fourth layer comprising an opening uncovering a part of an upper face of the second portion.

[0008] According to one embodiment, the fourth layer is flat.

[0009] According to one embodiment, the method comprises, after step d., a step e. of forming a second stack of layers comprising a fifth layer made of the emitter material of the bipolar transistor and a sixth insulating layer covering the fifth layer.

[0010] According to one embodiment, the fifth layer is in contact with the fourth layer and fills the opening in the fourth layer.

[0011] According to one embodiment, the thickness of the fifth layer is substantially equal to ten times the thickness of the fourth layer.

[0012] According to one embodiment, the method comprises the partial etching of the fourth, fifth and sixth layers. Brief description of the drawings

[0013] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0014] [Fig.l] represents a device resulting from a step of a method of manufacturing a bipolar transistor;

[0015] [Fig.2] represents a device resulting from another step of the bipolar transistor manufacturing process;

[0016] [Fig.3] represents a device resulting from another step of the manufacturing process of the bipolar transistor;

[0017] [Fig.4] represents a device resulting from another step of the bipolar transistor manufacturing process;

[0018] [Fig.5] represents a device resulting from another step of the bipolar transistor manufacturing process;

[0019] [Fig.6] represents a device resulting from another step of the bipolar transistor manufacturing process;

[0020] [Fig.7] represents a device resulting from another step of the manufacturing process of the bipolar transistor;

[0021] [Fig.8] represents a device resulting from another step of the manufacturing process of the bipolar transistor;

[0022] [Fig.9] represents a device resulting from another step of the process of manufacturing the bipolar transistor; and

[0023] [Fig. 10] represents a device resulting from another step of the bipolar transistor manufacturing process. Description of the embodiments

[0024] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0026] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0028] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0029] Unless otherwise specified, the expressions "conductor" and "insulator" mean "electrically conductive" and "electrically insulating".

[0030] Figures 1 to 10 represent steps, preferably successive, of a method of manufacturing a bipolar transistor 10.

[0031] [Fig.l] represents a device resulting from a step of a method of manufacturing the bipolar transistor 10.

[0032] During this step, a substrate 12 is formed. The substrate 12 constitutes the substrate in and on which the transistor 10 will be formed. The substrate 12 is for example made of a semiconductor material, for example silicon, for example silicon doped with N-type dopants. A portion of the substrate corresponds for example to a portion of the collector of the bipolar transistor 10.

[0033] The step of [Fig.l] comprises for example the formation of an isolation trench 14. The trench 14 is for example a simple shallow trench insulation (SSTI). The trench 14 corresponds to an insulating region located in the substrate 12, preferably on the surface of the substrate 12. Thus, an upper face of the trench 14 is coplanar with an upper face of the substrate 12. The region 14 is preferably made of an oxide, for example silicon oxide.

[0034] The step of [Fig.l] further comprises forming an insulating layer 16 on the structure. More specifically, the layer 16 covers the upper face of the substrate 12 and the trench 14. The layer 16 preferably completely covers the trench 14. The layer 16 is preferably in contact with the trench 14 and with the substrate 12. The layer 16 is preferably made of the same material as the region 14. The sum of the thicknesses of the layer 14 and of the trench 14 are preferably less than 70 nm, for example substantially equal to 50 nm.

[0035] The step of [Fig.l] further comprises the formation of a layer 18. The layer 18 is made of the material of the base of the transistor 10. The layer 18 is for example made of a semiconductor material. The layer 18 is for example made of polycrystalline silicon, for example P-type doped. The layer 18 covers at least the trench 14. The layer 18 is preferably in contact with the layer 16. The layer 18 preferably extends over the entire layer 16.

[0036] The step of [Fig.l] comprises the formation of a layer 20. The layer 20 is made of a single material, preferably a homogeneous material. The layer 20 is preferably a single layer and is preferably not composed of other layers. The layer 20 is an insulating layer. The layer 20 is for example made of silicon nitride.

[0037] The layer 20 covers at least the trench 14. Preferably, the layer 20 extends over the entire layer 18. The layer 20 rests on, and is in contact with, the layer 18. Preferably, the layer 20 is not separated, even partially, from the layer 18 by another layer or portion of a layer.

[0038] The sum of the thicknesses of the trench 14 and the layers 16, 18 and 20 is preferably less than 230 nm, preferably less than 200 nm, preferably less than or substantially equal to 150 nm.

[0039] [Fig.2] represents a device resulting from another step of the manufacturing process of the bipolar transistor 10.

[0040] The step of [Fig. 2] comprises a step of etching the structure so as to reach the substrate 12 at the level of the trench 14. In other words, the step of [Fig. 2] comprises the formation of a cavity 22. The cavity 22 passes through a stack comprising the layers 16, 18, 20 and the trench 14. The cavity thus reaches the substrate 12. The bottom of the cavity 22 is thus constituted by a portion of the substrate 12. The bottom of the cavity 22 is preferably substantially coplanar with the lower face of the trench 14.

[0041] Said stack preferably does not comprise any layer other than layers 16, 18, 20 and trench 14. Said stack comprises a single layer, i.e. layer 20, above layer 18. In other words, during the step of etching the stack, layer 18 is covered, for example at least opposite trench 14, for example at least opposite the location of the bipolar transistor, only with insulating layer 20. The etching step of step 2 does not comprise the etching of any layer covering layer 18 other than layer 20.

[0042] The height of the cavity 22 is preferably less than 230 nm, preferably less than 200 nm, preferably less than or substantially equal to 150 nm.

[0043] The step of [Fig. 2] may, optionally, comprise the formation of spacers 24. The spacers 24 are located on the side walls of the cavity 22. The spacers cover the side walls of the layers in the cavity 22. Thus, the side walls of the layers 16, 18, 20 and of the trench 14 forming the walls of the cavity 22 are covered, for example entirely covered, by the spacers 24.

[0044] [Fig.3] represents a device resulting from another step of the bipolar transistor manufacturing process.

[0045] The step of [Fig. 3] comprises a step of epitaxial growth of the substrate 12 in the cavity 22. The step of [Fig. 3] thus comprises the formation of a region 26 in the cavity 22.

[0046] The region 26 preferably extends from the bottom of the cavity 22 to a level higher than the level of the upper face of the layer 18, and preferably lower than the level of the upper face of the layer 20. The side walls of the layer 18 located at the level of the side walls of the cavity 22 are thus entirely separated by the region 26 and the spacers 24.

[0047] Region 26 is in contact with substrate 12 and with spacers 24. Region 26 is thus separated from layers 16, 18, 20 and trench 14 by spacers 24.

[0048] Region 26 is made of a semiconductor material, for example silicon, for example N-type doped silicon. Region 26 is preferably made of the material of substrate 12. Region 26 preferably corresponds to a portion of the collector of bipolar transistor 10.

[0049] [Fig.4] represents a device resulting from another step of the bipolar transistor manufacturing process.

[0050] The step of [Fig. 4] comprises the partial etching of the spacers 24. More precisely, the portions of the spacers located above the level of the upper face of the region 26 are etched. Thus, the upper faces of the spacers 24 are preferably, after etching, substantially coplanar with the upper face of the region 26.

[0051] The step of [Fig.4] further comprises the formation of a region 28. The region 28 is for example by epitaxial growth, for example from the region 26. The region 28 preferably fills the cavity 22. The region 28 preferably extends from the level of the upper faces of the spacers 24 and of the region 26. The region 28 extends between the lateral faces of the layer 20 located in the cavity 22. Thus, the region 28 is laterally in contact with the layer 20, preferably only with the layer 20. Preferably, the region 28 is preferably not in contact with the layer 18. The region 28 is in contact with the region 26 and the spacers 24.

[0052] The upper face of the structure, corresponding to the upper face of region 28 and the upper face of layer 20, is preferably flat.

[0053] Region 28 is made of a semiconductor material, for example silicon, for example P-type doped silicon. Region 28 corresponds to a portion of the base region of transistor 10.

[0054] [Fig.5] represents a device resulting from another step of the bipolar transistor manufacturing process.

[0055] During this step, a layer 30 is formed on the structure. More precisely, the layer 30 preferably covers the upper face of the layer 20 and the upper face of the region 28. The layer 30 for example completely covers the layer 20 and the region 28. The layer 30 is preferably in contact with the region 28 and the layer 20, preferably with the entire upper face of the region 28 and the layer 20. The layer 30 is for example made of the same material as the layer 16. The layer 30 is for example made of silicon oxide. The layer 30 has for example a thickness of between 4 nm and 20 nm.

[0056] The step of [Fig.5] further comprises the formation of a layer 32. The layer 32 preferably covers layer 30, preferably completely layer 30. Layer 32 is preferably in contact with layer 30, preferably in contact with the entire layer 30. Layer 32 is preferably made of the same material as layer 20, for example silicon nitride. Layers 30 and 32 are preferably made of different materials. The material of layer 32 is preferably made of a material that is selectively etchable relative to the material of layer 30. By selectively etchable, it is meant that the material of layer 32 can be etched, by an etching process, at least twice as fast as the material of layer 30, for example at least ten times faster. The thickness of layer 32 is for example between 8 nm and 40 nm.

[0057] [Fig.6] represents a device resulting from another step of the bipolar transistor manufacturing process.

[0058] During this step, a cavity 34 is formed in the layers 30 and 32, preferably only in the layers 30 and 32. The cavity 34 is located opposite the cavity 22. In other words, the cavity 34 is located opposite the regions 26 and 28. The cavity 34 extends over the entire height of the layers 30 and 32. The cavity 34 thus reaches the region 28. The bottom of the cavity 34 is formed by the upper face of the region 28, preferably only the upper face of the region 28. The side walls of the cavity 34 are formed by side walls of the layers 30 and 32. The layer 32 is for example physically etched by a succession of a photolithography process then dry etching. The layer 32 then serves as masking for a wet (isotropic) etching step of the layer 30.

[0059] The dimensions of the cavity 34, in particular the horizontal dimensions, that is to say for example in a plane parallel to the plane of the upper face of the layer 20, are for example smaller than the dimensions of the cavity 22, in particular the horizontal dimensions of the cavity 22. Thus, a part of the upper face of the region 28 is not uncovered by the etching forming the cavity 34. In other words, a portion of the layers 30, 32, preferably a portion located opposite the region 28 and surrounding the cavity 34, is not etched during the step of [Fig.6].

[0060] [Fig.7] represents a device resulting from another step of the bipolar transistor manufacturing process.

[0061] During this step, layer 32 is removed. Layer 30 is thus uncovered. Preferably, layer 32 is completely removed. Layer 30 is thus preferably completely uncovered.

[0062] The cavity 34 is thus replaced by a cavity, or opening, 34' corresponding to the part of the cavity 34 defined by the layer 30 and the region 28.

[0063] [Fig.8] represents a device resulting from another step of the bipolar transistor manufacturing process.

[0064] During this step, a layer 36 is formed on the structure. More specifically, the layer 36 preferably covers the upper face of the layer 30 and the bottom and walls of the cavity 34'. The layer 36 thus preferably covers the upper face of the layer 30, the side walls of the layer 30 forming the side walls of the cavity 34' and the portion of the upper face of the region 28 forming the bottom of the cavity 34'. The layer 36 for example completely covers the layer 30 and the walls and bottom of the cavity 34'. Layer 36 is preferably in contact with region 28 in cavity 34' and layer 30. Layer 36 is made of the material of the emitter region of bipolar transistor 10. Layer 36 is for example made of polycrystalline silicon, for example N-type doped polycrystalline silicon. Layer 36 has for example a thickness of between 50 nm and 100 nm. Layer 30 is for example substantially ten times smaller than layer 36..

[0065] The step of [Fig.8] further comprises the formation of a layer 38. The layer 38 preferably covers the layer 36, preferably the entire layer 36. The layer 38 is preferably in contact with the layer 36, preferably in contact with the entire layer 36. The layer 38 is preferably made of the same material as the layer 30, for example silicon oxide.

[0066] Since the layer 30 has a small thickness compared to the thickness of the layer 36, the upper face of the layer 36 is substantially flat and does not include any depression.

[0067] It would have been possible to choose, as in usual methods, to form, at the step of [Fig.l], a stack of a greater number of insulating layers, so as to form L-shaped insulating elements on the upper face of the region 28 so as to delimit the cavity 34'. The layers 36 and 38 would then not be flat and would form a depression at the level of the cavity 34'. Such a depression would cause contact problems with the emitter of the bipolar transistor.

[0068] [Fig.9] represents a device resulting from another step of the bipolar transistor manufacturing process.

[0069] During this step, layers 30, 36, 38 are partially etched. In other words, layers 30, 36, 38 are entirely etched except for portions of each of layers 30, 36, 38 located opposite region 28. Layers 38 and 36 are for example etched by a succession of photolithography and dry (anisotropic) etching. Layer 30 serves as a stop layer for this etching. Then, layer 30 is etched by wet (isotropic) chemistry.

[0070] Thus, following the partial etching of the layers 30, 36, 38, a portion of each layer 30, 36, 38 is held facing the region 28. Said portion of the layer 30 surrounds and delimits the cavity 34'. The portion of the layer 36 fills the cavity 34' and preferably completely covers the portion of the layer 30. The portion of the layer 38 preferably completely covers the layer 36. The portions of the layers 30, 36, 38 preferably have coplanar side walls. Preferably, a portion of the upper face of the region 28, for example a portion surrounding the portion covered by the portion of the layer 30, is not covered by the portions of layers 30, 36, 38.

[0071] The step of [Fig.9] further comprises the formation of a layer 40 made of an insulating material, for example the same material as the layer 16, for example silicon oxide. The layer 40 covers the side walls of the layer portions 30, 36, 38 and the upper face of the layer portion 38. The layer 40 covers for example a portion of the upper face of the region 28 surrounding the layer portions 30, 36, 38. The layer 40 does not cover the layer 20.

[0072] The step of [Fig.9] then comprises the removal, for example by etching, of the layer 20. The layer 20 is preferably entirely removed. At least a portion of the layer 20 surrounding the region 28 is removed. At least a portion of the layer 18 surrounding the region 26 is thus uncovered.

[0073] The step of [Fig.9] then comprises the epitaxial growth of layer 18. The growth of layer 18 is maintained until layer 18 is in lateral contact with region 28. Thus, the upper face of layer 18 is at a level higher than the level of the lower face of region 28. Preferably, the upper face of layer 18 is at a level lower than the level of the upper face of region 28. For example, the upper face of layer 18 and the upper face of region 28 are coplanar.

[0074] [Fig. 10] represents a device resulting from another step in the bipolar transistor manufacturing process.

[0075] During this step, layers 16 and 18 are partially etched. More precisely, layers 16 and 18 are partially etched so as to uncover the upper face of substrate 12. Layer 16 is for example etched so that a portion of layer 16 at least partially covers wafer 14. Thus, the portions of layer 16 covering substrate 12 around trench 14 are removed. In addition, layer 18 is partially etched so that a portion of layer 18 surrounding region 28 is maintained. Thus, said portion of layer 18 surrounds region 28 and is in lateral contact with region 28.

[0076] The step of [Fig. 10] further comprises the formation of contact pads. In particular, the step of [Fig. 10] comprises: - the formation of contact pads 42, resting on the substrate 12 and corresponding to collector contact pads; - the formation of contact pads 44, resting on the layer 18 and corresponding to base contact pads; - the formation of contact pads not shown, resting on layer 36 and corresponding to emitter contact pads.

[0077] An advantage of the described embodiments is that the etching of the cavity 22 involves the etching of a stack that is less thick and therefore easier to etch. It is therefore possible to make a smaller cavity, for example having critical dimensions less than 200 nm.

[0078] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0079] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A method of manufacturing a bipolar transistor (10) comprising: a. forming, on a substrate (12), a first stack of layers comprising a first layer (18) of the material of the base of the bipolar transistor between second (16) and third (20) insulating layers; b. forming a first cavity (22) passing through the first stack so as to reach the substrate (12), the step of forming the first cavity (22) does not include etching any layer covering the first layer (18) other than the third insulating layer (20) which is a single layer; and c. forming a first portion (26) of the collector of the bipolar transistor and a second portion (28) of the base of the bipolar transistor in the first cavity.

2. The method of claim 1, wherein the first (26) and second (28) portions are formed by epitaxial growth.

3. The method of claim 1 or 2, wherein the first portion (26) is closer to the bottom of the first cavity (22) than the second portion (28).

4. A method according to any one of claims 1 to 3, wherein the method comprises, after step c., a step d. of forming a fourth insulating layer (30) covering an upper face of the third layer (20) and an upper face of the second portion (28), the fourth layer (30) comprising an opening (34') uncovering a part of an upper face of the second portion (28).

5. The method of claim 4, wherein the fourth layer (30) is planar.

6. Method according to claim 4 or 5, in which the method comprises, after step d., a step e. of forming a second stack of layers comprising a fifth layer (36) made of the emitter material of the bipolar transistor and a sixth insulating layer (38) covering the fifth layer (36).

7. The method of claim 6, wherein the fifth layer (36) is in contact with the fourth layer (30) and fills the opening (34') in the fourth layer (30).

8. A method according to claim 6 or 7, wherein the thickness of the fifth layer (36) is substantially equal to ten times the thickness of the fourth layer (30).

9. A method according to any one of claims 6 to 8, wherein the method comprises partially etching the fourth (30), fifth (36) and sixth (38) layers.

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