Image sensor

Abstract

Image Sensor This description relates to an image sensor comprising a plurality of pixels (100) formed in and on a semiconductor substrate (104), each pixel comprising: – a photosensitive area (102) formed in the semiconductor substrate (104); – a peripheral isolation trench (106) extending vertically in the semiconductor substrate (104), from an upper face of the semiconductor substrate, and laterally delimiting the photosensitive area (102); – a charge collection area (110); – a transfer region (114) located in the semiconductor substrate (104) and extending vertically between the charge collection area (110) and the photosensitive area (102);and – a transfer grid (108) extending vertically into the semiconductor substrate (104), from the upper face of the semiconductor substrate and inside the peripheral insulation trench (108), deeper than the charge-collecting zone (110), in which the transfer region (114) is doped with the same first type of conductivity as the photosensitive zone (102) and has a doping level strictly lower than that of the photosensitive zone. Figure for the abstract: Fig. 1B;

Description

Title of the invention: Image sensor Technical field

[0001] The present description relates generally to electronic devices, more particularly to image sensor pixels. Prior art

[0002] Image sensor pixels each comprising a photosensitive area formed in a semiconductor substrate, adapted to convert light into electron-hole pairs, have been proposed. During an exposure phase of the sensor, photogenerated charges (electrons or holes) accumulate in the photosensitive area. During a subsequent reading phase, a charge transfer device is controlled to transfer the photogenerated charges, accumulated in the photosensitive area, to a charge collection area.

[0003] US patent application US 2021 / 0020675 describes examples of such pixels. In this application, each pixel more specifically comprises a photosensitive area formed in a semiconductor substrate and bordered laterally by a peripheral isolation trench. Each pixel further comprises a charge collection area interposed laterally between a vertical transfer gate, formed in the peripheral isolation trench, and an implanted region formed in the semiconductor substrate above the photosensitive area. The photosensitive area and the charge collection area are P-type doped, and the implanted region is N-type doped. In this example, a P-type doped transfer region having a doping level equal to that of the photosensitive area is interposed vertically between the photosensitive area and the charge collection area.By applying a potential to the vertical transfer gate of the pixel, a potential barrier can be formed in the transfer region between the vertical transfer gate and the N-type implanted region. This image sensor pixel, however, has various disadvantages, including the fact that it is difficult to form the N-type implanted region accurately. This makes it difficult to reduce the pixel pitch of the image sensor. Furthermore, pixels of this type have a relatively high dark current, which would be desirable to reduce. Summary of the invention

[0004] There is a need to overcome all or part of the disadvantages of image sensor pixels and known image sensors. In particular, it would be desirable to reduce the dimensions of the pixels, so as to allow the production of image sensors having pixel pitches smaller than those of existing image sensors.

[0005] For this, one embodiment provides an image sensor comprising a plurality of pixels formed in and on a semiconductor substrate, each pixel comprising: - a photosensitive zone formed in the semiconductor substrate; - a peripheral insulation trench extending vertically in the semiconductor substrate, from an upper face of the semiconductor substrate, and laterally delimiting the photosensitive zone; - a charge collection area; - a transfer region located in the semiconductor substrate and extending vertically between the charge collection area and the photosensitive area; and - a transfer gate extending vertically in the semiconductor substrate, from the upper face of the semiconductor substrate and inside the peripheral isolation trench, deeper than the charge collection zone, in which the transfer region is doped with the same first conductivity type as the photosensitive zone and has a doping level strictly lower than that of the photosensitive zone.

[0006] According to one embodiment, the transfer gate extends vertically in the semiconductor substrate to a depth substantially equal to that of the transfer region.

[0007] According to one embodiment, the photosensitive zone and the transfer region have a substantially horizontal interface.

[0008] According to one embodiment, the charge collection zone is doped with the first conductivity type and has a doping level strictly higher than that of the transfer region.

[0009] According to one embodiment, the sensor further comprises a doped box of a second conductivity type opposite to the first conductivity type, the box extending vertically in the semiconductor substrate, from the upper face of the semiconductor substrate, to a depth less than that of the transfer gate.

[0010] According to one embodiment, the sensor further comprises an electrically insulating trench interposed laterally between the charge collection zone and the box.

[0011] According to one embodiment, the electrically insulating trench extends vertically in the semiconductor substrate, from the upper face of the semiconductor substrate, to a depth greater than that of the charge collection zone.

[0012] According to one embodiment, the charge collection zone and the box are adjacent.

[0013] According to one embodiment, the peripheral isolation trench and the transfer grid respectively comprise first and second electrically conductive regions, the first electrically conductive region being electrically insulated from the second electrically conductive region.

[0014] According to one embodiment, the second electrically conductive region is flush with the upper face of the semiconductor substrate.

[0015] According to one embodiment, the second electrically conductive region is separated from the upper face of the semiconductor substrate by a non-zero thickness of insulating material.

[0016] According to one embodiment, the transfer grid is common to two pixels.

[0017] According to one embodiment, the transfer grid is common to four pixels.

[0018] According to one embodiment, the first type of conductivity is type N.

[0019] According to one embodiment, the sensor further comprises a control circuit configured to apply alternately, on the transfer grid: - a first potential adapted to block a transfer of charges from the photosensitive zone to the charge collection zone; and - a second potential, different from the first potential, adapted to allow a transfer of charges from the photosensitive zone to the charge collection zone. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.lA] and [Fig.lB] are schematic and partial views, respectively from above and in section along plane BB of [Fig.lA], of an example of an image sensor pixel according to one embodiment;

[0022] [Fig.2A] and [Fig.2B] are schematic and partial views, respectively from above and in section along plane BB of [Fig.2A], of an example of an image sensor pixel according to one embodiment;

[0023] [Fig.3A] and [Fig.3B] are schematic and partial views, respectively from above and in section along plane BB of [Fig.3A], of an example of an image sensor pixel according to one embodiment;

[0024] [Fig.4] is a schematic and partial top view of an arrangement of two adjacent pixels according to one embodiment; and

[0025] [Fig.5] is a schematic and partial top view of an arrangement of four adjacent pixels according to one embodiment. Description of the embodiments

[0026] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0027] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the methods for manufacturing the image sensor pixels have not been detailed, the described embodiments and variants being compatible with the usual methods for manufacturing image sensor pixels. Furthermore, the circuits (transistors and connections) of the pixels have not been detailed, the described embodiments and variants being compatible with the usual pixel circuits.Furthermore, the reading circuits, or column decoders, the control circuits, or row decoders, and the applications in which image sensors can be provided have not been detailed, the embodiments and variants described being compatible with the reading circuits and the control circuits of conventional image sensors, as well as with conventional applications implementing image sensors.

[0028] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0030] Unless otherwise specified, the expressions “about”, “approximately”, “substantially”, and “of the order of” mean to within 10%, preferably to within 5%.

[0031] [Fig.lA] and [Fig.lB] are schematic and partial views, respectively from above and in section along the plane BB of [Fig.lA], of an example of a pixel 100 of an image sensor according to one embodiment.

[0032] In the example shown, the pixel 100 comprises a photosensitive zone 102, or photoconversion zone. The photosensitive zone 102 is for example intended to collect photons, during illumination phases of the image sensor of which the pixel 100 is part, and to convert these photons into electron-hole pairs. The photosensitive zone 102 is located, in top view, at the center of the pixel 100 and has a substantially square-shaped perimeter. This example is however not limiting, the photosensitive zone 102 being able, as a variant, to have a perimeter of any shape, for example rectangular or circular.

[0033] The photosensitive zone 102 is formed in a substrate 104. The substrate 104 is made of a semiconductor material, for example silicon. For example, the substrate 104 is formed by epitaxial growth, or epitaxy, of a layer of semiconductor material on the side of a face of a wafer or a piece of wafer made of a semiconductor material, for example silicon. For example, the substrate 104 has a thickness of between 1 and 20 μm.

[0034] The substrate 104 is doped with a first conductivity type, for example the N type. In this case, the substrate 104 is for example doped with arsenic atoms. For example, the substrate 104 has a doping level or rate of between 1 x 1010 and 1 x 1018 at. / cm3.

[0035] The photosensitive area is for example intended to be illuminated from a lower face of the substrate 104, in the orientation of [Fig. 1B]. As a variant, the photosensitive area may be intended to be illuminated from an upper face of the substrate 104, in the orientation of [Fig. 1B]. Although this has not been illustrated in [Fig. 1B], the lower face of the substrate 104 may be coated with one or more passivation layers. Furthermore, the pixel 100 may comprise, on the side of the lower face of the substrate 104, optical elements such as a filter, for example a color filter, and / or a microlens.

[0036] In the example shown, the pixel 100 comprises a peripheral isolation trench 106, for example a capacitive isolation trench, laterally delimiting the photosensitive zone 102. By way of example, the peripheral isolation trench 106 is a so-called “deep” capacitive isolation trench (“Capacitive Deep Trench Isolation” (CDTI, in English). In top view, the peripheral isolation trench 106 has an annular shape completely surrounding the photosensitive zone 102 on all its side walls, or flanks. The peripheral isolation trench 106 has a periphery of a shape identical to that of the photosensitive zone 102, that is to say of a square shape, in the example illustrated. This example is however not limiting, the peripheral isolation trench 106 being able, as a variant, to have a periphery of any shape, for example rectangular or circular.In the illustrated example, the peripheral isolation trench 106 comprises four parts corresponding respectively to the four sides of the square formed by the trench 106.

[0037] The peripheral isolation trench 106 makes it possible in particular to electrically isolate the photosensitive zone 102 of the pixel 100 from the photosensitive zones of the neighboring pixels, not shown in FIGS. 1A and 1B. The peripheral isolation trench 106 is for example formed in the substrate 104. In the orientation of [Fig. 1B], the peripheral isolation trench 106 extends vertically in the thickness of the substrate 104, from an upper face of the substrate 104, to the lower face of the substrate 104. In other words, in this example, the peripheral isolation trench 106 extends vertically across the entire thickness of the substrate 104.

[0038] The peripheral isolation trench 106 has, for example, a width of between 20 and 300 nm, for example equal to approximately 160 nm, and a depth of between 10 and 20 μm. In the example illustrated in [Fig. 1B], the peripheral isolation trench 106 has a depth equal to the thickness of the substrate 104.

[0039] In the example shown, the peripheral insulation trench 106 comprises an electrically conductive region 106C. For example, the electrically conductive region 106C of the peripheral insulation trench 106 is made of polycrystalline silicon, a metal, for example copper, or a metal alloy. In the case where the region 106C is made of polycrystalline silicon, the region 106C has for example a doping rate greater than or equal to 1 x 1018 at. / cm3.

[0040] The peripheral insulation trench 106 further comprises, in this example, an electrically insulating layer 1061 coating the side walls of the electrically conductive region 106C. The electrically insulating layer 1061 electrically insulates the electrically conductive region 106C relative to the substrate 104. By way of example, the electrically insulating layer 1061 is made of a dielectric material, for example silicon oxide.

[0041] In the example shown, the pixel 100 further comprises a vertical transfer grid 108 formed inside the peripheral isolation trench 106. The vertical transfer grid 108 is for example located, in top view, in one of the sides of the square formed by the peripheral isolation trench 106 (the left side, in the orientation of [Fig. 1B]). In the example shown, the vertical transfer grid 108 comprises an electrically conductive region 108C extending vertically in the thickness of the substrate 104, from the upper face of the substrate 104, to a depth less than that of the peripheral isolation trench 106. By way of example, the vertical transfer grid 108 has a depth, or height, of between 0.2 and 1.5 μm.

[0042] The electrically conductive region 108C of the vertical transfer gate 108 is electrically insulated from the electrically conductive region 106C of the peripheral insulation trench 106. In the illustrated example, the side walls and the bottom of the electrically conductive region 108C of the vertical transfer gate 108 are coated with the electrically insulating layer 1061 of the peripheral insulation trench 106. Furthermore, in this example, the electrically conductive region 108C of the vertical transfer gate 108 is flush with the upper face of the substrate 104. By way of example, the electrically conductive region 108C of the vertical transfer gate 108 is made of polycrystalline silicon, a metal, for example copper, or a metal alloy. In the case where the region 108C is made of polycrystalline silicon, the region 108C for example has a doping rate greater than or equal to 1 x 1018 at. / cm3.

[0043] In the illustrated example, the pixel 100 further comprises a charge collection zone 110 extending vertically in the semiconductor substrate 104, from its upper face, to a depth less than that of the electrically conductive region 108C of the vertical transfer gate 108. In the example shown, the charge collection zone 110 has, in top view, a periphery of substantially square shape. This example is however not limiting, the charge collection zone 110 being able to have, as a variant, a periphery of any shape, for example rectangular or circular. By way of example, the square formed by the charge collection zone 110 has a side between 100 and 200 nm, for example equal to approximately 170 nm.

[0044] In the example shown, the charge collection area 110 is surrounded by an electrically insulating trench 112. The insulating trench 112 extends vertically in the semiconductor substrate 104, from its upper face, to a depth greater than that of the charge collection area 110 and less than that of the electrically conductive region 108C of the vertical transfer gate 108. In the example shown, the electrically insulating trench 112 covers three of the four lateral faces of the charge collection area 110, the fourth lateral face of the charge collection area 110 being covered with the electrically insulating layer 1061 of the peripheral insulating trench 106. The insulating trench 112 is for example based on an oxide, for example silicon oxide. By way of example, the insulating trench 112 has a width equal to approximately 40 nm.

[0045] The charge collection zone 110 is doped with the first conductivity type (N type, in this example) and has, for example, a doping level higher than that of the photosensitive zone 102. For example, the doping level of the charge collection zone 110 is between 1 x 1016 and 5 x 1020 at. / cm3.

[0046] In the illustrated example, the pixel 100 further comprises a transfer region 114 formed in the substrate 104 and extending vertically between the charge collection zone 110 and the photosensitive zone 102. The transfer region 114 extends, for example, in the thickness of the substrate 104 to a depth substantially equal to that of the conductive region 108C of the transfer gate 108. In the example shown, the transfer region 114 has, in top view, a periphery of substantially square shape. This example is not, however, limiting, the transfer region 114 being able, as a variant, to have a periphery of any shape, for example rectangular or circular. In the illustrated example, three of the four sides of the square formed by the transfer region 114 are bordered laterally by the peripheral insulation trench 106, and the fourth side of the transfer region 114 is essentially bordered laterally by the vertical transfer grid 108.

[0047] According to one embodiment, the transfer region 114 is doped with the first conductivity type (the N type, in this example) and has a doping level strictly lower than that of the photosensitive zone 102. Furthermore, the doping level of the transfer region 114 is for example strictly lower than that of the charge collection zone 110. By way of example, the transfer region 114 has a doping level of between 1 x 1010 and 9 x 1017 at. / cm3.

[0048] Advantageously, the highest possible doping level gradient is formed at the interface between the photosensitive area 102 and the transfer region 114 (so-called "abrupt" interface). Furthermore, in the example shown, the interface between the transfer region 114 and the photosensitive area 102 is substantially horizontal and located at a depth approximately equal to the depth to which the vertical transfer gate 108 extends. N-type doping of the photosensitive area 102, of the transfer region 114 and of the charge collection area 110 is preferred, because the atoms used to obtain N-type doping, for example arsenic atoms, diffuse less than the atoms used to obtain P-type doping, for example boron atoms.Providing that the photosensitive area 102, the transfer region 114 and the charge collection area 110 are N-type doped advantageously makes it possible to obtain an interface between the photosensitive area 102 and the transfer region 114 that is more abrupt than in the case of P-type doping. The diffusion of boron atoms could however be limited by using reduced thermal budgets during the manufacture of the pixel 100 or by introducing chemical elements making it possible to block the diffusion of boron atoms.

[0049] In the example shown, the pixel 100 further comprises a well 116 extending vertically in the thickness of the substrate 104, from its upper face, to a depth less than that of the vertical transfer gate 108, for example to a depth substantially equal to that of the charge collection zone 110. In the example illustrated, the well 116 is bordered laterally by the peripheral isolation trench 106 and by the insulating trench 112, the insulating trench being interposed laterally between the charge collection zone 110 and the well 116. The well 116 is doped with a second type of conductivity, opposite to the first type of conductivity (the P type, in this example). In the case where the well 116 is doped with the P type, the doping is for example obtained by boron atoms. For example, box 116 has a doping level between 1 x 1016 and 1 x 1019 at. / cm3.

[0050] In the example shown, the insulating trench 112 advantageously makes it possible to avoid or attenuate field effects between the charge collection zone 110 and the box 116.

[0051] In the illustrated example, the pixel 100 comprises another box 118 formed in the box 116 and extending vertically in the thickness of the substrate 104, from its upper face, to a depth less than that of the box 116. The box 118 is formed in one of the corners of the box 116 opposite the vertical transfer grid 108. In practice, the box 118 can extend laterally, as in the example shown, inside the peripheral isolation trench 106. The box 118 is doped with the second type of conductivity (the P type, in this example) and has a doping level strictly higher than that of the box 116. For example, the doping level of the box 118 is between 1 x 1017 and 5 x 1020 at. / cm3.

[0052] In the example shown, the pixel 100 further comprises contact recovery elements 120A, 120B, 120C and 120D, for example conductive pads, respectively formed on and in contact with the conductive region 106C of the peripheral insulation trench 106, the conductive region 108C of the vertical transfer gate 108, the charge collection zone 110 and the box 118. In the example shown, each contact recovery element 120A, 120B, 120C, 120D has, in top view, a periphery of substantially square shape. This example is however not limiting, each contact recovery element 120A, 120B, 120C, 120D being able, as a variant, to have a periphery of any shape, for example rectangular or circular. The contact recovery elements 120A, 120B, 120C and 120D are made of an electrically conductive material, for example a metal, for example copper, or a metal alloy.For example, each contact recovery element 120A, 120B, 120C, 120D has a maximum lateral dimension (for example one side, in the example shown where each contact recovery element is square in shape) equal to approximately 90 nm.

[0053] During an exposure or accumulation phase of the pixel 100, electron-hole pairs are for example created inside the photosensitive zone 102. During this phase, the electrically conductive region 106C of the peripheral isolation trench 106 and the electrically conductive region 108C of the vertical transfer gate 108 are brought to potentials V_CDTI and V_TG_OFF respectively. In the example shown, the potentials V_CDTI and V_TG_OFF are applied by means of the contact recovery elements 120A and 120B, respectively. The potential V_TG_OFF is for example substantially equal to the potential V_CDTI. During the exposure phase, the application of the potentials V_CDTI and V_TG_OFF to the electrically conductive regions 106C and 108C makes it possible to form a potential barrier in the transfer region 114, between the photosensitive zone 102 and the charge collection zone 110.In the example shown, the transfer region 114 is bordered by the internal side walls of the peripheral isolation trench 106 and the vertical transfer grid 108 and extends vertically, in the thickness of the substrate 104, under the charge collection zone 110. In other words, the potential barrier formed. jointly by the peripheral isolation trench 106 and the vertical transfer grid 108 extends laterally, in top view, over the entire surface of the transfer region 114.

[0054] The presence of the potential barrier in the transfer region 114 makes it possible, during the exposure phase, to block a transfer of photogenerated carriers (electrons, in the case where the photosensitive zone 102, the transfer region 114 and the charge collection zone 110 are of N type) from the photosensitive zone 102 to the charge collection zone 110. This potential barrier results from the presence, along the side walls of the peripheral isolation trench 106 and the transfer grid 108, of an inversion layer attracting carriers of the opposite type to the substrate (holes, in this example).

[0055] During the exposure phase, the charge collection zone 110 and the well 118 are respectively brought to potentials V_SN and V_WELL. In the example shown, the potentials V_SN and V_WELL are applied by means of the contact recovery elements 120C and 120D, respectively. The contact recovery element 120D makes it possible, for example, to provide the charge carriers making it possible to form the potential barrier inside the transfer region 114 during the exposure phase.

[0056] During a reading phase subsequent to the exposure phase, the electrically conductive region 108C of the vertical transfer gate 108 is for example brought to a potential V_TG_ON different from the potential V_TG_OFF, the electrically conductive region 106C of the peripheral isolation trench 106 being maintained at the potential V_CDTI. During the reading phase, the application of the potential V_TG_ON to the electrically conductive region 106C makes it possible to lower, or even eliminate, the potential barrier in the transfer region 114 between the photosensitive zone 102 and the charge collection zone 110. The disappearance of the potential barrier allows, during the reading phase, a transfer of the photogenerated charges from the photosensitive zone 102 to the charge collection zone 110.

[0057] By way of example, the image sensor comprising the pixel 100 further comprises a control circuit configured to alternately apply, to the contact recovery element 120B connected to the conductive region 108C of the transfer grid 108: - the potential V_TG_OFF adapted to block a transfer of charges from the photosensitive zone 102 to the charge collection zone 110; and - the potential V_TG_ON adapted to allow a transfer of charges from the photosensitive zone 102 to the charge collection zone 110.

[0058] During the reading phase, the charge collection zone 110 and the well 118 are for example respectively maintained at the potentials V_SN and V_WELL. Although this has not been detailed in figures 1A and 1B, the contact recovery element 120C is for example connected or linked to a reading circuit, for example located on the side of the upper face of the substrate 104. The contact recovery element 120C is for example more precisely connected to a reading node, not shown, and makes it possible to transfer charges accumulated in the charge collection zone 110 to the reading node.

[0059] For example: - in the case where the photosensitive zone 102, the transfer region 114 and the charge collection zone 110 are of type N and where the boxes 116 and 118 are of type P: the potential V_TG_ON is equal to approximately 1.8 V; the potential V_TG_OFF is equal to approximately -0.5 V; the potential V_CDTI is equal to approximately -0.5 V; the potential V_WELL is equal to approximately 0.2 V; and the potential V_SN is equal to approximately 1.8 V, and - in the case where the photosensitive zone 102, the transfer region 114 and the charge collection zone 110 are of type P and where the boxes 116 and 118 are of type N: the potential V_TG_ON is equal to 0 V; the potential V_TG_OFF is equal to approximately 1.8 V; the potential V_CDTI is equal to approximately 1.8 V; the potential V_WELL is equal to approximately 1.5 V; and the potential V_SN is equal to approximately 0.5 V.

[0060] In the example above, the potential V_TG_ON is equal to the potential V_SN. This example is not, however, limiting, the potential V_TG_ON being able, as a variant, to be different from the potential V_SN.

[0061] In a sensor comprising a plurality of pixels arranged in a matrix according to rows and columns, the term "pixel pitch" refers to the center-to-center distance between two neighboring pixels in the direction of the rows or columns. The pixel pitch in the direction of the rows or columns corresponds substantially to the lateral dimension of the pixel in said direction.

[0062] An advantage of the sensor integrating pixels of the type of pixel 100 described above is that it can have a pixel pitch, in the direction of the rows and in the direction of the columns, lower than that of existing sensors, for example less than 1 pm, for example between 0.6 and 0.8 pm.

[0063] [Fig.2A] and [Fig.2B] are schematic and partial views, respectively from above and in section along the plane BB of [Fig.2A], of an example of a pixel 200 of an image sensor according to one embodiment.

[0064] The pixel 200 of Figures 2A and 2B comprises elements in common with the pixel 100 of Figures 1A and 1B. These common elements will not be detailed again below. Pixel 200 of Figures 2A and 2B differs from pixel 100 of Figures 1A and 1B in that pixel 200 is devoid of the electrically insulating trench 112. This makes it easier to produce pixel 200 compared to pixel 100.

[0065] In this example, the charge collection zone 110 and the box 116 are adjacent. This example is however not limiting, the charge collection zone 110 being able, as a variant, to be separated from the box 116 by a part of the transfer region 114 extending laterally between the zone 110 and the box 116. This advantageously makes it possible to reduce an electric field at the origin of a dark current.

[0066] [Fig.3A] and [Fig.3B] are schematic and partial views, respectively from above and in section along the plane BB of [Fig.3A], of an example of a pixel 300 of an image sensor according to one embodiment.

[0067] The pixel 300 of Figures 3A and 3B comprises elements in common with the pixel 100 of Figures 1A and 1B. These common elements will not be detailed again below. The pixel 300 of Figures 3A and 3B differs from the pixel 100 of Figures 1A and 1B in that the electrically conductive region 108C of the vertical transfer gate 108 of the pixel 300 is separated from the upper face of the substrate 104 by a non-zero thickness of electrically insulating material, for example an oxide, for example the material of the insulating layer 1061 of the peripheral insulation trench 106. In other words, the electrically conductive region 108C of the transfer gate 108 of the pixel 300 is not flush with the upper face of the substrate 104. This advantageously makes it possible to reduce a capacitance between the conductive region 108C of the vertical transfer gate 108 and the charge collection zone 110 compared to the case of the pixel 100.

[0068] [Fig.4] is a schematic and partial top view of an arrangement 400 of two adjacent pixels 100 according to one embodiment.

[0069] In the example shown, the two pixels 100 are juxtaposed so that they share a portion of the peripheral isolation trench 106. In the orientation of [Fig. 4], the left pixel 100 is symmetrical to the right pixel 100 with respect to a vertical axis. The vertical transfer grid 108 is formed in the portion of the peripheral isolation trench 106 common to the two pixels 100. This makes it possible to reduce the surface area occupied by the pixels of the image sensor.

[0070] In the example shown, the insulating trench 112 is common to the two pixels 100 and surrounds the contact recovery element 120B, located in the center of the arrangement 400, and the two contact recovery elements 120C located on either side of the vertical transfer grid 108. Furthermore, the two pixels 100 of the arrangement 400 comprise, for example, a single conductive pad 120A.

[0071] In the arrangement 400 of [Fig. 4], the transfer grid 108 is common to the two pixels 100 and allows simultaneous blocking and transfer, from the photosensitive areas 102 to the charge collection areas 110 of the pixels 100, of the charges photogenerated in these pixels.

[0072] [Fig.5] is a schematic and partial top view of an arrangement 500 of four adjacent pixels 100 according to one embodiment.

[0073] In the example shown, the four pixels 100 are juxtaposed so that they share portions of the peripheral isolation trench 106. In the orientation of [Fig. 5], the left pixels 100 are symmetrical to the right pixels 100 about a vertical axis, and the top pixels 100 are symmetrical to the bottom pixels 100 about a horizontal axis. The vertical transfer grid 108 is formed in the portions of the peripheral isolation trench 106 common to the four pixels 100 and has, in top view, a cross shape (+). This makes it possible to further reduce the surface area occupied by the pixels of the image sensor.

[0074] In the example shown, the insulating trench 112 is common to the four pixels 100 and surrounds the contact recovery element 120B, located in the center of the arrangement 500, and the four contact recovery elements 120C. Furthermore, the four pixels 100 of the arrangement 500 comprise, for example, a single conductive pad 120A.

[0075] In the arrangement 500 of [Fig. 5], the transfer grid 108 is common to the four pixels 100 and allows simultaneous blocking and transfer, from the photosensitive areas 102 to the charge collection areas 110 of the pixels 100, of the charges photogenerated in these pixels.

[0076] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the embodiment of pixel 200 of Figures 2A and 2B and the embodiment of pixel 300 of Figures 3A and 3B may be combined, so as to obtain a pixel without an insulating trench 112 and in which the electrically conductive region 108C of the vertical transfer gate 108 is separated from the upper face of the substrate 104 by a non-zero thickness of electrically insulating material.

[0077] Furthermore, although the arrangements 400 and 500 have been described above in a case where they comprise pixels 100, similar arrangements may be provided with pixels 200, with pixels 300 or with pixels combining the characteristics of pixels 200 and 300 as indicated above. Such arrangements are within the ability of a person skilled in the art from the indications of the present description.

[0078] Furthermore, although the embodiments described take as an example the case where the photosensitive zone 102, the transfer region 114 and the charge collection zone 110 are N-type doped while the wells 116 and 118 are P-type doped, the person skilled in the art is capable, from the indications of the present description, of transposing these embodiments to the case where the types of doping are inverted, that is to say that the photosensitive area 102, the transfer region 114 and the charge collection area 110 are P-type doped while the wells 116 and 118 are N-type doped.

[0079] Finally, the practical implementation of the described embodiments and variants is within the reach of those skilled in the art from the functional indications given above. In particular, the described embodiments are not limited to the particular examples of materials and dimensions mentioned in the present description.

Claims

Claims

1. An image sensor comprising a plurality of pixels (100; 200; 300) formed in and on a semiconductor substrate (104), each pixel comprising: - a photosensitive area (102) formed in the semiconductor substrate (104); - a peripheral isolation trench (106) extending vertically in the semiconductor substrate (104), from an upper face of the semiconductor substrate, and laterally delimiting the photosensitive area (102); - a charge collection area (110); - a transfer region (114) located in the semiconductor substrate (104) and extending vertically between the charge collection area (110) and the photosensitive area (102);and - a transfer gate (108) extending vertically in the semiconductor substrate (104), from the upper face of the semiconductor substrate and inside the peripheral isolation trench (108), deeper than the charge collection zone (110), in which the transfer region (114) is doped with the same first conductivity type as the photosensitive zone (102) and has a doping level strictly lower than that of the photosensitive zone.;

2. The sensor (100; 200; 300) of claim 1, wherein the transfer gate (108) extends vertically into the semiconductor substrate (104) to a depth substantially equal to that of the transfer region (114).

3. Sensor (100; 200; 300) according to claim 1 or 2, in which the photosensitive area (102) and the transfer region (114) have a substantially horizontal interface.

4. Sensor (100; 200; 300) according to any one of claims 1 to 3, in which the charge collection zone (110) is doped with the first conductivity type and has a doping level strictly higher than that of the transfer region (114).

5. A sensor (100; 200; 300) according to any one of claims 1 to 4, further comprising a well (116) doped with a second conductivity type opposite to the first conductivity type, the well extending vertically in the semiconductor substrate (104), from the upper face of the semiconductor substrate, to a depth lower than that of the transfer grid (108).

6. Sensor (100; 300) according to claim 5, further comprising an electrically insulating trench (112) interposed laterally between the charge collection zone (110) and the box (116).

7. The sensor of claim 6, wherein the electrically insulating trench (112) extends vertically into the semiconductor substrate (104), from the upper face of the semiconductor substrate, to a depth greater than that of the charge collection area (110).

8. The sensor (200) of claim 5, wherein the charge collection area (110) and the box (116) are adjacent.

9. A sensor (100; 200; 300) according to any one of claims 1 to 8, wherein the peripheral isolation trench (106) and the transfer gate (108) respectively comprise first and second electrically conductive regions (106C, 108C), the first electrically conductive region (106C) being electrically isolated from the second electrically conductive region (108C).

10. Sensor (100; 200) according to claim 9, wherein the second electrically conductive region (108C) is flush with the upper face of the semiconductor substrate (104).

11. The sensor (300) of claim 9, wherein the second electrically conductive region (108C) is separated from the upper face of the semiconductor substrate (104) by a non-zero thickness of insulating material.

12. Sensor according to any one of claims 1 to 11, in which the transfer grid (108) is common to two pixels (100; 200; 300).

13. Sensor according to any one of claims 1 to 11, in which the transfer grid (108) is common to four pixels (100; 200; 300).

14. A sensor according to any one of claims 1 to 13, wherein the first conductivity type is N-type.

15. Sensor according to any one of claims 1 to 14, further comprising a control circuit configured to alternately apply, to the transfer grid (108): - a first potential adapted to block a transfer of charges from the photosensitive zone (102) to the charge collection zone (110); and - a second potential, different from the first potential, adapted to allow a transfer of charges from the photosensitive zone (102) to the charge collection zone (110).

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