integrated circuit comprising a memory cell and corresponding manufacturing process

Abstract

The integrated circuit comprises a semiconductor substrate (SUB) and at least one memory cell (CEL) equipped with a vertical-gate selector transistor (TA) embedded in the substrate, and a floating-gate state transistor (TE) (PO1) covering a first active region (ACT1) and a second active region (ACT2) of the substrate, delimited by lateral isolation regions (STIs). The memory cell has a thickness (E) of lateral isolation region (STI) between a flank of the vertical gate (TG) of the embedded transistor and the second active region (ACT2). Figure for the abstract: Fig 1C

Description

Title of the invention: Integrated circuit comprising a memory cell and corresponding manufacturing method

[0001] Embodiments and implementations relate to non-volatile memory integrated circuits, in particular memories capable of implementing programming and erasure with a granularity of one bit.

[0002] Non-volatile memories that can be programmed and erased with a granularity of one bit have been proposed in a technology comprising memory cells equipped with a vertical gate selection transistor buried in a semiconductor substrate and a floating gate state transistor.

[0003] In this type of architecture, there is an interface between the gate of the selector transistor and an active region supporting erasure conditions, aimed, for example, at obtaining a Fowler-Nordheim effect with the floating gate of the state transistor. This is particularly the case in a technique known as "voltage sharing".

[0004] Indeed, in the split voltage technique, potentials of opposite signs are typically generated on either side of the floating gate, for example substantially -8V in the control gate of the state transistor and substantially +8V in the active region, while the gate of the selector transistor is typically at 0V.

[0005] Under such conditions, the interface between the gate of the selection transistor and the active region, which typically includes a gate dielectric layer, is subjected to a voltage of 8V.

[0006] Thus, the interface must on the one hand be able to withstand a stress of 8V at each erasure cycle throughout the entire life of the product.

[0007] On the other hand, a space charge zone can form at the interface between the gate of the selection transistor and the active region, which leads to a loss in erasure efficiency.

[0008] Increasing the thickness of the gate dielectric layer at the interface between the gate of the selection transistor and the active region makes it possible to increase the voltage withstand and limit the loss in efficiency of the erasure operations.

[0009] However, it is advantageous to benefit from a co-integrated manufacturing of capacitive elements (capacitors) simultaneously with the manufacturing of the buried vertical grids.

[0010] However, increasing the thickness of the gate dielectric layer of the selection transistor, in the case of cointegration, leads to an increase in the thickness of the dielectric layer of the capacitive interface and therefore a degradation of the performance of the capacitor (lower capacitive value).

[0011] Providing a dissociation of the two dielectric layers in vertical grid structures, in order to obtain two different thicknesses, leads to an increase in manufacturing cost and a loss of the advantage of cointegration.

[0012] Thus, there is a need to remedy the aforementioned disadvantages, namely a need to increase the voltage resistance of the buried vertical grid and to improve the efficiency of the memory cell erasure operations, without causing a loss in performance of a possible cointegrated capacitive element, or an increase in production costs.

[0013] Embodiments and implementations defined below propose an embodiment of memory cell in which the thickness of the dielectric interface between the vertical grid and the active region is increased, without increasing the thickness of the grid dielectric of the dielectric interface of the cointegrated capacitive element, and without harming the cointegration or generating additional cost.

[0014] Thus, according to one aspect, an integrated circuit is proposed comprising a semiconductor substrate and at least one memory cell equipped with a vertical gate selector transistor buried in the substrate, and a floating gate state transistor covering a first active region and a second active region of the substrate delimited by lateral isolation regions; in which the memory cell has a lateral isolation region thickness between a flank of the vertical gate of the buried transistor and the second active region.

[0015] For example, the lateral isolation regions are of the shallow trench isolation type (usually "Shallow Trench Isolation" in English).

[0016] This aspect offers a free solution and is compatible with almost all manufacturing processes since almost all technologies provide for lateral isolation regions.

[0017] According to one embodiment, the vertical gate of the selection transistor has a dielectric envelope on the sides and bottom of a trench in the substrate filled by a conductive region, said thickness of lateral insulation region between the side of the vertical gate and the second active region being at least 5 times greater than the thickness of the dielectric envelope.

[0018] According to one embodiment, the integrated circuit further comprises a capacitive element with a vertical conductive electrode buried in the substrate having the same structure and composition as the vertical gate of the selection transistor.

[0019] According to one embodiment, the second active region comprises a dopant implantation of the opposite type to that of the substrate, occupying a volume located under the floating gate of the state transistor.

[0020] It should be noted that the presence of the thickness of the lateral insulation region between the the side of the vertical grid of the buried transistor and the second active region offers in addition to the advantages mentioned above, additional robustness in the alignment of the layout in the second active region.

[0021] According to one embodiment, the integrated circuit further comprises writing means configured to generate programming and erasure conditions, respectively adapted to generate charge transfers of a first sign between the floating gate and the first active region, and charge transfers of a second sign between the floating gate and the second active region.

[0022] According to another aspect, a method for manufacturing at least one memory cell of an integrated circuit comprising is also proposed: - the formation of lateral isolation regions in a semiconductor substrate, delimiting a first active region and a second active region; - a vertical gate selector transistor formation embedded in the substrate, positioned such that a lateral isolation region thickness lies between one flank of the vertical gate and the second active region; and - a formation of a floating gate state transistor covering the first active region and the second active region.

[0023] According to one embodiment, the formation of the vertical gate of the selection transistor comprises etching a trench in the substrate, forming a dielectric envelope on the sides and bottom of the trench and forming a conductive region filling the rest of the trench, the etching of the trench being positioned vis-à-vis the lateral insulation region so as to maintain after etching said thickness of lateral insulation region between the side of the vertical gate and the second active region, at least 5 times greater than the thickness of the dielectric envelope.

[0024] According to one embodiment, the formation of the vertical gate of the selection transistor is carried out jointly with the formation of a vertical conducting electrode embedded in the substrate of a capacitive element. Consequently, the electrode has, in particular, the same structure and composition as the vertical gate of the selection transistor.

[0025] According to one embodiment, the process further comprises an implantation, in the second active region, of dopants of a type opposite to that of the substrate occupying a volume located under the future floating grid.

[0026] According to one embodiment, the method further comprises training writing means configured to generate programming and erasure conditions, respectively adapted to generate first-sign charge transfers between the floating grid and the first active region, and second-sign charge transfers between the floating grid and the second active region.

[0027] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and implementations, which are by no means limiting, and the accompanying drawings, in which the figures:

[0028] [Fig.lA] ;

[0029] [Fig.lB] ;

[0030] [Fig.lC] ;

[0031] [Fig.2A] ;

[0032] [Fig.2B] ;

[0033] [Fig.3];

[0034] [Fig.4];

[0035] [Fig.5];

[0036] [Fig.6];

[0037] [Fig.7];

[0038] [Fig.8];

[0039] [Fig.9] illustrate embodiments and implementations of the invention.

[0040] Figures IA, IB and IC illustrate a first example of a memory cell CEL, made in and on a SUB semiconductor substrate of an integrated circuit.

[0041] Fig. 1A illustrates a top view of the CEL cell, the elements of which are represented by transparency.

[0042] [Fig.1B] illustrates a cross-sectional view of cell CEL, in plane AA' of [Fig.1A],

[0043] [Fig.1C] illustrates a cross-sectional view of cell CEL, in plane BB' of [Fig.1A],

[0044] The CEL cell is equipped with a vertical gate selection transistor TA buried in the substrate, and a state transistor TE. The state transistor TE has a floating gate PO1 capable of storing charges in a non-volatile manner, and a control gate PO2 capable of receiving control potentials.

[0045] The vertical grid structure TG buried in the substrate comprises a dielectric envelope GO on the sides and bottom of a trench in the substrate SUB, the remainder of the volume of the trench being filled by a gate-conducting region PO, for example in polycrystalline silicon.

[0046] The stacked structure of the floating gates PO1 and control gates PO2 of the state transistor TE covers a first active region ACT1 and a second active region ACT2 of the substrate, delimited by lateral isolation regions STI, typically shallow isolation trenches.

[0047] In the first active region ACT1, the state transistor TE and the selection transistor TA are coupled in series, from a drain region D of the state transistor, typically accessible via a bitline, and the contact CNT1, an S / D conduction region (serving as the source of the state transistor TE and the drain of the selector transistor TA), to a source region of the selector transistor TA located in a NISO box embedded deep within the SUB substrate.

[0048] The second active region ACT2 includes a CAPIMP dopant implantation of the opposite type to that of the substrate, occupying a volume located under the floating gate of the state transistor TE.

[0049] The implanted CAPIMP region is located on the surface of the SUB substrate, and extends deeper than the implanted drain D and conduction S / D regions, but less deeply than the lateral isolation STI regions.

[0050] A CNT2 contact allows the CAPIMP implanted region to be electrically connected to the second active region ACT2.

[0051] The cutting plane AA' crosses longitudinally through the first active region ACT1, while the cutting plane BB' crosses longitudinally through the second active region ACT2.

[0052] In the first example of a CEL memory cell, the first active region ACT1 and the second active region ACT2 extend parallel in length in a first direction, and are crossed by the stack of gates of the state transistor TE and by the buried vertical gate TG which extend parallel in a second direction perpendicular to the first direction.

[0053] The first active region ACT1 is intended to implement programming-type write operations and reads of the data contained in the memory cell CEL, while the second active region ACT2 is intended to implement data erasure-type write operations.

[0054] Reference is made to ECR writing operations in [Fig.9].

[0055] Figure 9 is a table of values ​​illustrating an example of voltage conditions on the control gate CG (PO2), on the drain D / CAPIMP (also biasing the implanted CAPIMP region in the second active region ACT2), on the vertical gate of the selection transistor TG and on the source plane NISO, enabling the implementation of PROG programming and EFF erasure operations in the memory cell CEL.

[0056] The different writing tensions can be generated and distributed by conventional writing means, which will not be detailed here.

[0057] The PROG programming conditions include a control gate bias at +10V, the drain D at +4.5V, the implanted region CAPIMP in the second active region ACT2 at 0V, the vertical gate at a voltage Vt sufficient to generate a conduction channel, for example IV, and the source plane S at 0V.

[0058] These PROG programming conditions allow a channel region to be formed conduction, from drain D to source plane NISO, and to generate an impact ionization phenomenon on the source side S / D of the state transistor TE, in order to generate an injection of hot (negative sign) carriers into the floating gate from the source side channel S / D.

[0059] The EFF erasure conditions, of the split voltage type, include a control gate bias at -8V, drain D at 0V, and the CAPIMP implanted region in the second active region ACT2 at +8V, the vertical gate at a blocking voltage of 0V and the source plane S at 0V.

[0060] These EFF removal conditions allow for the generation of a charge transfer (of negative sign) by Fowler-Nordheim effect from the floating grid PO1 to the second active region ACT2 via the implanted region CAPIMP.

[0061] The EFF erasure conditions can also allow the generation of a positive charge transfer (for example by Fowler-Nordheim effect as well) in the floating grid PO1, via the implemented region CAPIMP.

[0062] These writing conditions, and in particular EFF erasure, offer good performance, a granularity of one bit, and little disturbance in neighboring cells (usually "disturb" in English).

[0063] Furthermore, and referring again to figures IA, IB and IC, advantageously with respect to the writing conditions described above, a thickness E of lateral isolation region STI between a flank of the vertical gate TG of the buried transistor and the second active region ACT2 is retained after the etching of the trench TG in the memory cell CEL.

[0064] Indeed, this makes it possible on the one hand to protect against stress on the GO gate dielectric of the TA selection transistor subjected to a voltage of 8V during erasure operations.

[0065] And on the other hand, this also makes it possible to avoid the formation of an inversion zone (also called a space charge zone) along the buried vertical grid at the interface with the second active region ACT2 during the clearing operations, which causes a loss of clearing efficiency.

[0066] To a rough order of magnitude, the thickness E of the lateral insulation region STI between the side of the vertical grid and the second active region ACT2 is at least 5 times greater than the thickness of the dielectric envelope GO. Indeed, depending on the manufacturing limitations (or node) of the technology (usually referred to as the "technological node" in English), said thickness E can be on the order of 5 to 25 times greater than the thickness of the dielectric envelope GO.

[0067] For example, the conserved thickness E of STI can have a size between 0.03 pm and 0.25 pm, for example 0.08 pm, while the gate dielectric layer can have a size of a few nanometers, for example from 3 nm to 10 nm.

[0068] Figures 2A and 2B illustrate a second example of the CEL memory cell, which differs from the first from an architectural point of view (i.e. in the arrangement of the elements made), and not from a functional point of view.

[0069] Fig. 2A illustrates a top view of the CEL cell, the elements of which are represented by transparency.

[0070] Fig. 2B illustrates a cross-sectional view of cell CEL, in plane CC' of Fig. 2A.

[0071] The second example of the CEL memory cell is an architectural alternative to the first example of the CEL memory cell, where only the arrangement of the elements of the memory cell has changed.

[0072] In the second example of the CEL memory cell, the first active region ACT1 and the second active region ACT2 are aligned lengthwise in the first direction, on either side of the vertical grid TG which extends in the second direction perpendicular to the first.

[0073] The grid stack of the state transistor TE covers the vertical gate as well as the first active region ACT1 and the second active region ACT2 on each side of the selection transistor TA in the first direction.

[0074] The cutting plane CC' crosses longitudinally the first active region ACT1, crosses laterally the vertical grid TG, and crosses longitudinally the second active region ACT2.

[0075] The elements of the CEL memory cell in both examples are the same and support the same references. The description given previously with regard to Figures IA, IB and IC applies to the CEL memory cell in Figures 2A and 2B except for the arrangement described above.

[0076] Figures 3 to 8 illustrate steps in a manufacturing process for the CEL memory cell, advantageously with a cointegrated manufacturing of a TCAP capacitive element.

[0077] The cross-sectional views in the AA' and BB' planes corresponding to the planes of figures IB and IC are shown for the manufacture of the CEL memory cell in the arrangement of the first example, and also a corresponding cross-sectional view for the TCAP capacitive element.

[0078] Fig. 3 illustrates a step 300 in which the NISO region has been implanted deep into the SUB substrate in the region of the substrate hosting the CEL memory cell.

[0079] The SUB substrate is, for example, conventionally P-type doped silicon, the deep-implanted layer NISO being N-type doped.

[0080] Figure 4 illustrates a step 400 in which the lateral insulation regions STI are formed, for example according to the shallow insulation trench technique in in which a shallow trench is opened in the substrate which is filled with a dielectric volume such as silicon oxide.

[0081] The lateral isolation regions STI allow the active regions ACT1, ACT2, ACT3 to be defined between them, at the level of the substrate surface SUB.

[0082] It will be noted in particular that a lateral isolation region STI crossing the cutting plane BB' of the memory cell is provided at this step 400.

[0083] Fig. 5 illustrates a 500 implantation step, in the second active region ACT2, of dopants of a type opposite to that of the substrate SUB (i.e. an implantation of N-type dopants) occupying the entire extent of the second active region ACT2 on the surface, down to a depth less than, but of comparable size, the depth of the lateral isolation regions STI.

[0084] The presence of the lateral isolation region STI in the BB' plane of the second active region ACT2 provides additional robustness in the alignment of the CAPIMP implantation.

[0085] Fig. 6 illustrates a step 600 of etching the TR trenches which will accommodate the vertical gate structure of the TA selection transistor of the CEL memory cell and the vertical electrode structure of the TCAP capacitive element.

[0086] In the BB' plane, the 600 engraving of the TR trench is positioned opposite the lateral isolation region STI so as to maintain after the 600 engraving a thickness E of the lateral isolation region STI between the side of the future vertical grid and the second active region ACT2.

[0087] The thickness E can be parameterized so as to be at least 5 times greater than the thickness of the dielectric layer of the GO gate formed in the next step 700.

[0088] The thickness E of the remaining lateral insulation region can be approximately 0.08 pm, for example between 0.03 pm and 0.25 pm.

[0089] Fig. 7 illustrates a step 700 in which a dielectric envelope GO is formed on the sides and bottom of the trench TR and a conductive region PO0 is formed filling the rest of the trench TR.

[0090] The GO dielectric envelope, for example made of silicon oxide, has a dielectric thickness of the logic transistor gate type, typically less than 10 nm, for example from 3 to 10 nm.

[0091] This order of magnitude of the thickness of the dielectric envelope GO advantageously allows for a high capacitive value in the realization of the TCAP capacitor.

[0092] Indeed, the capacitive interface of the TCAP capacitor is located between the trench-filling conductive region PO0 and the active region ACT3 of the substrate, i.e. the dielectric layer GO.

[0093] The conductive region PO0 is, for example, formed by an excess filling of polycrystalline silicon then a chemo-mechanical flattening until the front face of the SUB substrate is exposed.

[0094] Thus, in the first active region ACT1 of the memory cell and in the third active region ACT3 hosting the TCAP capacitor, the thickness of the dielectric interface between the gate conductive region PO0 and the substrate SUB is the thickness of the gate dielectric GO.

[0095] This is particularly advantageous for the control of the TA selection transistor in the first active region ACT1, and the capacitive value of the capacitive element TCAP.

[0096] In the second active region ACT2 of the CEL memory cell, the thickness of the dielectric interface between the gate conductive region PO0 and the substrate SUB comprises the sum of the gate dielectric layer GO and the remaining thickness E of the lateral insulation region STI, from the front face of the substrate to a depth beyond the depth of the implanted region CAPIMP (it is recalled that the implanted region CAPIMP will support the erasure voltage of 8V).

[0097] The remainder of the dielectric interface between the gate conductive region PO0 and the substrate SUB, i.e. between the bottom of the lateral insulation region STI and the deep-embedded box NISO, has the thickness of the gate dielectric layer GO (under erasure conditions, the substrate SUB opposite this thickness GO is at a substantially zero potential).

[0098] Fig. 8 illustrates a conventional 800 formation of the stacking of the floating grid PO1 and the control grid PO2 in the part housing the memory cell CEL.

[0099] In summary, a memory cell has been formed in which the thickness of the dielectric interface between the vertical gate and the second active region is increased, without increasing the thickness of the gate dielectric of the dielectric interface of the cointegrated capacitive element, and without generating a dedicated step or additional cost.

[0100] The thicker dielectric interface allows better insulation between the implanted CAPIMP region in the second active region ACT2, and the vertical gate of the TA selection transistor.

[0101] The better insulation between the second active region ACT2 (CAPIMP) and the vertical gate of the TA selection transistor allows for better erasure efficiency, due to the absence of the space charge zone between the implanted CAPIMP region and the dielectric interface; and also a potentially longer lifetime due to better reliability of the dielectric thickness at the erasure zone.

[0102] Furthermore, the possibility of co-integrating the two different dielectric interface thicknesses makes it possible, on the one hand, not to increase the manufacturing cost in terms of additional steps and masks; and, at the same time, not to degrade the capacitive value of the capacitor, so that the costs due to the surface area of ​​the capacitor do not increase either.

Claims

Claims

1. Integrated circuit comprising a semiconductor substrate (SUB) and at least one memory cell (CEL) provided with a selection transistor (TA) with a vertical gate (TG) buried in the substrate, and a state transistor (TE) with a floating gate (PO1) covering a first active region (ACT1) and a second active region (ACT2) of the substrate delimited by lateral isolation regions (STI); in which the memory cell comprises a thickness (E) of lateral isolation region (STI) between a flank of the vertical gate (TG) of the buried transistor and the second active region (ACT2).

2. Integrated circuit according to claim 1, in which the vertical gate (TG) of the selection transistor comprises a dielectric envelope (GO) on the sides and the bottom of a trench in the substrate filled by a conductive region (PO), said thickness (E) of lateral insulation region (STI) between the side of the vertical gate and the second active region (ACT2) being at least 5 times greater than the thickness of the dielectric envelope (GO).

3. Integrated circuit according to one of claims 1 or 2, further comprising a capacitive element (TCAP) provided with a vertical conductive electrode (POO) buried in the substrate having the same structure and the same composition as the vertical gate (TG; POO) of the selection transistor (TA).

4. Integrated circuit according to one of claims 1 to 3, in which the second active region (ACT2) comprises a dopant implantation (CAPIMP) of the opposite type to that of the substrate, occupying a volume located under the floating gate of the state transistor (TE).

5. Integrated circuit according to one of claims 1 to 4, further comprising writing means (ECR) configured to generate programming (PROG) and erasing (EFF) conditions, respectively adapted to generate charge transfers of a first sign between the floating gate (PO1) and the first active region (ACT1), and charge transfers of a second sign between the floating gate (PO1) and the second active region (ACT2).

6. Method for manufacturing at least one memory cell (CEL) of an integrated circuit comprising: - a formation (400) of lateral isolation regions (STI) in a semiconductor substrate (SUB), delimiting a first active region (ACT1) and a second active region (ACT2); - a formation (600-700) of a vertical gate selection transistor (TA) buried in the substrate (SUB), positioned so that a thickness (E) of lateral isolation region (STI) is located between a flank of the vertical gate (PO0) and the second active region (ACT2); and - a formation (800) of a floating gate state transistor (TE) (PO1) covering the first active region (ACT1) and the second active region (ACT2).

7. Method according to claim 6, in which the formation (600-700) of the vertical gate (TG) of the selection transistor comprises an etching (600) of a trench (TR) in the substrate, a formation (700) of a dielectric envelope (GO) on the sides and the bottom of the trench (TR) and a formation of a conductive region (PO0) filling the remainder of the trench (TR), the etching of the trench (600) being positioned opposite the lateral isolation region (STI) so as to maintain after the etching said thickness (E) of lateral isolation region between the side of the vertical gate (PO0) and the second active region (ACT2), at least 5 times greater than the thickness of the dielectric envelope (GO).

8. Method according to one of claims 6 or 7, in which the formation (600-700) of the vertical gate of the selection transistor is done in conjunction with a formation (600-700) of a vertical conductive electrode buried in the substrate of a capacitive element (TCAP).

9. Method according to one of claims 6 to 8, further comprising an implantation (500), in the second active region (ACT2), of dopants of the opposite type to that of the substrate (SUB) occupying a volume located under the future floating gate (PO1).

10. Method according to one of claims 6 to 9, further comprising a formation of writing means (ECR) configured to generate programming (PROG) and erasure (EFF) conditions, respectively adapted to generate charge transfers of a first sign between the floating gate (PO1) and the first active region (ACT1), and charge transfers of a second sign between the floating gate (PO1) and the second active region (ACT2).

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