METHOD FOR MANUFACTURING A QUANTUM ELECTRONIC CIRCUIT WITH A REDUCED GATE PITCH

Abstract

METHOD FOR MANUFACTURING A QUANTUM ELECTRONIC CIRCUIT WITH A REDUCED GATE PITCH One aspect of the invention relates to a method for manufacturing an electronic circuit (1) comprising the steps of: forming first electrodes (51) distributed according to a constant pitch R; forming spacers against the first electrodes (51); forming, between two adjacent spacers, a second electrode (52); and replacing each spacer with a third electrode (53). The first, second, and third electrodes (51, 52, 53) are thus distributed according to an average pitch equal to R / 4. Figure to be published with the abbreviation: Figure 3

Description

Title of the invention: METHOD FOR MANUFACTURING A QUANTUM ELECTRONIC CIRCUIT WITH A REDUCED GATE PITCH TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of quantum electronics and more particularly the manufacture of such a circuit. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] The manipulation of quantum states, also called "qubits" for "quantum bits" in English, offers new possibilities in the manipulation of information. There are several types of qubits, such as spin qubits for which the information is stored in the quantum state of a spin. Quantum electronic circuits capable of allowing the manipulation of spin qubits include islands, also called quantum dots, capable of storing qubits while they are being manipulated and measured.

[0003] [Fig.l] represents a simplified example of an AAI electronic circuit architecture as commonly implemented. According to this architecture, the quantum dots AA21 are formed in a semiconductor layer AA 11 called the qubit layer. The boxes AA21 correspond to wells formed in the electrostatic potential AA20 of the qubit layer AA11 by means of conductive electrodes AA 13, called “gate electrodes” or “gates”. The gates AA13 are arranged on the qubit layer AAI 1 and electrically insulated from the latter by a dielectric layer AA 12, called “gate oxide” because it is frequently formed by an oxide. Modulating the electrical potential of the gates AA 13 makes it possible to modulate the shape of the quantum dots AA21. When each box AA21 comprises a qubit A2, these modulations make it possible to manipulate the qubits AA2.

[0004] The integration of AA21 quantum dots in the form of an electronic circuit must satisfy several requirements. On the one hand, it must offer a high integration density in order to provide a substantial computing capacity. On the other hand, the manufacturing processes of said quantum electronic circuits must ensure low variability of the circuits. Indeed, the efficiency of storage and manipulation of AA2 qubits is highly dependent on the position of the qubits within the AA21 quantum dots. However, the latter can be influenced by their environment.

[0005] [Fig.2] considers the circuit of [Fig.l] in which a distribution of electric charges AA 14 is dispersed in the qubit layer AAI 1 and / or the dielectric layer AA 12. These electric charges AA 14 correspond for example to dilute dopants or vacancies within these AA11, AA12 layers. This AA14 charge distribution modifies the AA20 electrostatic potential at the AAI 1 qubit layer and distorts the AA21 quantum dots. Parasitic AA21' potential wells can be formed, trapping the AA2 qubits. The location of the AA2 qubits thus becomes erratic instead of being directly above the AA13 gates. Manipulation of the AA2 qubits is made more difficult.

[0006] In order to reduce the impact of the AA14 electric charges on the localization of the qubits 2, it is known to reduce the spacing between the neighboring AA13 gates. Reducing the spacing between these AA13 gates amounts to reducing the distribution interval between these AA 13 gates, called pitch. A gate pitch of less than 80 nm, and preferably less than 25 nm, makes it possible to effectively counter the impact of the distribution of AA14 electric charges on the AA21 boxes. However, manufacturing an electronic circuit with a greatly reduced gate pitch raises new problems.

[0007] The manufacture of AA 13 grids having a pitch lower than 25 nm requires, for example, the implementation of lithography steps in the extreme ultraviolet, known as "extreme ultraviolet" in English or "EUV". This type of lithography requires expensive and complex installations. In addition, it can give rise to a drift phenomenon when several EUV lithography steps follow one another (known as "pitch walking" in English).

[0008] A low grid pitch also complicates the alignment of electrical contacts on each grid. Misalignment or overhanging of contacts can short-circuit multiple grids together, rendering the circuit unusable.

[0009] Document US 2019 / 0140073 A1 describes a method for manufacturing a quantum device from a substrate on which first gates extend. These first gates are distributed parallel to each other and according to an initial gate pitch. Second gates are formed between the first gates. The first and second gates are thus distributed with a reduced pitch, equal to half the initial gate pitch. This method thus makes it possible to reduce the final gate pitch of the quantum circuit. However, unless EUV lithography steps are implemented, it does not make it possible to achieve a final pitch that is sufficiently low to improve the localization of the qubits. Summary of the invention

[0010] There is therefore a need to provide an electronic circuit making it possible to form quantum dots of reduced width, for example less than 80 nm, and not requiring the implementation of EUV lithography steps for its manufacture.

[0011] The invention provides a method of manufacturing an electronic circuit allowing to achieve a final gate pitch divided by four compared to an initial gate pitch, for example equal to the minimum pitch accessible with DUV (Deep UV) type lithography equipment. It is thus possible to achieve a final gate pitch of less than 80 nm, or even less than 25 nm, with DUV equipment that typically allows a gate pitch of 100 nm to be obtained.

[0012] For this, the invention relates to a method of manufacturing an electronic circuit from a substrate, comprising the steps of: • forming, on the substrate, first gate electrodes spaced apart from each other, each first gate electrode having a first branch extending parallel to a first direction, the first branches of the first gate electrodes being distributed according to a constant pitch R, measured according to a second direction perpendicular to the first direction; • form spacers, against the first grid electrodes; • forming, on the substrate, second gate electrodes, each second gate electrode being arranged between two neighboring first gate electrodes and separated from each of them by one of the spacers, each second gate electrode having a first branch extending between the two first branches of the neighboring first gate electrodes; and • forming, in replacement of the spacers, third gate electrodes, each third gate electrode being arranged between a first gate electrode and a second neighboring gate electrode, each third gate electrode having a first branch extending between a first branch of a first gate electrode and a first branch of a second gate electrode.

[0013] By "gate electrode" is meant a conductive track or a conductive electrode intended to apply an electrical potential to a semiconductor layer.

[0014] By "branch" is meant a substantially straight portion of a gate electrode.

[0015] By "neighbors" is meant two nearest neighbors. For example, two first neighboring gate electrodes are distant from each other, adjacent in the second direction and nearest neighbors.

[0016] By “constant pitch” we mean that the pitch is constant to within 10%, or even 5%.

[0017] By "perpendicular" and "perpendicularly" is meant perpendicular at 20° close or even 10° close. Similarly, by "parallel" and "parallelly" we mean parallel to within 20° or even 10° close.

[0018] By "forming against a gate electrode" is meant forming against opposite sides of said gate electrode.

[0019] By "opposite sides" is meant two portions of a flank, the flank being a surface extending perpendicular to the substrate and delimiting an object, such as a gate electrode.

[0020] By “spacer” is meant an electrically insulating track.

[0021] By "against" or "extending against" is meant that an object is in direct contact, without intermediary.

[0022] The above method makes it possible to form first electrodes with a predefined pitch, for example at the resolution limit achievable by DUV lithography equipment. Inserting the second gate electrodes between each pair of first gate electrodes makes it possible to obtain first and second gate electrodes distributed, in the second direction, according to an average pitch of R / 2. Inserting the third electrodes, in place of the spacers, between each pair of consecutive first and second gate electrodes, makes it possible to obtain first, second and third gate electrodes distributed according to an average final pitch divided by 4 compared to the initial pitch. For an initial pitch of 100 nm, the average final pitch is approximately 25 nm. This pitch makes it possible to form narrow quantum dots in the active area which are little, if at all, influenced by the charges distributed in the substrate or the active area.

[0023] By "average pitch" is meant the average of the distances separating two neighboring electrodes, measured in the second direction, and for each pair of neighboring electrodes (independently of the concept of first, second or third electrode).

[0024] Advantageously, the replacement of the spacers by the third gate electrodes comprises a selective etching of the spacers relative to the first and second gate electrodes.

[0025] Advantageously, the first gate electrodes are formed from a first sacrificial material, such as polycrystalline silicon; the second gate electrodes are formed from a second conductive material, such as titanium nitride; and the method comprises a step of replacing the first sacrificial material of the first gate electrodes with the second conductive material.

[0026] Advantageously, the first gate electrodes are formed from a first sacrificial material; the second gate electrodes are formed from a second sacrificial material; and the third gate electrodes are formed from a third conductive material; and the method comprises a step of replacing the first and second sacrificial materials of the first and second gate electrodes with the third conductive material.

[0027] Advantageously, each first gate electrode is formed so that the first branch has a first width, measured in the second direction, less than or equal to R / 4; and the spacers are formed so as to have a second width, measured in the second direction and at the level of the first branches of the first grid electrodes, less than or equal to R / 4.

[0028] Advantageously, each third gate electrode is formed so as to extend between first and second neighboring gate electrodes and so as to have at least one portion, called a “free portion”, extending beyond said first and second neighboring gate electrodes.

[0029] Advantageously, the method comprises, after the formation of the spacers and before the formation of the third gate electrodes, a partial etching of each first gate electrode from one end, the etching being carried out selectively with respect to the spacers so that each spacer has a free portion extending beyond the first gate electrodes, the formation of the second gate electrodes being carried out so that said spacer portions also extend beyond the second gate electrodes and so that during the formation of the third gate electrodes, each third gate electrode has, after replacement of each spacer, a free portion extending beyond the first and second gate electrodes.

[0030] Advantageously, the method comprises, after the formation of the third gate electrodes, a step of reestablishing contact on each free portion of the third gate electrodes extending beyond the first and second gate electrodes.

[0031] Advantageously, the formation of the first gate electrodes is carried out so that each of the first, second and third gate electrodes also comprises a second branch extending perpendicular to its first branch.

[0032] In other words, the first and second branches of the same first electrode are produced simultaneously, for example by etching or deposition through the same mask. Thus, the second and third gate electrodes which are inserted between the first gate electrodes may also have a second portion extending in the second direction. The second portions may, by their orientation perpendicular to the first portions (extending in the first direction), be freely distributed in the first direction without impact on the distribution in the second direction. Therefore, these second portions may be distributed in a relatively spaced manner to provide easy contact recovery, reducing the risk of short-circuiting with the third electrodes, without impacting the final pitch at the level of the active zone.

[0033] For example, the formation of the second branches of the first and second gate electrodes is carried out such that, for each of the first and second gate electrodes, a width of the second branch, measured along the first direction, is strictly greater than a width of the first branch.

[0034] Advantageously, the method comprises a contact resumption on the second branch of each first gate electrode and of each second gate electrode.

[0035] According to a development, the second branches of the first grid electrodes are distributed according to a constant pitch, measured in the first direction, strictly greater than 2 x R.

[0036] Advantageously, the method comprises, before the formation of each second gate electrode and / or each third gate electrode, the deposition of a dielectric layer, called “gate oxide”, on the substrate between two neighboring first gate electrodes, the formation of each second gate electrode and / or each third gate electrode being carried out on the gate oxide.

[0037] By heel is meant a dielectric layer having a substantially constant thickness.

[0038] The invention also relates to an electronic circuit comprising, on a substrate: • first gate electrodes spaced apart from each other, each first gate electrode having a first branch extending parallel to a first direction, the first branches of the first gate electrodes being distributed according to a constant pitch R, measured according to a second direction perpendicular to the first direction; • of the second grid electrodes, each second grid electrode being disposed between two adjacent first grid electrodes, each second grid electrode having a first branch extending between the two first branches of the adjacent first grid electrodes, the electronic circuit being remarkable in that it comprises third grid electrodes, each third grid electrode being disposed between an adjacent first grid electrode and a second grid electrode, each third grid electrode having a first branch extending between a first branch of a first grid electrode and a first branch of a second grid electrode, and in that the first, second and third grid electrodes are distributed with an average pitch, measured along the second direction, equal to R / 4.

[0039] Advantageously, the first, second and third gate electrodes extend at least partly over a portion of the substrate, called the “active zone”, configured to accommodate quantum dots.

[0040] Advantageously, the first gate electrodes comprise a first conductive material and the second gate electrodes comprise a second conductive material, identical to the first conductive material.

[0041] Advantageously, the third grid electrodes comprise a third conductive material, identical to the materials of the first and second grid electrodes.

[0042] Advantageously, every third grid electrode has a portion, called the "free portion", extending beyond the first and second grid electrodes, the circuit including electrical contacts, each electrical contact being connected to a free portion of a third grid electrode extending beyond the first and second grid electrodes.

[0043] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0044] The figures are presented by way of indication and in no way limit the invention. Unless otherwise specified, the same element appearing in different figures has a single reference.

[0045] The [Fig.l], [Fig.2] show circuits according to the prior art.

[0046] [Fig.3], [Fig.4] and [Fig.5] show a first embodiment of a circuit electronics according to the invention.

[0047] [Fig.6] shows a second embodiment of an electronic circuit according to the invention.

[0048] [Fig.7] shows a third embodiment of an electronic circuit according to the invention.

[0049] [Fig.8], [Fig.9], [Fig.10], [Fig.1 1], [Fig.12], [Fig.13], [Fig.14], [Fig.15], [Fig.16], [Fig.17], [Fig.18], [Fig.19], [Fig.20], [Fig.21] show intermediate devices that can be obtained during different steps or sub-steps of a manufacturing method according to the invention. DETAILED DESCRIPTION

[0050] Figures 3 and 4 schematically present a first embodiment of an electronic circuit 1 according to the invention. [Fig.3] presents a perspective while [Fig.4] presents a top view of the circuit 1.

[0051] The electronic circuit 1 comprises a substrate 4 extending in a plane {X; Y}. The substrate 4 comprises a portion 2 called the “active zone”. The active zone 2 is intended to accommodate quantum dots and qubits within it. It has a raised shape relative to the substrate 4, also called a “mesa”. The circuit 1 also comprises a network of conductive electrodes 51, 52, 53 called gate electrodes, extending, among other things, over the active zone 2. The gate electrodes 51, 52, 53 are arranged to allow the application of an electrical potential to the active zone 2 so as to be able to modulate the electrostatic field in the active zone 2 and form quantum dots therein.

[0052] Circuit 1 makes it possible to form quantum dots distributed in a single direction (in this case the Y direction). Indeed, the active zone 2 has a parallelepiped shape with a very high aspect ratio. In particular, it has a thickness, measured in a Z direction, which is very low, from 5 nm to 30 nm. It also has, in this embodiment, a width W2, measured in a first direction X, between 10 nm and 100 nm. On the other hand, it has a length L2, measured in a second direction Y, greater than 100 nm and which can reach several micrometers. This length L2 depends, among other things, on the number of quantum dots targeted, the dimension and the distribution of the gate electrodes 51, 52, 53. In this way, the quantum dots formed in the active zone 2 are constrained in width (along X) and in thickness (along Z). On the other hand, they are distributed according to the length of the active zone 2 (along Y).

[0053] The gate electrodes 51, 52, 53 extend above the active zone 2, in the X direction, overlapping the latter. In this way, the electrodes 51, 52, 53 make it possible to modulate the electrostatic field of the active zone 2 in the Y direction, to form the set of quantum dots distributed in the Y direction.

[0054] The active zone 2 comprises a thin semiconductor layer 21, intended to receive the quantum dots. This thin layer 21 can be called a qubit layer. In the embodiment of FIGS. 3 and 4, the qubit layer 21 of the active zone 2 corresponds to an extension of a thick semiconductor layer 41 of larger dimension of the substrate 4. This arrangement can be obtained by etching the thick layer 41 of the substrate 4 through a mask so as to retain only the mesa forming the active zone 2. Alternatively, the qubit layer 21 can be cut out in the thick layer 41 by a trench made in the thick layer 41 of the substrate 4.

[0055] The active zone 2 also comprises an insulating layer 22 extending over the qubits layer 21. This insulating layer 22 extends between the qubits layer 21 and the conductive electrodes 51, 52, 53, thus forming a layer called “gate oxide”. The gate oxide 22 may be formed by oxidation of the surface of the qubits layer 21 or by deposition of a dielectric on this layer 21. Alternatively, the gate oxide may be of a nature other than an oxide; however, by misuse of language, we will still call it “gate oxide”. The gate oxide 22 may have a thickness, measured along Z, of between 1 nm and 20 nm.

[0056] In this embodiment, the gate electrodes 51, 52, 53 have a particular L-shape. They thus form two straight branches 51a, 52a, 53a, 51b, 52b, 53b that are consecutive and perpendicular to each other. A first straight branch 51a, 52a, 53a extends over the active zone 2, in the X direction. A second straight branch 51b, 52b, 53b extends at a distance from the active zone 2, in the Y direction. electrodes 51, 52, 53 are arranged side by side and resting on each other, separated only by an insulating layer (discussed below, with reference to figures 5 and 6). The first branches 51a, 52a, 53a extending over the active zone 2 make it possible to apply an electrostatic field at the level of the active zone 2 and form quantum dots in the qubit layer 21. The second branches 51b, 52b, 53b, extending at a distance from the active zone 2 make it possible to connect these electrodes 51, 52, 53.

[0057] In this case, each electrode 51, 52, 53 is connected to an electrical contact 9. The contacts 9 are, for example, conductive vias extending perpendicularly to the substrate 4. These contacts 9 are usually connected to the electrodes 51, 52, 53 during a so-called “contact recovery” step. For example, a well is formed vertically above each electrode 51, 52, 53 and a contact 9 is formed in said well, in direct contact with one of the electrodes 51, 52, 53.

[0058] Contacts 9 are also connected to the active zone 2.

[0059] Contact recovery can be critical, partly due to well alignment relative to the electrodes 51, 52, 53. A slight misalignment or poor control of the diameter of the well can cause a contact 9 to overlap on two neighboring electrodes 51, 52, 53. This contact resumption step is also made more delicate when the pitch between electrodes is small, as is the case in the invention.

[0060] To overcome this problem, the resumption of contact on the first and second electrodes 51, 52 is carried out on the second straight branches 51b, 52b of these electrodes 51, 52. Indeed, the second straight branches 51b, 52b, of the first and second electrodes 51, 52, oriented in the second direction Y. They can be widened and / or separated without involvement in the first direction X, that is to say on the arrangement of the first straight branches 51a, 51b (in order to maintain an optimal pitch at the level of the active zone 2).

[0061] For example, the second straight branches 51b of the first electrodes 51 may be distributed along the first direction X with a constant pitch strictly greater than R (R being the constant pitch at which the first straight branches 51a of these same first electrodes 51 are distributed). Preferably, said second straight branches 51b are distributed with a constant pitch greater than 2 x R. Thus, the second straight branches 51b, 52b of the first and second electrodes 51, 52 may be widened while leaving sufficient space to insert the third electrodes 53.

[0062] Furthermore, the widths W51b, W52b of their second straight branches 51b, 52b, measured along X, can be chosen to be large enough to accommodate the contacts 9 without risk of short-circuiting with an adjacent third electrode 53.

[0063] To facilitate the resumption of contact on the third electrodes 53, without risk of short circuit on the neighboring electrodes 51, 52, each third electrode 53 extends between a first and second neighboring electrodes 51, 52 and beyond these first and second neighboring electrodes 51, 52. Thus each third electrode 53 has at least one free portion 53c, 53d, forming a fin without any other electrode directly in contact with it. Thus, despite the small width of the third electrodes 53, they can be connected to a contact 9 without risk of short circuit.

[0064] In the example of Figures 3 and 4, the third electrodes 53 have two portions 53c, 53d extending beyond the first and second electrodes 51, 52. For example, the first straight branch 53a of each third electrode 53 extends in the first direction X, overlapping the active zone 2 and exceeding the neighboring first and second electrodes 51, 52. Each third electrode 53 then has a first free portion 53c extending in the first direction X, from one end of a first or a second electrode 51, 52. Each first free portion 53c then has a length L53c, measured in the direction X and from one end of a first or a second electrode 51, 52, which is not zero.

[0065] In Figures 3 and 4, the first free portions 53c are connected to the contacts 9.

[0066] In the example of Figures 3 and 4, each third electrode 53 also has a second free portion 53d extending beyond the first and second electrodes 51, 52. The second straight branch 53b of each third electrode 53 extends in the second direction Y, exceeding the neighboring first and second electrodes 51, 52. Each third electrode 53 then has a second free portion 53d extending in the second direction Y, from one end of a first or a second electrode 51, 52. Each second free portion 53d then has a length L53d, measured in the direction Y and from one end of a first or a second electrode 51, 52, which is not zero.

[0067] [Fig.7] shows an embodiment of circuit 1 in which the second free portions 53d are connected to contacts 9.

[0068] [Fig. 5] schematically shows a section of the electrodes 51, 52, 53 of the circuit 1 of FIGS. 3 and 4, this section being made at the level of the active zone 2 and in the direction Y. This section shows in particular the arrangement of the first branches of the electrodes 51a, 52a, 53a at the level of the active zone 2.

[0069] The electrodes comprise three subsets 51, 52, 53 of electrodes which correspond to first electrodes 51, second electrodes 52 and third electrodes 53. The first electrodes 51 are three in number in these examples. The second electrodes 52 are two in number. The third There are six electrodes 32. Electrodes 51, 52, 53 extend over the gate oxide 22. The electrodes are arranged side by side in an alternating manner. They are separated from each other by an insulating film 31 which can be an oxide film. The insulating film has for example a thickness between 1 nm and 5 nm.

[0070] In this embodiment, the first and second electrodes 51, 52 are made of polycrystalline silicon. The third electrodes 53 include a metal layer 531, for example made of Ti / TiN, lining the cavity in which the electrode 53 is located, and a conductive material 532, for example made of W, filling the lined cavity. When the first and second electrodes 51, 52 are made of the same material, they can be used interchangeably to form the quantum boxes in the active zone 2.

[0071] Alternatively, the first, second and third electrodes 51, 52, 53 are made from the same material. All the gate electrodes (51, 52, 53) can be used interchangeably to form the quantum dots in the active zone 2.

[0072] The first, second and third electrodes 51, 52, 53 each have, at the level of the active zone 2, a width W51, W52, W53 of between 20 nm and 80 nm. Their side-by-side arrangement is carried out periodically. The first electrodes 51 are arranged according to a pitch R (also called period or “pitch” in English), which, measured in the Y direction, is preferably less than or equal to 80 nm. A second electrode 52 and two third electrodes 53 are inserted between two neighboring first electrodes 51. The resulting final arrangement has a pitch R / 4. The final pitch R / 4 makes it possible to form quantum dots in the qubit layer 21 having a dimension along Y which is reduced, for example of the order of 20 nm. Recall that at this length, the electrostatic charges distributed in the qubit layer 21 no longer significantly modify the shape of the quantum dots and therefore the location of the qubits in the dots.This circuit 1 therefore offers better localization of the qubits in the qubit layer 21. It therefore offers better robustness and / or better reproducibility with regard to the operations which can be carried out on the qubits.

[0073] [Fig. 6] schematically shows a variant of the electrodes 51, 52, 53 shown in [Fig. 5]. This variant is materialized along the same section plane as [Fig. 6], at the level of the active zone 2.

[0074] Unlike the embodiment of [Fig. 5], the first, second and third electrodes 51, 52, 53 each have a metal layer 511, 521, 531, for example Ti / TiN, lining the cavity receiving each electrode 51, 52, 53, and a conductive material 512, 522, 523, for example W, filling the lined cavity.

[0075] The insulating film 31 separating the electrodes 51, 52, 53 also has differences in that it has a greater thickness vertically of the third electrodes 53. The third electrodes 51, 53 therefore have a distance from the qubit layer 21 which is greater than that of the first and second electrodes 51, 52. This may result from the method of manufacturing the third electrodes 53 according to which the cavities intended to accommodate the third electrodes 53 may first be lined with the film 31, for example made of oxide, before being lined in turn with a metallic layer of Ti / TiN and filled with W. It may also result from this method of manufacturing that the third electrodes 53 have a width W53 less than the width W51, W52 of the first or second electrodes 51, 52. However, this reduction of width W53 of the third electrodes does not impact the pitch at which the electrodes 51, 52, 53 are distributed.

[0076] Figures 8 to 21 schematically present different steps of a method of manufacturing a circuit 1 as presented in the different embodiments of Figures 3 to 7.

[0077] [Fig.9] shows the result of a first step of the process consisting of the formation of the first gate electrodes 51. This step may be preceded by a preliminary step of defining the active zone 2, as illustrated by [Fig.8]. This step is carried out using a semiconductor substrate 4. The semiconductor substrate 4 is a solid substrate, for example made of silicon, or a substrate of the “SOI” type (for “Semiconductor On Insulator” in English, i.e. “semiconductor on insulator”). In the example of [Fig.8], it is a substrate 4 of the SOI type with a thick semiconductor layer 41 made of silicon extending over a buried insulating layer 42 made of silicon oxide. The active zone 2 is formed by etching the thick layer 41 through a mask. This etching makes it possible to delimit the qubit layer 21. The etching is for example carried out over a thickness of between 5 nm and 30 nm. The gate oxide 22 can then be deposited on the qubit layer 21 so as to form the active zone 2.

[0078] As mentioned previously, the delimitation of the active zone 2 can be achieved by etching a trench in the thick layer 41 rather than the total removal of the part of the substrate 4 which surrounds the active zone 2.

[0079] [Fig.9] shows the result of the step aimed at forming the first electrodes 51. The first electrodes 51 extend over the active area 2. The circuit precursor 1' as illustrated comprises in particular three first electrodes 51. Each first electrode 51 extends partly over the substrate 4 and partly over the active area 2. They each have two straight branches 51a and 51b, consecutive and arranged perpendicular to each other. A first straight branch 51a extends partly over the active area 2, substantially perpendicular to an edge of the latter, and a second right branch 51b extends substantially perpendicular to the first right branch 51a.

[0080] The first electrodes 51 are spaced apart, that is, there is no direct contact between them. In the advantageous mode presented in [Fig. 9], they are also arranged partly parallel to each other. By arranged partly parallel, it is meant that the first straight branches 51a are parallel to each other and that the second straight branches 51b are parallel to each other. According to another way of putting it, a first electrode 51 is the image of another first electrode 51 by translation.

[0081] The formation of the first electrodes 51 can be carried out by depositing a layer of a first material, covering the substrate 4 and the active zone 2. The layer of first material is etched through a first hard mask 61 deposited on the first material. The parts of first material extending under the first hard mask 61 form the first electrodes 51. Preferably, the deposition of the first hard mask 61 is preceded by chemical-mechanical polishing (called “CMP” for “Chemical and Mechanical Polishing” in English) so that the first material has a flat surface.

[0082] The first material may be a conductive material, if the electrodes 51 are not subsequently removed. This is, for example, polycrystalline silicon. It may also be a sacrificial material if the first electrodes 51 are removed to be redeposited. In both cases, the first material is chosen for its etching speed, which is high compared to that of the hard mask 61. The hard mask 61 is, for example, a silicon oxide SiO2 or a silicon nitride SiN. The anisotropic etching may be carried out by so-called “dry” etching, i.e. using a plasma, for example argon.

[0083] The photolithography of the first hard mask 61 on the layer of first material is carried out by considering a pitch R achievable by photolithography equipment. This is preferably the maximum resolution achievable by said equipment, i.e. the smallest pitch achievable. In the case of equipment operating in the deep ultraviolet spectrum (called “DUV” for “Deep UV” in English), the pitch R is for example equal to 80 nm. This pitch R thus makes it possible to form first electrodes 51 which, when they are as close as possible to each other (for example at the level of the active zone 2), are distributed according to this pitch R.

[0084] The first electrodes 51 are formed with a width W5la at their first straight branches 51a which is less than R / 3 and preferably less than or equal to R / 4. The pitch of the first electrodes 51 at their first straight branches 51a makes it possible to define the final pitch R / 4 of the electrodes 51, 52, 53 of the final circuit 1 at the active zone 2 (and therefore of the qubit layer 21). In tra working at maximum resolution, we guarantee a final step R / 4, which is minimal. We thus obtain narrow quantum dots that are little, if any, deformed by the electrostatic charges dispersed in the qubit layer 21.

[0085] The first electrodes 51 each have a flank 510 which is a lateral surface delimiting each electrode 51. These flanks 510 are formed during the anisotropic etching of the first material and are therefore oriented in the direction of the anisotropic etching. This etching is preferably carried out at an angle relative to the substrate which is substantially perpendicular. Each flank 510 has two portions 513, 514 opposite each other, in other words two surfaces opposite each other, forming opposite sides.

[0086] By convention, a first electrode 51 has a single flank 510 which entirely delimits said electrode 51. In other words, the flank 510 goes all the way around the electrode 51. The opposite sides 513, 514 join the ends 515, 516 of the electrodes 51.

[0087] The first electrodes 51 are advantageously formed so as to have a width W51b at their second straight branches 51b which is wider than the width W51a of the first straight branches 51a. Indeed, this widening makes it possible to offer a large surface area for contact recovery.

[0088] This widening of the second straight branches 51b relative to the first straight branches 51a is made possible by the substantially perpendicular orientation of the two straight branches 51a, 51b. Thus, the width W51b of the second straight branches 51b, measured along the X direction, can be increased without increasing the width W51a of the first straight branches 51a along the Y direction.

[0089] Figures 10 and 11 show a step of forming layers of dielectric material 71, called “spacers”, extending against the opposite sides 513, 514 of the first electrodes 51. [Fig. 11] shows a section of [Fig. 10] along the plane AA, perpendicular to the first branches 51a of the first electrodes 51.

[0090] To obtain the spacers 71, a layer of dielectric material is for example deposited conformally on the first electrodes 51 and in particular on the flanks 510 of these electrodes 51. Anisotropic etching is then carried out to delimit the spacers 71. The anisotropic etching is carried out with a direction substantially parallel to the flanks 510. It is stopped when the gate oxide 22 is reached. Thanks to the conformal deposition and the anisotropic etching, there remains a layer of dielectric material 71 extending against each opposite side 513, 514. Since the etching is stopped when the gate oxide 22 is reached, the spacers 71 extending on adjacent electrodes 51 are distinct and distant from each other.

[0091] Each spacer 71 has a width W71 (measured from the opposite side 513, 514 on which it is in contact and perpendicular to this side) which is preferably constant whatever the branch 51a, 51b considered of the electrode 51. This thickness W71 can however be greater at the level of the second branches 51b when these are sufficiently spaced. The thickness of the layer of dielectric material deposited in a conforming manner defines the width W71 of the spacers 71.

[0092] The spacing C71a between two adjacent spacers 71, at the level of the first branches 51a (considering that they are distributed according to the pitch R), is equal to C71a = R-2W71 -W51a.

[0093] Advantageously, the thickness of the layer of dielectric material deposited conformally to form the spacers is less than R / 3. In this way, the spacers 71 have, after formation, spacing C71a after the etching step, allowing the insertion of the second electrodes 52. Ideally, the thickness of the layer of dielectric material is less than or equal to R / 4 so that the spacers 71 have a thickness W71 less than or equal to R / 4. The second electrodes 52 thus have, at the first branches 51a of the first electrodes 51, a thickness W52a greater than or equal to R / 4.

[0094] [Fig. 12] shows the outcome of a step of partial etching of the first electrodes 51 from each of their ends 515, 516. The etching is carried out in a direction parallel to the substrate 4 so as to remove sections 517, 518 extending from the ends 515, 516 of the electrodes 51. The first electrodes 51 have, after etching, new ends 515', 516'. The partial etching is carried out selectively with respect to the spacers 71. In this way, each spacer 71 has two portions 711, 712, freed from the first electrode 51 on which it was supported, forming a fin.

[0095] In a subsequent step, the spacers 71 are replaced by conductive electrodes and in particular the third electrodes 53 as illustrated in FIGS. 3 to 7. The fins 711, 712 released by the etching form the free portions 53c, 53d of the third grid electrodes 53. By way of reminder, these free portions 53c, 53d are connected to contacts 9 in a subsequent contact resumption step. [Fig. 12] shows an etching performed from the two ends 515, 516 of the first electrodes 51. However, an etching performed from only one of these ends 515 or 516 may be sufficient to form the free portions 53c or 53d of the third electrodes 53. It is therefore advantageous for the etching to be performed such that the length of one of the segments 517, 518 allows easy contact resumption at the free portions 53c, 53d.The length of the section 517, 518 depends on the number of contacts 9 to be positioned and the number of first grid electrodes 51. For example, for three (3) first grid electrodes 51, six (6) contacts 9 can. be necessary (if contacts 9 are positioned on the same side). The removed section 517, 518 may have a length of at least 300 nm.

[0096] Figures 13 and 14 show two sub-steps for carrying out the partial etching of the first electrodes 51. The etching is carried out in particular using the device illustrated in Figures 10 and 11, for which the flank 510 of each first electrode 51 is continuously surrounded by a spacer 71, even at two ends 515, 516. Thus, a first sub-step consists of releasing at least one end 515, 516 of the first electrodes 51, for example by cutting one of the ends 515, 516. By end, we mean a portion of the flank 510 which is located for example at an apex of the electrode 51.

[0097] In order to expose the ends 515, 516, the first electrodes 51, surrounded by their spacers 71, are covered with a first dielectric layer 81, called the encapsulation layer or “PMD layer”, for “pre-metal dielectric” in English. This is for example a SiO2 layer which can be obtained by plasma deposition. The PMD layer 81 completely covers each electrode 51, each hard mask 61 and each spacer 71. A chemical-mechanical planarization (called “CMP” for “Chemical and mechanical planarization”) can be carried out while ensuring that the thickness h81 of the first PMD layer 81 remains sufficient to allow the aforementioned elements to be covered. A thickness h81 of the PMD layer 81 of 1.5 times the height h51 of the first electrodes 51 is for example sufficient.

[0098] A trench 811, 812 is made from the surface of the PMD layer 81 and at each end 515, 516 of the electrodes 51, in order to release the latter. In this case, two trenches 811, 812 are made, each being arranged vertically above one end 515, 516 of an electrode 51. In other words, the ends 515, 516 of each first electrode 51 are arranged in the volume which is removed to form the trenches 811, 812. The trenches 811, 812 can be made by anisotropic etching, for example through a mask, and stopped at the substrate 4. When the trenches 811, 812 are etched, the ends 515, 516 of each electrode 51 are then also etched. The spacer portions 71 which cover the ends 515, 516 of the electrodes 51 are then also etched, in other words removed, thus freeing the ends of the electrodes 51.A portion, preferably small, of the electrodes 51 can also be removed during the etching of the trenches 811, 812. The ends 515, 516 can then be slightly moved back and positioned directly above the walls delimiting the trenches 811, 812.

[0099] The free ends 811, 812 of the first electrodes 51 expose the first material of each electrode 51 so that it can be removed.

[0100] [Fig. 12] shows the result obtained when the end sections 517,518 (extending from the ends 515,516) are removed from the device of the [Fig. 14]. The removal is for example carried out by isotropic etching of the electrodes 51 using the trenches 811, 812 which allow the ends of the electrodes 51 to be exposed to an etching solution. Thus, the etching is carried out parallel to the surface of the substrate 4, by nibbling the electrodes 51 from their ends 515, 516 and towards their center. The duration and the etching speed determine the length of the section which is removed. It also determines, in a complementary manner, the length of the free portions 53c, 53d.

[0101] Said solution is for example tetramethylammonium hydroxide, also known as “TMAH”. The etching solution is advantageously chosen to allow selective etching with respect to the material of the spacer 71 and preferentially to the hard mask 61.

[0102] It is however preferable that the etching of the extreme sections 517, 518 does not reach the active zone 2. It is moreover preferable that the remaining parts of the first electrodes 51 extend beyond the active zone 2 so as not to induce an edge effect at the level of the active zone 2.

[0103] The anisotropic etching of the first electrodes 51 carried out from one end 515, 516 makes it possible to simply control the length of the section which is removed. It is sufficient to adjust the etching speed and the etching time, which are easily controllable parameters. The anisotropic etching from one end also makes it possible to reduce the occurrence of alignment problems. Indeed, the removal of the sections carried out by anisotropic etching perpendicular to the substrate requires a step of aligning a mask with respect to the electrodes and the spacers, which inevitably induces an alignment error. The length of the fins of the third electrodes could then be strongly impacted and cause subsequent connection problems during a contact resumption step. The control of the length of the sections offered by the invention makes it possible to guard against this type of problem.

[0104] [Fig. 15] shows the device of [Fig. 12] in which the end sections 517, 518, after their removal, have given way to a PMD type oxide. The PMD oxide makes it possible to maintain the fins 711, 712 of the spacers 71 for the subsequent manufacturing steps.

[0105] This PMD oxide is for example deposited after partial removal of the first PMD layer 81. The partial removal is for example carried out by CMP with a stop at the level of the hard mask 61 or the first material of the first electrodes 51. A second PMD layer 82 is deposited on the device so as to completely fill the space left by the removed end sections 517, 518. This deposition is for example carried out in a conformal manner. The device of [Fig. 15] is presented after a new planarization by CMP to update the spacers 71 and the partially etched first electrodes 51.

[0106] The device of [Fig. 16] comprises the second electrodes 52 as shown in Figures 3 to 7. Unlike the device of [Fig. 15], the second electrodes 52 are arranged between each pair of adjacent spacers 71.

[0107] The first and second electrodes 51, 52 are arranged according to a pitch R / 2, i.e. half of the initial pitch R. This is due to the insertion of the electrodes 52 between the spacers 71.

[0108] Figures 17 and 18 show two intermediate devices that can be obtained during a first implementation of sub-steps making it possible to produce the first and second definitive electrodes 51, 52 as illustrated in [Fig. 16]. These two sub-steps take as input the device of [Fig. 15].

[0109] According to the first embodiment of the sub-steps for forming the second electrodes 52, first trenches 821 are first formed between pairs of adjacent spacers 71; then the first electrodes 51 are removed leaving second trenches 822 free; finally the first and second trenches 821, 822 are filled with a conductive material in order to form the first and second electrodes 51, 52. The filling with the conductive material may be preceded by a deposition of a conductive film, for example Ti / TiN, on the walls of the first and second trenches 821, 822. The conductive material, for example W, may then be deposited to fill the trenches 821, 822.

[0110] When the materials of the first and second electrodes (51, 52) are identical, this makes the electrodes interchangeable with respect to the quantum dots in the qubit layer.

[0111] The second mode of implementing the sub-steps for forming the second electrodes 52 may be chosen when the first electrodes 51 are formed from a conductive material such as polycrystalline silicon. Unlike the first mode of implementation, it is not necessary to remove the first electrodes 51. They can be retained. Thus, it is only necessary to form the first trenches 821 between adjacent spacers 71; then fill these first trenches 821 with a conductive material or a gate structure to form the second electrodes 52.

[0112] [Fig. 17] shows the first trenches 821 that can be dug in the second PMD layer 82, for example following the first implementation of the aforementioned sub-steps. These first trenches 821 extend between the first electrodes 51, and in particular between the spacers 71. The first trenches 821 extend at least over the active zone 2 and between the second branches 51b of the first electrodes 51.

[0113] In practice, these first trenches 821 can be made by selective etching of the second PMD layer 82 through a hard mask. The etching is carried out se selectively with respect to the spacers 71 and to the first material of the first electrodes 51. In the case of [Fig. 17], a mask (not shown) having a rectangular opening is arranged on the first electrodes 51. The opening of the mask is adjusted to be vertical to at least part of the two branches 51a, 51b of each first electrode 51 and in particular to its central section 511. The opening of the mask is also advantageously arranged vertically to the active zone 2. In other words, the projection of the opening of the mask on the substrate 4 overlaps the active zone 2. Thus, the second electrodes 52 which will be produced will extend over the active zone 2, or even beyond the active zone 2 to reduce edge effects.

[0114] The opening of the mask is also arranged so that the second electrodes 52 all have second branches 52b, extending substantially perpendicularly to the first branches 52a. In this way, the final electrodes 51, 52 can be connected via a contact resumption step.

[0115] The etching of the first trenches 821 is for example carried out by plasma.

[0116] [Fig. 18] shows the device obtained after the formation of the first and second trenches 821, 822. The second trenches 822 are for example obtained by removing the first electrodes 51. This removal is carried out selectively with respect to the spacers 71. The spacers 71 are thus released and have, on either side, first and second trenches 821, 822 in which a conductive material or a grid structure can be deposited to form the first and second electrodes 51, 52.

[0117] The removal of the first electrodes 51, or more particularly of the first material, can be carried out by anisotropic and selective etching with respect to the spacers 71. This is for example a wet etching.

[0118] When the first electrodes 51 are separated from the active zone 2 by a dielectric heel, for example made of oxide, the latter can also be removed, for example by etching using hydrofluoric acid.

[0119] The formation of the first and second electrodes 51, 52 is obtained by filling the first and second trenches 821, 822 with a conductive material or a grid structure.

[0120] In the case of a conductive material, the latter is for example deposited so as to cover the spacers 71, for example in a conformal manner. Planarization by CMP with a stop on the top of the spacers 71 thus makes it possible to form the first and second electrodes 51, 52 of FIGS. 3 to 7 and 16.

[0121] The conductive material is for example intrinsically doped polycrystalline silicon.

[0122] By grid structure is meant a structure having an outer envelope conductive, for example tungsten, intended to line the walls of the cavity in which the structure is formed, and a conductive filling material, for example a titanium nitride. In the case where the first and second definitive electrodes 51, 52 have a grid structure, a first conductive material for forming said conductive envelope is deposited in a conformal manner so as to line the first and second trenches 821, 822.

[0123] The filling material is then deposited so as to cover the assembly. Planarization by CMP with a stop at the top of the spacers 71 thus makes it possible to form the final electrodes 51, 52.

[0124] Since the previous etching and / or acid cleaning steps may have damaged the gate oxide 22 of the active area 2, it may be preferable to form, initially, a dielectric material lining at least the bottom of the first and second trenches 821, 822 before forming the electrodes 51, 52 in these trenches 821, 822. Thus, the qubit layer 21 of the active area 2 is protected and insulated. The dielectric material is for example silicon oxide. The dielectric material may be formed by atomic layer deposition (ALD). Alternatively, it may be formed by oxidation of the silicon of the qubit layer 21. Said dielectric material has a thickness of approximately 1 to 5 nm.

[0125] Unlike the first embodiment mentioned above, in the second embodiment for forming the second electrodes 52, only the first trenches 821 are dug, for example in the same way as described previously. The first electrodes 51, when formed by a conductive material, are not removed. In other words, the intermediate device of [Fig. 18] is not obtained.

[0126] The formation of the second electrodes 52 is then obtained by filling the first trenches 821 with a conductive material or a grid structure.

[0127] In the case of a conductive material, the latter is for example deposited in a manner similar to the previous embodiment. When the first electrodes 51 are formed in a conductive material, for example intrinsically doped polycrystalline silicon, and the first trenches 821 are filled with the same conductive material, all the second electrodes 52 are then formed by the same material.

[0128] Alternatively, the first trenches 821 may be filled with a different conductive material, thereby providing first and second electrodes 51, 52 of two different types.

[0129] The same applies when the first trenches 821 are filled with a grid structure as described previously. Here too, the first and second electrodes 51, 52 are of two different types.

[0130] Since the formation of the first trenches 821 and / or the acid cleaning of these trenches 821 may have damaged the gate oxide 22 of the active zone 2, a complementary gate oxide may be formed to line the first trenches 821, in the same manner as previously explained (for example by ALD). As a result, the second electrodes 52 will extend over an excess thickness, called a “heel” or “shim”, extending over the qubit layer 21. The thickness of this heel may be adjusted during the deposition of the dielectric material (for example between 3 and 5 nm). This difference in height (in other words, the presence of a heel or not) may make it possible to modify the coupling with the qubit layer 21 relative to the first electrodes 51, so as to modify the function of these gates. A different thickness and / or a different material of the heel than that of the gate oxide allows to adjust the threshold voltage of the electrodes 51,52,53.

[0131] [Fig. 19] shows the device obtained after formation of the third definitive electrodes 53. Apart from the presence of the contacts 9, this device corresponds to the circuit 1 of figures 3 to 7. In this device, the spacers 71 of [Fig. 16] are replaced by the third electrodes 53.

[0132] [Fig. 20] shows a device in which the spacers 71 have been removed. The latter have for example been etched selectively with respect to the first and second electrodes 51, 52. The etching is for example carried out isotropically, for example by wet method. This is for example H3PO4 if the spacers 71 are made of silicon nitride. The removal of the spacers 71 frees up third trenches 823.

[0133] When the second electrodes 52 are formed while retaining the first electrodes 51, the spacers 71 therefore bear directly against these first electrodes 51 and in particular against the flank 510 of these electrodes. Thus, to avoid direct contact of the third electrodes 53 with these flanks 510, it may be necessary to form an insulating layer in the third trenches 823, lining the latter and in particular lining the flanks 510 of the first electrodes 51.

[0134] The insulating layer may be deposited in the third trenches 823, for example by deposition of a dielectric material by ALD. It may also be formed thermally. For example, when the first and / or second electrodes 51, 52 are formed from a non-metallic conductive material such as polycrystalline silicon, a heat treatment of the device of [Fig. 20] under oxygen makes it possible to form an oxide film on the sides 510 of the first and second electrodes 51, 52.

[0135] The third electrodes 53 may be formed by deposition of a non-metallic conductive material, such as doped polycrystalline silicon. The latter is for example deposited conformally until completely filling the third trenches 823. Planarization by CMP with stopping at the top of the first and / or second electrodes 51, 52 makes it possible to form the third electrodes 53 of [Fig.19].

[0136] Alternatively, the third electrodes 53 may be formed by deposition of a metallic material, such as W. A first TiN layer is for example deposited conformally in the third trenches 823 to line the latter. It preferably extends over the insulating layer extending against the first and second electrodes 51, 52. A second W layer is then deposited until the third trenches 823 are completely filled. Planarization by CMP with a stop at the top of the first electrodes 31 finally makes it possible to form the second electrodes 32.

[0137] The insertion of the third electrodes 53 between the first and second electrodes 51, 52 makes it possible to distribute the electrodes 51, 52, 53 with a pitch R / 4. Thus, the electrodes 51, 52, 53 have, on the active zone 2, a reduced pitch.

[0138] [Fig. 21] shows the device of [Fig. 19] which is connected to electrical contacts 9 during a contact recovery step. The active zone 2 is also connected.

[0139] To achieve the contact recovery, encapsulation in a third PMD layer 83 is carried out. Wells intended to accommodate the contacts 9 are then produced by DUV photolithography and anisotropic etching, for example by plasma. The wells are for example located vertically to the second branches 51b, 52b of the first and second electrodes 51, 52 and vertically to the first branches 53a of the third electrodes 53 (case illustrated by FIGS. 3, 4 and 21). Alternatively, the wells can be located vertically to the second branches 53b of the third electrodes 53 (case illustrated by [Fig. 7]). The contacts 9 are for example formed by a Ti / TiN deposition followed by a W filling in order to contact all of the electrodes 51, 52, 53 manufactured.

Claims

Claims

1. A method of manufacturing an electronic circuit (1) from a substrate (4), comprising the steps of: - forming, on the substrate, first gate electrodes (51) spaced apart from each other, each first gate electrode (51) having a first branch (51a) extending parallel to a first direction (X), the first branches (51a) of the first gate electrodes (51) being distributed according to a constant pitch R, measured in a second direction (Y) perpendicular to the first direction (X); - forming spacers (71) against the first gate electrodes (51);- forming, on the substrate (4), second gate electrodes (52), each second gate electrode (52) being arranged between two neighboring first gate electrodes (51) and separated from each of them (51) by one of the spacers (71), each second gate electrode (52) having a first branch (52a) extending between the two first branches (51a) of the neighboring first gate electrodes (51); and - forming, in replacement of the spacers (71), third gate electrodes (53), each third gate electrode (53) being arranged between a first gate electrode (51) and a second gate electrode (52) adjacent to each other, each third gate electrode (52) having a first branch (53a) extending between a first branch (51a) of a first gate electrode (51) and a first branch (52a) of a second gate electrode (52).;

2. A manufacturing method according to the preceding claim, wherein the replacement of the spacers (71) by the third gate electrodes (53) comprises selective etching of the spacers relative to the first and second gate electrodes (51, 52).

3. Manufacturing method according to one of the preceding claims, in which: the first gate electrodes (51) are formed from of a first sacrificial material, such as polycrystalline silicon; - the second gate electrodes (52) are formed from a second conductive material, such as titanium nitride; and - the method comprises a step of replacing the first sacrificial material of the first gate electrodes (51) with the second conductive material.

4. Manufacturing method according to one of the preceding claims, wherein: - each first gate electrode (51) is formed so that the first branch (51a) has a first width (W51a), measured along the second direction (Y), less than or equal to R / 4; and - the spacers (71) are formed so as to have a second width (W71), measured along the second direction (Y) and at the first branches (51a) of the first gate electrodes (51), less than or equal to R / 4.

5. Manufacturing method according to one of the preceding claims, in which each third gate electrode (53) is formed so as to extend between first and second neighboring gate electrodes (51, 52) and so as to have at least one portion, called "free portion", extending beyond said first and second neighboring gate electrodes.

6. A manufacturing method according to the preceding claim, comprising, after the formation of the spacers (71) and before the formation of the second gate electrodes (52), a partial etching of each first gate electrode (51) from one end (515, 516), the etching being carried out selectively with respect to the spacers (71) so that each spacer has a free portion (711, 712) extending beyond the first gate electrodes (51), the formation of the second gate electrodes (52) being carried out so that said spacer portions (711, 712) also extend beyond the second gate electrodes (51) and so that during the formation third gate electrodes (53), each third gate electrode (53) having, after replacement of each spacer (71), a free portion (53c, 53d) extending beyond the first and second gate electrodes (51, 52).

7. Manufacturing method according to one of the two preceding claims, comprising, after the formation of the third gate electrodes (53), a step of resuming contact on each free portion (53c, 53d) of the third gate electrodes (53) extending beyond the first and second gate electrodes (51, 52).

8. A manufacturing method according to one of the preceding claims, wherein the formation of the first gate electrodes (51) is carried out such that each of the first, second and third gate electrodes (51) also comprises a second branch (51b, 52b, 53b) extending perpendicular to its first branch (51a, 52a, 53a).

9. Manufacturing method according to the preceding claim, wherein the formation of the second branches (51b, 52b) of the first and second gate electrodes (51, 52) is carried out so that, for each of the first and second gate electrodes (51, 52), a width of the second branch (51b, 52b), measured in the first direction (X), is strictly greater than a width of the first branch (51a, 52a).

10. Manufacturing method according to one of the two preceding claims, comprising a contact recovery on the second branch (51b, 52b) of each first gate electrode (51) and of each second gate electrode (52).

11. Manufacturing method according to one of claims 1 to 8, comprising, before the formation of each second gate electrode (52) and / or each third gate electrode (53), the deposition of a dielectric layer, called "gate oxide", on the substrate (4) between two neighboring first gate electrodes (51), the formation of each second gate electrode (52) and / or each third gate electrode (53) being carried out on the gate oxide.

12. Electronic circuit (1) comprising, on a substrate: - first gate electrodes (51) spaced apart from each other, each first gate electrode (51) having a first branch (51a) extending parallel to a first direction (X), the first branches (51a) of the first grid electrodes being distributed according to a constant pitch R, measured according to a second direction (Y) perpendicular to the first direction;- second gate electrodes (52), each second gate electrode being arranged between two neighboring first gate electrodes, each second gate electrode (52) having a first branch (52a) extending between the two first branches (51a) of the neighboring first gate electrodes (51), the electronic circuit being characterized in that it comprises third gate electrodes (53), each third gate electrode (53) being arranged between a neighboring first gate electrode (51) and a neighboring second gate electrode (52), each third gate electrode (52) having a first branch (53a) extending between a first branch (51a) of a first gate electrode (51) and a first branch (52a) of a second gate electrode (52), and in that the first, second and third gate electrodes (51, 52, 53) are distributed according to a average step, measured along the second direction (Y), equal to R / 4.;

13. Electronic circuit (1) according to the preceding claim, in which the first, second and third gate electrodes (51, 52, 53) extend at least partly over a portion (2) of the substrate (4), called “active zone”, configured to accommodate quantum dots.

14. Electronic circuit (1) according to the preceding claim, wherein the first gate electrodes (51) comprise a first conductive material and the second gate electrodes (52) comprise a second conductive material, identical to the first conductive material.

15. Electronic circuit (1) according to the preceding claim, wherein the third gate electrodes (53) comprise a third conductive material, identical to the materials of the first and second gate electrodes (51, 52).

16. Electronic circuit (1) according to one of the four preceding claims, in which each third gate electrode (53) has a portion (53c, 53d), called a “free portion”, extending beyond the first and second gate electrodes (51, 52), the electronic circuit (1) comprising electrical contacts (9), each electrical contact being connected to a free portion (53c, 53d) of a third gate electrode (53) extending beyond the first and second gate electrodes (51, 52).