DEVICE WITH COULOMB BLOCKADE DETECTION STRUCTURE SUPERIMPOSED ON A QUANTUM DOT

Abstract

Quantum device formed from a substrate (5), the substrate being coated with: - at least one semiconductor region (12a, 120a) forming a quantum dot (BQ), - a Coulomb blocking detection structure for detecting a charge state of the quantum dot, said Coulomb blocking detection structure comprising a detection island (ID) arranged above and opposite the quantum dot (BQ) and capable of being coupled to the quantum dot by electrostatic coupling, said detection structure further comprising at least one first tunnel junction (JT1) between said detection island (ID) and a first gate block (22), the first gate block (22) being juxtaposed with said detection island (ID). Figure for abstract: Figure 1.

Description

Title of the invention: DEVICE WITH COULOMB BLOCKAGE DETECTION STRUCTURE SUPERIMPOSED ON A QUANTUM BOX

[0001] TECHNICAL FIELD AND STATE OF THE PRIOR ART

[0002] The present application relates to the field of quantum devices in which at least one bit of quantum information based on a given quantum state among at least two measurable levels is used as an information vector. This quantum state is called a qubit or quantum bit or even "quantum bit" in English.

[0003] A special type of qubit is the spin qubit when the intrinsic degree of freedom of the spin of individual electrons is used to encode quantum information.

[0004] Qubits can be formed in a semiconductor material within nanometric-sized, electrostatically defined confinement structures. These confinement structures are typically called "quantum dots".

[0005] A quantum dot behaves like a potential well confining one or more elementary charges (electrons or holes) in a semiconductor region.

[0006] To measure the state of a qubit, it is known to carry out a spin / charge conversion which makes it possible to convert the spin state of the charged particles into a charge state of the quantum dots containing said particles. It is then necessary to measure this charge state in order to deduce the spin state of the charged particles before conversion. For this, a means for measuring the charge state is generally arranged opposite each quantum dot.

[0007] Reading a qubit can in particular be carried out using another quantum box called a “reading island” or “detection island” coupled to that of the qubit intended to be read. These two elements form two potential wells separated by a potential barrier.

[0008] Devices in which the detection islands and quantum dots are arranged opposite and in the same plane parallel to the main plane of a substrate on which the detection islands and quantum dots are formed are known.

[0009] They pose problems of size. Furthermore, due to manufacturing constraints of such devices, the possibilities of bringing together the detection structure and the quantum box are limited, which can harm the detection sensitivity.

[0010] Document FR 3066297, originating from the applicant, provides a quantum device in which, according to one embodiment, the detection structure can be located in a plane separate from that of the quantum dots. Electrostatic control grids are provided between a level in which the quantum dots are formed and a level in which charge detectors are provided. Such a device poses a problem in terms of the complexity of implementing its manufacturing process.

[0011] The problem arises of producing a quantum device that is improved with respect to at least one of the drawbacks mentioned above. Statement of the invention

[0012] According to one aspect, the present invention relates to a quantum device formed from a coated substrate:

[0013] - at least one semiconductor region in which a quantum dot is capable to be trained,

[0014] - at least a first grid block for modulating the potential of the quantum box and forming a charge reservoir,

[0015] - a detection structure for detecting a charge state of said quantum box, said detection structure comprising a detection island arranged above and opposite the quantum dot and capable of being coupled to the quantum dot by electrostatic coupling, said detection structure further comprising at least one first tunnel junction between said detection island and the first grid block, the first grid block being juxtaposed with said detection island.

[0016] The semiconductor region is typically located at a first level of the device, in other words in a first plane parallel to a main plane of the substrate, while the first gate block and the detection structure are arranged in a second level, in other words in a second plane parallel to a main plane of the substrate.

[0017] Such an arrangement with a superimposed quantum dot and detection island makes it possible to provide a reduced footprint in the plane and to achieve a close arrangement of the detection island with respect to the quantum dot, which makes it possible to establish good capacitive coupling between the detection island and the quantum dot and thus to improve the detection sensitivity. Such an arrangement of the aforementioned elements also makes it easier to integrate into a matrix provided with one or more rows of quantum dots and associated detection structures.

[0018] According to a first embodiment of the quantum device and the detection structure, a second gate block distinct from the first gate block and located in the same first plane as the first gate block and the detection island, the first plane being parallel to a main plane of the substrate, the second gate block being arranged so that the detection island is arranged between the first gate block and the second gate block, the charge detection structure being provided with a second tunnel junction formed between the detection island and the second gate block.

[0019] With such an arrangement, it is possible to implement a detection of the charge state of the quantum box by suitably biasing the first block and the second gate block so as to pass a current through the tunnel junctions. The current level then provides information on the charge state of the quantum box.

[0020] To make contact on the first grid block, a first contact pad can be provided on this first grid block.

[0021] Similarly, to make contact on the second grid block, a second contact pad can also be provided on this second grid block.

[0022] According to one possible implementation, the detection pilot may be based on the same doped conductive or semiconductive material as the gate block(s).

[0023] Advantageously, the first contact pad and the second contact pad are provided, respectively, for:

[0024] - during a so-called “detection” operating phase, apply respectively a first potential at the first gate block and a second potential at the second gate block different from the first potential so as to allow the passage of a current through said first and second junction and,

[0025] - during at least one other operating phase distinct from said phase of detection operation: apply the same given potential to the first grid block and to the second grid block.

[0026] The application of the same given potential makes it possible to prevent the circulation of current, which can prove troublesome during the operation of the qubits and to overcome problems of local heating of the device and charge noise generated near the quantum box which would be likely to disturb the state of the qubit during the operations.

[0027] Advantageously, the device may also be provided with a stage for measuring the current through said first junction and second junction coupled to the first contact pad and to the second contact pad.

[0028] According to a second embodiment of the quantum device, the device may further comprise a first contact pad on the first grating block, the first contact pad being coupled to a circuit of a reflectometry measurement device, said circuit being in particular configured to:

[0029] - emit an RF signal on the first contact pad to said detection island; detection;

[0030] - detect a variation in the phase and / or amplitude of an RF signal reflected by said island subsequent to said emission.

[0031] Advantageously, whether for the first or the second embodiment, the device may be provided with a conductive pad for electrostatic control of said detection island, said conductive pad being disposed above and facing said detection island and separated from said detection island by means of at least one dielectric region so as to allow electrostatic coupling between said conductive pad and said detection island.

[0032] According to a particular embodiment of the device, the conductive pad can be arranged in contact with a region of conductive or semi-conductive material separated from the detection island by means of the dielectric region, said detection island being based on the same material as said region of conductive or semi-conductive material.

[0033] Advantageously, the conductive pad is arranged in contact with a region of doped conductive or semi-conductive material separated from the detection island by means of a dielectric region, said region of doped conductive or semi-conductive material, said dielectric region, said detection island having the same imprint and forming the same pattern.

[0034] According to another aspect, the present invention relates to a method of manufacturing a quantum device as defined above.

[0035] According to another aspect, the present invention relates to a method of manufacturing a quantum device comprising the following steps:

[0036] - providing a substrate coated with at least one semiconductor layer, at least one region of said semiconductor layer being capable of forming a quantum dot,

[0037] - forming a bar based on at least one conductive or semiconductive material in which at least one detection island opposite said quantum box is provided,

[0038] - form at least one tunnel dielectric region on at least one lateral flank of the said bar,

[0039] - form one or more grid blocks juxtaposed to said bar and extending principally palely in a direction orthogonal to a main direction in which said bar extends, at least a first grid block among said grid blocks being arranged against the tunnel dielectric region arranged on said detection island, so as to form a tunnel junction between the first grid block and the detection island.

[0040] Advantageously, said one or more grid blocks can be formed by:

[0041] - depositing at least one grid material, then:

[0042] - etching of said grid material, said etching being carried out concomitantly with an engraving of the bar to form the detection island.

[0043] According to a particular embodiment, said bar may be based on said grid material.

[0044] Advantageously, the tunnel dielectric region may be formed by depositing a tunnel dielectric layer on the bar and then etching the tunnel dielectric layer, the etching of the tunnel dielectric layer and the etching of said bar to form the detection island and the etching of said gate material being carried out in using the same masking.

[0045] Alternatively, the tunnel dielectric region may be formed by oxidation of said bar.

[0046] According to one possible implementation, the bar is called the “upper bar” and formed by depositing a conductive material then etching the conductive material using masking, said etching of the conductive material being extended into the semiconductor layer and so as to form another bar called the “lower” bar and advantageously reproducing the shape of the upper bar.

[0047] Advantageously, at the end of said etching to form the lower bar, lateral flanks of the lower bar are revealed. The method may then further comprise: after formation of said lower bar and prior to the formation of said tunnel dielectric region, steps of:

[0048] - deposition of one or more insulating layers,

[0049] - etching of said one or more insulating layers so as to form blocks of insulating protection on either side of the lateral faces of the semiconductor region,

[0050] - formation of a tunnel dielectric region by deposition of a layer of di electric tunnel on the upper bar while the side flanks of the lower bar are protected. Brief description of the drawings

[0051] The present invention will be better understood upon reading the description of exemplary embodiments given purely for informational purposes and in no way limiting, with reference to the appended drawings in which:

[0052] [Fig.l] schematically represents an example of a quantum device according to a first embodiment in which each quantum box is associated with a Coulomb blocking detection structure arranged above and opposite this quantum box.

[0053] [Fig.2] schematically represents a variant embodiment of the quantum device for which each quantum box is formed in a semiconductor block with a width of the order of that of a detection island of said detection structure placed opposite the box.

[0054] [Fig.3] schematically represents a variant of implementation of the device quantum for which the detection structure is associated with a reflectometry measuring device.

[0055] [Fig.4] illustrates an example of a possible starting substrate for implementing a quantum device according to the invention.

[0056] [Fig.5]

[0057] [Fig.6A]

[0058] [Fig.6B] illustrate an embodiment of a conductive or semi-conductive bar in which one or more quantum boxes are intended to be formed.

[0059] [Fig.7]

[0060] [Fig. 8]

[0061] [Fig.9A]

[0062] [Fig.9B] illustrate an implementation of a plurality of electrostatic control grids of a quantum island and definition by concomitant etching to produce this quantum island and these grids.

[0063] [Fig. 10]

[0064] [Fig. 11]

[0065] [Fig.l2A]

[0066] [Fig. 12B], illustrate the optional realization of a siliciding of the top of the gate blocks when these are semi-conductors.

[0067] [Fig. 13]

[0068] [Fig.l4A]

[0069] [Fig.l4B]

[0070] [Fig. 15 A]

[0071] [Fig.l5B]

[0072] [Fig.16A]

[0073] [Fig.l6B]

[0074] [Fig. 17]

[0075] [Fig. 18]

[0076] [Fig.l9A]

[0077] [Fig.l9B]

[0078] [Fig.20]

[0079] [Fig.21]

[0080] [Fig.22] illustrate another example of a method of manufacturing a device quantum as implemented according to the present invention.

[0081] [Fig.23] illustrates an alternative embodiment for which a lower end of a pad for the control by electrostatic coupling of a detection island is arranged in contact with a conductive or semi-conductive layer provided above the detection island and separated from the island by a dielectric region.

[0082] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0083] Furthermore, in the following description, terms that depend on the orientation of the structure such as "above", "below", "back", "front", "upper", "lower", apply considering that the structure is oriented in the way illustrated in the figures.

[0084] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0085] The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other.

[0086] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0087] We first refer to [Fig.l] which gives an example of the embodiment of a quantum device according to a first embodiment.

[0088] In the particular embodiment example given in this figure, a quantum dot BQ is formed in a region of a semiconductor layer 12. This semiconductor layer 12 may be the surface layer of a substrate or a layer transferred or deposited on a substrate and formed from a semiconductor material or several stacked semiconductor materials.

[0089] According to a particular exemplary embodiment, the semiconductor layer 12 is the surface layer of a substrate of the semiconductor on insulator type, in particular a silicon layer of an SOI substrate (SOI for “Silicon On Insulator” or silicon on insulator), for example 28Si. According to another exemplary embodiment, the semiconductor layer 12 may be formed from a heterostructure, for example SiGe / Si.

[0090] The quantum box BQ ensures the confinement of at least one elementary charge (electrons or holes). Preferably, the quantum box BQ here comprises a single elementary charge. The spin of this charge, in particular an electron, can be provided to encode the quantum information. In this case, the qubit associated with the quantum box BQ is a spin qubit.

[0091] To enable the detection of the quantum box BQ, a charge detection structure is provided in the vicinity of and here above the quantum box BQ. The operation of this charge detection structure is based on a capacitive coupling, also called “electrostatic coupling,” between the quantum box BQ and a detection island ID arranged above and opposite the quantum box BQ. The detection island ID is made in a block, typically conductive or semiconductive, and separated from the quantum box BQ by means of an insulating region 13a. This insulating region 13a may be an area of ​​an insulating layer covering the surface semiconductor layer 12. The composition of the insulating region 13a, for example silicon oxide, and the thickness of this insulating layer, for example between 2 nm and 20 nm, advantageously between 5 nm and 10 nm are provided to allow coupling between the quantum box BQ and a detection island ID.Such coupling depends on the capacitance between the detection island ID and the quantum dot BQ in terms of respective surfaces facing each other, thickness of the layer. insulating material separating them and the dielectric constant of the insulator separating them. Such an arrangement of superimposed quantum dot BQ and detection island ID makes it possible to minimize the quantum dot - detector distance to ensure good detector sensitivity.

[0092] The device is here provided with a first gate block 22 and a second gate block 24 located above the semiconductor layer 12 and on either side of the island ID. These gate blocks 22, 24 serve as a reservoir of charge(s) and also to adjust the potential of the quantum box BQ. They are designed to be good conductors - including at the cryogenic temperatures of use of the device.

[0093] The first gate block 22 and the second gate block 24 are typically provided based on a doped semiconductor material such as for example polysilicon, or based on a conductive material such as for example TiN. The first gate block 22 is here located in the same plane P parallel to a main plane of the substrate as the detection island ID, this plane P being arranged above the semiconductor layer 12 in which the quantum box is arranged. By main plane of the substrate is meant a plane passing through the substrate and parallel to the plane [O; x; y ] of the orthogonal reference frame [O; x; y; z ] given in [Fig.l].

[0094] The first gate block 22 and the second gate block 24 are separated from the semiconductor region 12a in which the quantum box BQ is produced by at least one insulating layer.

[0095] The charge detection structure is a Coulomb blockade type structure here based on the passage of a current through the island ID opposite the quantum box BQ. Detection of this current provides information on the charge state of this box BQ.

[0096] The Coulomb blockade structure is provided with a first tunnel junction JT1 between the detection island ID arranged above and opposite the quantum dot BQ and a portion of the first gate block 22 juxtaposed with the detection island ID. The first gate block 22 and the detection island ID are separated by means of a tunnel dielectric region DTI.

[0097] In this particular embodiment, the second gate block 24 is juxtaposed with the detection island ID and located in the same plane P as the detection island ID and the first gate block 22, such that the detection island ID is arranged between the first gate block 22 and the second gate block 24. A second tunnel junction JT2 is provided between the detection island ID and the second gate block 24. The second gate block 24 and the detection island ID are separated by a tunnel dielectric region DT2. The Coulomb blocking structure thus has, in this particular embodiment, an operation similar to a single electron transistor (SET). The gate blocks 22, 24 can here be likened respectively to a source region and a drain region. of the transistor. The passage of a current from this transistor SET is thus controlled as a function of respective potentials applied to the gate blocks 22, 24.

[0098] Conductive contact pads 72, 74 connected to the gate blocks 22, 24 are here preferably provided to allow respective polarization potentials to be applied to them. Depending on the polarization potentials applied respectively to the pad 72 and to the pad 74, a current (shown schematically by arrows) can be caused to flow through the junctions JT1, JT2 and the detection island ID.

[0099] When not using the Coulomb blocking structure as a charge detector, in particular when initializing, controlling or maintaining at rest the qubit stored in the quantum box without reading a charge state, the contact pads 72, 74, and consequently the gate blocks 22, 24 can be set to the same first potential VG1. The transistor SET is then in a blocked operating mode so that current flow through the junctions JT1, JT2 is prevented.

[0100] This potential VGi is adjustable and can be set when initializing the quantum box BQ, so as to allow a given charge state to be imposed on this quantum box. The initialization of the quantum box BQ can then be implemented via the grid blocks 22, 24. The grid blocks on either side of the detection island ID are maintained at the potential VGi. The tunnel junctions allow the passage of charge and the filling of the island ID until the potentials between the grid blocks 22, 24 and the quantum island are balanced to a resolution of the order of a few mV or less, which does not impact the adjustment of the potential of the quantum box.

[0101] The grid blocks themselves have an influence and contribute to this adjustment to possibly go below the resolution imposed by the coulomb blockade.

[0102] During a phase of use of the Coulomb blocking structure as a charge detector, a potential difference AVSDSET is applied between the contact pads 72, 74. The contact pads 72, 74 are then set to respective distinct potentials VG2 and VG3 such that VG3 - VG2 = AVSDSET with AVSDSET 0, so as to allow a passage of current (shown by two arrows in [Fig.l]) through the Coulomb blocking structure.

[0103] According to a particular exemplary embodiment, the respective potentials VG2 and VG3 applied to the gate blocks 22, 24 may be such that VG2 = VGi and VG3 = VGi + AVSdset

[0104] The value of the current resulting from this particular polarization depends on, and therefore provides information on, the state of charge of the quantum box BQ located opposite and below the detection island ID. Detection of this current can be carried out by means of a current detection circuit which is connected to the contact pads 72, 74.

[0105] An arbitrary voltage VG can be applied to the first contact pad 72 by example via a stage equipped with a digital-to-analog converter (DAC).

[0106] The current reading at the second contact pad 74 can be done using a TIA (Trans-Impedance Amplifier) ​​circuit. In order for this pad 74 to also be biased to a controllable voltage, it is possible, for example, to use an additional digital-to-analog converter (DAC) in order to adjust the reference voltage of the TIA circuit to this value.

[0107] Optionally and advantageously, the detection island ID can itself be controlled and coupled by electrostatic coupling to an additional pad 71 to provide an additional electrostatic control means. This conductive pad 71 is here arranged above and opposite said detection island ID without being in contact with the latter. The conductive pad 71 is separated from said detection island ID by means of at least one dielectric region RDI provided, in particular in terms of composition and thickness, so as to allow electrostatic coupling between said conductive pad 71 and said detection island ID. For example, the dielectric region RDI is formed from a dielectric material such as a silicon oxide with a thickness which can be comprised for example between 5 and 15 nm.

[0108] Depending on a potential applied to the conductive pad 71, the chemical potential, in other words the Fermi level of the Coulomb blocking structure, can be adjusted. The conductive pad 71 thus offers an additional degree of adjustment for the detection structure. The voltage applied to this conductive pad 71 is used to control the chemical potential of the detection island. In other words, it makes it possible to adjust the discrete energy levels of the detection island ID relative to the potential of the grid blocks 22, 24, and therefore to switch it from a Coulomb blocking regime to an unblocked regime without having to modify the voltages applied to the grid blocks 22, 24. Furthermore, modulating this voltage provides a way to finely control the potential of the quantum dot.

[0109] A variant (not shown) without this conductive pad 71 can however be provided. The electrostatic control of the detection island ID can then be done by means of the grid blocks 22, 24, which however removes a degree of freedom in the control of the detection structure and makes the polarization of the different elements more complex.

[0110] An alternative embodiment of a quantum device as described previously is illustrated in [Fig. 2]. It differs from the embodiment described previously in particular by the configuration of the semiconductor region in which the quantum dot BQ is provided. In the particular embodiment given in this figure, the quantum dot BQ is thus formed in a semiconductor region which here does not extend over the entire surface of the substrate but only over a part of this substrate. This semiconductor region may in particular be a region of an etched or transferred semiconductor block 120.

[0111] The semiconductor block 120 may be provided with a width (dimension measured parallel to the y axis of the orthogonal reference frame [O; x; y; z] given in [Fig.2]) which is of the order of that of the detection island, preferably equal to or less than that W of the detection island ID. The width of the block 120 for accommodating the quantum box BQ may be, for example, between 20 nm and 100 nm, advantageously between 20 nm and 40 nm. With such an arrangement, and by positioning the quantum box BQ exactly in line with the detection island ID, the detection sensitivity can be maximized.

[0112] Advantageously, for this structural variant, a dielectric region 202 is provided against the lateral flanks of the semiconductor region 12a which is of composition and / or dimensions different from that of the tunnel dielectric zones DTI, DT2 against the detection island ID and preferably provided to prevent a passage of current between the gate blocks and the quantum box via the lateral flanks.

[0113] A variant of the embodiment described previously is illustrated in [Fig. 3]. The Coulomb blocking structure differs from those described previously here in particular in that it is provided with a single tunnel junction JT1 formed between the detection island ID and a first grid block 22 juxtaposed with the detection island ID. A single grid block 22 is then provided opposite a first lateral flank 301 of the detection island ID. Instead of a second grid block, an insulating region 305 is here arranged against a second lateral flank 302 of the island ID.

[0114] The detection of the state of charge of the quantum box BQ can be implemented here by reflectometry. A conductive pad 72 provided to apply a bias potential to the first gate block 22 is coupled to a circuit 350 of a reflectometry device configured to emit an SE RF signal on the contact pad 72 and receive a reflected SR RF signal following the emission of the SE RF signal.

[0115] The SE RF signal is typically a high-frequency signal (for example between 100 MHz and 1 GHz) sent to the detection island ID. The RF signal reflected by this island ID is then demodulated by the circuit 350. An inductor 352 is used to create an LC resonator composed of this inductor 352 and which depends on a quantum capacitance Cq formed by the quantum box BQ and the detection island ID. When the value of Cq varies, the phase and the amplitude of the reflected signal vary, which can be detected by measuring means. It is thus possible to know the relative state of charge of the quantum box BQ of the qubit intended to be read.

[0116] A circuit of a type as described for example in the document by RJ Schoelkopf et al., Science, 280, 5367, pp. 1238-1242, 1998 may alternatively be used.

[0117] Optionally, and again advantageously, a conductive pad 71 may be provided above and at a distance from the detection island ID. This conductive pad 71 is separated from the detection island ID by means of at least one dielectric region, and makes it possible to adjust the chemical potential of the Coulomb blocking structure by electrical coupling. trostatic with the ID detection island.

[0118] When not using the Coulomb blocking structure as a charge detector, the contact pad 72 and consequently the gate block 22, can be maintained at a given, adjustable potential.

[0119] During a phase of use of the Coulomb blocking structure as a charge detector, an RF signal is applied to contact pad 72. The amplitude of the RF signal reflected and taken from the contact pad 72 provides information on the charge configuration of the island ID, and therefore on its electrostatic environment.

[0120] In the example of [Fig.3], the quantum box BQ is provided in a semiconductor layer which can extend across the entire plate on the substrate. Here again, it is possible, as a variant, to provide for producing this quantum box in an etched or transferred semiconductor block and whose dimensions, in particular in terms of width, are substantially equal to or less than that of the island ID.

[0121] Either of the quantum devices introduced previously may comprise more than one quantum dot BQ. In reality, a quantum device according to the invention typically comprises several qubits each formed of at least one quantum dot for storing quantum information associated with a Coulomb blocking detection structure arranged above. The quantum dots may thus be arranged in at least one row or even in several rows and according to a matrix arrangement of quantum dots with a corresponding matrix arrangement of Coulomb blocking detection structures.

[0122] An example of a method for producing a quantum device of a type as described previously, in particular in connection with [Fig.l] will now be given in connection with Figures 4 to 12A-12B.

[0123] A possible starting material ([Fig.4]) for producing the device is here in the form of a substrate 5 of the semiconductor on insulator type. The substrate 5 thus comprises a so-called “support” layer 10 of semiconductor material, an insulating layer 11 arranged on the support layer 11 and a semiconductor surface layer 12 arranged on the insulating layer. The substrate 5 is for example an SOI substrate whose surface layer 12 is made of silicon. The semiconductor surface layer 12 is here intended to accommodate the quantum dot(s). The semiconductor on insulator type substrate may in particular be an SOI type substrate (for “Silicon On Insulator”) with a surface layer 12 of silicon, in particular 28Si when this layer is intended to accommodate electron spin qubits.The insulating layer 11 and the support layer 10 of the substrate are typically, respectively, a silicon oxide layer commonly called "BOX" (for "Burried Oxide" or "buried oxide") and a semiconductor layer, for example based on silicon. The thickness of the super layer. ficiel 12 is for example between 5 nm and 25 nm, typically of the order of 10 nm.

[0124] Then, one or more detection islands are created.

[0125] To do this, a stack is formed covering the surface semiconductor layer 12. This stack comprises at least one insulating layer 13, advantageously based on a gate dielectric such as, for example, silicon oxide. An insulating layer 13 with a thickness of, for example, between 5 nm and 15 nm can be formed.

[0126] A so-called “high-k” dielectric, in other words with a high dielectric constant k such as, for example, HfO2, can also be used to form this insulating layer 13.

[0127] The insulating layer 13 is topped with at least one layer 14 of semiconductor or conductive material, typically a gate material such as, for example, polysilicon with a thickness which may be, for example, between 20 nm and 50 nm. The layer 14 of semiconductor or conductive material is coated with at least one dielectric layer 15. A gate dielectric formed from a silicon oxide or a “high-k” dielectric such as, for example, HfO2 may, here again, also be used. The stack produced is then covered with at least one masking layer 17, in particular a hard mask. Such a masking layer may be formed from at least one layer of insulating material, for example, SiN and / or SiO2. In the illustrated embodiment, the masking layer is formed from a bilayer of SiN and SiO2.

[0128] One or more patterns are then defined by etching in the masking layer 17, and in particular at least one pattern, in the particular example illustrated parallelepiped, to form a masking block. This makes it possible to then transfer this pattern to the stack of underlying layers 14, 15. Anisotropic etchings, in particular using a plasma, are thus carried out to produce the masking block, then a block of corresponding shape reproducing that of the masking block in the second dielectric layer 15 and the layer 14 of gate material.

[0129] A structure that can be obtained at the end of this step is illustrated in FIGS. 6A, 6B, giving respectively a perspective view, a sectional view along a section plane parallel to a plane [O; y; z ] of an orthogonal reference frame [O; x; y; z ] given in these figures. The layer 14 forms, after etching, a block in the form of a bar 14a in which one or more detection islands ID is or are provided. In the particular embodiment illustrated, the etching to form the block 14a is stopped on the first insulating layer 13. The insulating layer 13 can in this case be kept so as to cover the entire surface layer 12.

[0130] A thin layer of tunnel dielectric 19, the thickness of which for example is comprised between 1 nm and 5 nm, depends on the material chosen is then deposited, in particular on the lateral sides of the bar 14a ([Fig.7]). The dielectric 19 used can be for example SiO2 or HfO2 formed by deposition. Alternatively, oxidation of the bar 14a can be carried out to allow the formation of a tunnel dielectric 19 on the lateral sides of the bar 14a.

[0131] Grid blocks are then formed on either side of the detection island(s).

[0132] To do this, a layer of at least one conductive material is first deposited. or semiconductor, advantageously a gate material identical to that of the bar 14a, for example polysilicon, which may optionally be doped. The production of patterns in this layer may be preceded by a CMP (“Chemical mechanical planarization”) planarization step to then form a second masking on a preferably relief-free layer. This second masking may be formed of one, or as in the embodiment illustrated in [Fig.8], of several layers 21, 23 of hard mask in which one or more patterns are then defined by etching, in particular orthogonal to the bar 14a.

[0133] An anisotropic etching of the layer of at least one conductive or semiconductive material 20 is then carried out, typically using a plasma. In the particular example illustrated in FIGS. 9A-9B, the anisotropic etching of the layer of conductive or semiconductive material 20 protected by the masking 25 is continued until the dielectric layer 19 or the insulating layer 13 is reached. Grid blocks 22, 24 are thus formed on either side of a detection island ID.

[0134] These gate blocks 22, 24 extend mainly in a direction orthogonal to that of the bar 14a before it is etched. A first gate block 22 is disposed against a region of the tunnel dielectric layer 19 arranged on a lateral flank of the detection island ID, so as to form a tunnel junction between the first gate block 22 and the detection island ID. A second gate block 24 is disposed against a region of the tunnel dielectric layer 19 arranged on an opposite lateral flank of said detection island, so as to form a tunnel junction between the second gate block 24 and the detection island.

[0135] To form the contact pads 72, 74 on the grid blocks 22, 24, one or more insulating layers can then be formed in which holes are made whose bottom reaches the grid blocks. Then, these holes are filled using a conductive material, in particular a metallic material such as, for example, W.

[0136] In the optional case where an additional conductive pad 71 is provided coupled to the detection island ID, an additional hole is formed but the bottom of which is arranged at a distance from the block 14a for receiving the detection island ID. This additional hole can be formed concomitantly with the holes for receiving the contact pads 72, 74. This additional hole is then subsequently filled with conductive material, typically at the same time time as the aforementioned reception holes.

[0137] To facilitate contact between the gate blocks and the contact pads, it is possible, optionally, to provide regions of metal and semiconductor alloy on the gate blocks 22, 24.

[0138] An example of embodiment of these regions of metal and semiconductor alloy is given in connection with figures 10, 11, 12A-12B.

[0139] In order to produce the alloy regions only on the upper faces of the gate blocks, it is possible to provide beforehand an encapsulation of the revealed lateral faces of these gate blocks 22, 24. Such an encapsulation is illustrated for example in [Fig. 10], where insulating spacers 47 are produced, for example by deposition then etching of dielectric material such as for example silicon nitride.

[0140] It is then possible, as in [Fig.l 1], to remove the masking 25 possibly preserved on the grid blocks 22, 24 to reveal their upper faces 233. In the illustrated case where a nitride layer is to be removed at the top of the grid blocks, selectively with respect to a lateral encapsulation in SiO2, a chemical etching based on H3PO4 can be used.

[0141] Then, as in Figures 12A-12B, the regions 51 based on metal and semiconductor alloy are formed on the upper faces 233 of the gate blocks 22, 24 in order to form ohmic contacts on the latter. A step of depositing at least one layer of metal, for example Ni, Pt, W, Co, Ti, can be carried out for this first. A heat treatment is then carried out to achieve siliciding. Such a treatment can be implemented at a temperature of, for example, between 400°C and 500°C and a duration adapted according to the treatment temperature. The temperature range strongly depends on the materials used and the alloy phases that one wishes to obtain.

[0142] A variant of a manufacturing method for implementing a quantum device of the type illustrated for example in [Fig.2] will now be given in connection with figures 13 to 22.

[0143] A device is manufactured here in which the quantum box(es) is(are) confined in a block also called a semiconductor bar which does not extend over the entire surface of the substrate.

[0144] The starting material may be the same substrate 5 as in the previously described embodiment.

[0145] This substrate 5 can then be coated ([Fig.13]) with a stack comprising the first insulating layer 13, the layer 14 of semiconducting or conducting material, and the masking layer 17.

[0146] A masking block 17a is then defined in the masking layer 17 and the pattern of this masking is transferred to the stack of layers 12, 13, 14 under underlying. At least one anisotropic etching using a plasma is then carried out to reproduce the pattern of the masking block in the layer 14 of gate material. In this exemplary embodiment, the insulating layer 13 and the superficial semiconductor layer 12 of the substrate are also etched in order to reproduce this same pattern in the insulating 13 and semiconductor 12 layers.

[0147] A structure that can be obtained at the end of this step is shown in Figures 14A, 14B, (giving respectively a perspective view, a sectional view along the axis A'A). A bar 140a called "upper" is formed at the end of the etching of the layer 14. In this bar 140a several detection islands are provided. A bar 120a called "lower" is located under the upper bar 140a and comes from the etching of the superficial semiconductor layer 12. In the particular embodiment illustrated, the etching to form the upper bar 140a and the lower bar 120a is stopped on the insulating layer 11 of the substrate 5.

[0148] Lateral flanks 121 of the semiconductor bar 120a are revealed at the end of this etching. In order to avoid the possibility of a current flow between the future gate blocks and the bar 120a, insulating protection blocks are then formed on either side of the lateral flanks 121 of the lower semiconductor bar 120a. A high temperature deposited oxide (HTO “High Thermal Oxide”) can be used.

[0149] The production of these insulating protection blocks may, as in the embodiment illustrated in FIGS. 15A-15B, comprise the deposition of a first thin insulating layer 151, for example a thermal silicon oxide, with a thickness which may be for example between 5 nm and 20 nm. This deposition may be followed by the deposition of a thicker insulating layer 153, for example between 50 nm and 200 nm and based on SiO2. The cumulative thickness of the insulating layers 151, 153 may then be provided to be greater than the height of the stack coated with the masking layer 17. In this case, a planarization (CMP) is then typically carried out by stopping at the level of the masking layer 17.

[0150] A partial removal of the insulating layers 151, 153 is then carried out (figures 16A-16B) so as to remove these insulating layers 151, 153 around the upper bar 140a and reveal at least a portion of the lateral faces of this upper bar 140a, while preserving these insulating layers 151, 153 against the lateral flanks 121 of the lower bar 120a. The partial removal of the insulating layers 151, 153 can be carried out by wet etching, for example using HF.

[0151] A thin layer of tunnel dielectric 159, for example with a thickness of between 1 nm and 5 nm, is then formed by deposition on the lateral faces 141 of the upper bar 140a or by oxidation of the upper bar 14a. In the particular embodiment illustrated in [Fig. 17] the thin layer of tunnel dielectric 159 also covers the masking layer 17 located at the top of the stacking of bars 120a, 140a. The thin layer of dielectric 159 tunnel layer may be, for example, based on silicon oxide and, for example, of thickness between 1 and 2 nm.

[0152] The gate blocks are then formed on either side of the stack of superimposed lower and upper bars 120a and 140a. To do this, a layer of conductive or semiconductive material 162 is first deposited ([Fig. 18]), preferably a gate material identical to that of the upper bar 140a such as, for example, polysilicon. CMP planarization is then implemented in order to match the level reached by the conductive or semiconductive material 162 with the top of the central stack in which the bars 120a, 140 are arranged.

[0153] Then, a second masking 165 is formed. In a case where the aim is to produce several detection islands and several pairs of grid blocks, the second masking 165 is formed of several distinct blocks 165a, 165b, 165c, 165d parallel to each other and which here extend orthogonally to the main direction of the superimposed bars 120a, 140a (said main direction being a direction parallel to the axis x of the reference frame [O; x; y; z] given in the figures).

[0154] An etching of the layer 162 of gate material and of the bar 140a is then carried out in order to remove areas of the layer of gate material 162 and of the bar 140a not protected by these blocks 165a, 165b, 165c, 165d of masking 165.

[0155] At the end of such etching, pairs of grid blocks 172, 174 are obtained as illustrated in FIGS. 19A-19B. Each pair of grid blocks is associated and arranged on either side of an island ID1, ID2, ID3, ID4 formed by an etched portion of the upper bar 140a.

[0156] As for the example method described previously, here again, optional steps of forming an encapsulation or insulating spacers 177 on the lateral sides of the gate blocks ([Fig.20]), of removing the second masking 165 on the upper face 173 of these gate blocks ([Fig.21]), then of producing regions 185 of metal and semiconductor alloy, in particular silicidated regions ([Fig.22]) of the gate blocks in order to produce ohmic contacts can be carried out.

[0157] Contact pads can then be formed to make contact points on the grid blocks. Conductive pads facing and at a distance from the detection islands can be provided in order to provide a means of electrostatic control of the islands above the latter.

[0158] To implement a structure such as described previously in connection with [Fig.3] where each detection island can only be associated with a single grid block, one or other of the methods described previously is adapted by forming a masking 25 or 165 which only extends from a first side of the island in order to be able to then remove the material of the grid block(s) on a second side of the island opposite the first side. Process steps as described above can then be followed.

[0159] In another alternative embodiment, illustrated in [Fig.23], provision is made to replace the masking layer 17 formed in [Fig.5] and typically made of at least one insulating material and / or commonly used to produce a hard mask, with a region 232 of conductive or semiconductive material. Advantageously, the material used to form the region 232 is a gate material which may be the same material as that used to form the detection island ID, for example polysilicon. This may make it possible to produce improved contact with a conductive pad 71 which may be provided above the island ID and which is intended to control it by electrostatic coupling. This may make it possible to have an insulating region 234 with better controlled dielectric properties and thus to be able to implement improved electrostatic coupling between the conductive pad 71 associated with the region 232 of conductive or semiconductive material and the detection island ID.

[0160] Advantageously, the region 232 of conductive or semi-conductive material, insulating region 234 and the detection island can be formed concomitantly by means of the same etching step and / or through the same masking in order to have substantially the same imprint and reproduce the same pattern.

[0161] To make a contact of the same type with a conductive pad 71 above and opposite the island ID, another method provides for replacing the layer of material used to form the island ID, in a stack of several layers comprising a first conductive or semi-conductive layer, for example polysilicon, an insulating layer on this first conductive or semi-conductive layer, and a second conductive or semi-conductive layer, preferably made of a material identical to that of the first conductive or semi-conductive layer, for example polysilicon. A hard mask used to etch this stack can then be removed after carrying out this etching and before forming the conductive pad 71. This conductive pad 71 is then typically formed by filling a hole made in an insulating layer and which opens onto the second conductive or semi-conductive layer.

Claims

Claims

1. Quantum device formed on a substrate (5) and comprising: - a first level in which at least one semiconductor region (12a, 120a) is arranged, - a second level in which at least one first gate block (22) is arranged and provided to modulate the potential of a quantum dot (BQ) formed in the at least one semiconductor region (12a, 120a), the second level also comprising a structure for detecting a charge state of the quantum dot, said detection structure comprising a detection island (ID) arranged above and opposite the quantum dot (BQ) and capable of being coupled to the quantum dot, said detection structure further comprising at least one first tunnel junction (JT 1 ) between said detection island (ID) and the first gate block (22),the first grid block (22) being juxtaposed with said detection island (ID) and the first grid block (22) forming a charge reservoir for the detection island (ID).,

2. Quantum device according to claim 1, comprising at least one second gate block (24) distinct from the first gate block (22) and located in the same first plane (P) as the first gate block (22) and the detection island (ID), the first plane being parallel to a main plane of the substrate (5), the second gate block (24) being arranged so that the detection island (ID) is arranged between the first gate block (22) and the second gate block (24), the charge detection structure being provided with a second tunnel junction (JT2) formed between the detection island (ID) and the second gate block (24).

3. The quantum device of claim 2, further comprising a first contact pad (72) on the first gate block (22) and a second contact pad (74) on the second gate block (24).

4. Quantum device according to claim 3, in which the first contact pad (72) and the second contact pad (74) are provided for: - during a so-called "detection" operating phase, respectively applying a first potential to the first gate block (22) and a second potential to the second gate block (24), different from the first potential, so as to allow the passage of a current through said first and second junctions (JT1, JT2) and, - during at least one other operating phase distinct from said detection operating phase: applying the same potential given to the first grid block (22) and to the second grid block (24).

5. A quantum device according to claim 4, wherein the first contact pad (72) and the second contact pad (74) are coupled to a stage for measuring the current through said first junction (JT 1 ) and second junction (JT2).

6. Quantum device according to one of claims 1 to 3, further comprising a first contact pad (72) on the first gate block (22), the first contact pad (72) being coupled to a circuit (350) of a reflectometry measuring device, said circuit (350) being in particular configured to: - emit an RF signal on the first contact pad to said island; - detect a variation in impedance by means of a change in amplitude or phase of the RF signal reflected by said island.

7. Quantum device according to one of claims 1 to 6, wherein the detection structure is provided with a conductive pad (71) for electrostatic control of said detection island (ID), said conductive pad (71) being arranged above and opposite said detection island (ID) and separated from said detection island by means of at least one dielectric region (RD, 234) so ​​as to allow electrostatic coupling between said conductive pad (71) and said detection island (ID).

8. Quantum device according to claim 7, in which the conductive pad (71) is arranged in contact with a region of doped conductive or semiconductive material (232) separated from the detection island (ID) by means of a dielectric region (234), said region of doped conductive or semiconductive material (232), said dielectric region (234), said detection island (ID) having the same imprint and forming the same pattern.

9. Quantum device according to one of claims 1 to 8, in which the detection island (ID) is based on the same doped conductive or semi-conductive material as the gate block(s) (22, 24).

10. A method of manufacturing a quantum device comprising the following steps: - providing a substrate (5) coated with at least one semiconductor layer (12) provided with at least one region (12a, 120a) in which a quantum dot is capable of being formed, - forming a bar (14a, 140a) based on at least one doped conductive or semiconductor material in which at least one island of detection opposite said quantum box is provided, - forming at least one tunnel dielectric region (19, 159) on at least one lateral flank of said bar (14a, 140a), - forming one or more grid blocks (22, 24, 172, 174) juxtaposed with said bar (14a, 140a) and extending mainly in a direction orthogonal to a main direction in which said bar (14a, 140a) extends, at least a first grid block among said grid blocks being arranged against the tunnel dielectric region arranged on said detection island, so as to form a tunnel junction between the first grid block and the detection island.

11. Method according to claim 10, in which said one or more grid blocks (22, 24, 172, 174) are formed by: - ​​depositing at least one grid material, then: - etching said grid material, said etching being carried out concomitantly with an etching of the bar (14a, 140a) to form the detection island.

12. A method according to claim 10, said bar (14a, 140a) being based on said grid material.

13. A method according to one of claims 11 or 12, wherein the tunnel dielectric region is formed by depositing a tunnel dielectric layer (19, 159) on the bar (14a, 140a) and then etching the tunnel dielectric layer (19, 159), the etching of the tunnel dielectric layer and the etching of said bar (14a, 140a) to form the detection island and the etching of said gate material being carried out using the same masking.

14. A method according to one of claims 10 to 13, wherein the tunnel dielectric region is formed by oxidation of said bar.

15. Method according to one of claims 10 to 14, in which said bar is called "upper" and formed by depositing a conductive material then etching the conductive material using masking, said etching of the conductive material being extended into the semiconductor layer (12) and so as to form another bar (120a) called "lower".

16. The method of claim 15, wherein upon completion of said etching so as to form said other lower bar (120a), lateral flanks (121) of the lower bar (120a) are revealed, the method further comprising: after formation of said lower bar (120a) and prior to formation of said tunnel dielectric region, steps of: - depositing one or more insulating layers (151, 153), - etching said one or more insulating layers (151, 153) so as to form insulating protection blocks on either side of the lateral faces of the semiconductor region, - forming a tunnel dielectric region by depositing a tunnel dielectric layer (159) on the upper bar (140a) while lateral flanks of the lower bar (120a) are protected.

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