MICROELECTRONIC DEVICE OBTAINED BY 3D INTEGRATION AND CORRESPONDING MANUFACTURING PROCESS

Abstract

A 3D microstructure is formed by bonding an upper plate (1) to a lower plate (2) via a hybrid bond with metallic bonding pads (17b, 17c; 27b, 27c) at the interface between the upper metallization level (HBM) of the respective interconnection structure of each plate. These interconnection structures further include a horizontal interconnection level (MX) directly below the upper interconnection level (HBM). These pads are distributed horizontally in a substantially homogeneous manner and with a fine bonding pitch. Among these pads, only the bonding pads (17b; 27b) are electrically isolated from any horizontal metallization element (15; 25) of the horizontal interconnection level (MX).Conversely, bonding and electrical connection pads (17c; 27c) are electrically coupled, without vias, to an underlying horizontal metallization element (15; 25) formed in the horizontal interconnection level (MX). Figure 2.

Description

Title of the invention: MICROELECTRONIC DEVICE OBTAINED BY 3D INTEGRATION AND CORRESPONDING MANUFACTURING METHOD technical field

[0001] The invention relates generally to the field of the microelectronics or semiconductor industry. It relates more particularly to three-dimensional (3D) integration, by the vertical assembly of two two-dimensional (2D) microelectronic devices, each formed on a wafer or a die made of the respective semiconductor material, known as W2W (from the English "Wafer-to-Wafer") or D2W (from the English "Die-to-Wafer") or D2D (from the English "Die-to-Die") bonding, for the realization of a 3D microelectronic device.

[0002] More specifically, the invention relates to a 3D microelectronic structure (or 3D microstructure) obtained by bonding a first upper wafer to a lower wafer with a high density of interconnection between said wafers, as well as a method for making such a 3D microelectronic structure for the manufacture of an integrated semiconductor product.

[0003] It finds applications, in particular, in the manufacture of high-density integration microsystems and components, such as microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS), actuators, radio frequency (RF) components, power devices, or microelectronic devices such as advanced microprocessors, graphics chips, optoelectronic circuits such as, for example, image sensors (or imagers) in CMOS (Complementary Metal-Oxide-Semiconductor) technology, or other. PREVIOUS STATE OF THE ART

[0004] The microelectronic devices used in the composition of packaged semiconductor products (or integrated circuits) are manufactured through essentially planar technological steps. These steps are performed on wafers made of semiconductor material, such as doped silicon. More specifically, a series of technological steps are implemented, starting from a planar substrate that supports the device, with access to the microstructure being fabricated at each step via the top face of the wafer, also called the "front face." The size of a wafer is generally about 200 mm. diameter in 8" technology (i.e., 6 inches) or approximately 300 mm in diameter in 12" technology.

[0005] A wafer on which a microelectronic device is fabricated comprises a substantially flat substrate, with an active area in the upper part of said substrate in which the active components of the device are fabricated, and a multilayer interconnection structure formed above said active area of ​​the substrate for connecting the previously formed active components to each other and to the pins of the integrated circuit. Optionally, the interconnection structure may also incorporate passive components (inductors, capacitors, resistors, etc.) fabricated as metallic elements in the stacked interconnection layers.

[0006] The fabrication of the active components of the device in the active area of ​​the substrate corresponds to the FEOL (Front-End-of-Line) phase of the device manufacturing process. The fabrication of the interconnection structure, on the other hand, takes place during the BEOL (Back-End-of-Line) phase of the manufacturing process. The FEOL phase will not be specifically addressed here, as the invention is implemented during the BEOL phase.

[0007] The interconnection structure comprises a stack of interconnection layers, arranged sequentially with alternating horizontal and vertical interconnection layers. The former include horizontal metallizations, i.e., metallic traces extending parallel to the plane of the wafer to electrically connect respective elements of the active components made in the active area of ​​the substrate, and / or, where applicable, metallic elements forming the aforementioned passive components. The latter include vias extending perpendicularly to the plane of the wafer to electrically connect metallic traces and / or passive components belonging to their respective horizontal interconnection layers.

[0008] The formation of such an interconnection structure by the process known as Damascus comprises successively, for each level of interconnection to be implemented in stacking: • the deposition of a layer of dielectric material on the upper face of the substrate of the microelectronic device, for the first interconnection layer, or on the upper face of an interconnection layer already made, for any interconnection layer following said first interconnection layer; • the etching, in this dielectric layer, of trenches (for horizontal interconnection layers) or of via passage holes (for vertical interconnection layers); • the deposition of copper (Cu) onto the etched dielectric layer, in order to fill the trenches and / or via holes, to obtain the desired metallic interconnecting elements; and, • the mechanochemical polishing of excess copper in order to flatten the upper surface of the interconnection layer thus produced, with a view to the formation of another level of interconnection on top of the one which has just been produced.

[0009] Wafer bonding refers to a technology for vertically joining a first wafer, called the top wafer, to another wafer, called the bottom wafer, also known as the handle wafer, in reference to its function of supporting the resulting microstructure. To this end, the first wafer is inverted vertically, then aligned and deposited with its front face onto the front face of the handle wafer. If the top surfaces of the respective wafers brought into contact are extremely flat, Van der Waals forces, namely microscopic attractive interactions that exist for all materials, ensure adhesion between the top and bottom wafers. In the relevant technical field, the term "bonding" is used to describe an assembly based on the use of these adhesive forces.Adhesion is stronger when the contact surface between the two plates is large at the microscopic level, hence the importance of eliminating all surface imperfections at this scale. The upper surfaces of the two plates, corresponding to their respective front faces, are therefore ultra-polished prior to their assembly to ensure they are extremely smooth and prevent any bonding defects.

[0010] Bonding two or more wafers stacked vertically, with or without an intermediate layer, allows for the creation of a 3D microstructure, even though only 2D fabrication technologies are separately implemented in the FEOL (Front-End-of-Line) phase of manufacturing to fabricate the microelectronic devices in each of the two wafers, respectively. Various technological protocols (process flows) exist for achieving such a 3D assembly. These various technological protocols can be adapted to the specific requirements of the intended applications, which are numerous and varied. This discussion will be limited to hybrid bonding solutions for W2W semiconductor wafers, compatible with a bond between assembled wafers that is at the wafer level (a bond known as "wafer-level bonding").

[0011] The bond between the stacked wafers can be achieved, in particular, by means of bonding pads provided for this purpose. These pads are positioned opposite each other on the upper surface of each of the two wafers to be joined. In practice, the bonding pads are metal elements made from the dielectric material of an interconnecting layer, by implementing a final step of the Damascus process. Such metallic bonding pads are therefore harder than the dielectric material of the insulating layer in which they are made.

[0012] The bonding pads are more specifically formed in the final metallization level of each wafer, i.e., the highest metallization level of the interconnection structure of said wafer, which is also the level furthest from the substrate. In what follows, this will be referred to as the HBM level (from the English "Hybrid Bonding Metal"). The upper face of the bonding pads is therefore exposed on the surface of the interconnection structure of each respective wafer, which is also the surface of the wafer, at the end of the BEOL phase of the fabrication.

[0013] This embodiment of the connecting pads, made of metal, is advantageous for various reasons related, in particular, to the hardness of the metal and the technological steps involved in manufacturing such metal pads. These reasons include, in particular: • the rigidity of the upper face of the plate thus obtained (subject to a sufficient density of metal studs); • the precision of the patterns for creating the plots (by implementing the Damascus process, which is an effective and mature technique); • the quality of polishing that can be obtained by conventional mechano-chemical processes (due in particular to the relative hardness of the metal); and, • the accuracy of the alignment between the pads which can be obtained by using the metal studs for the shimming in relative positions of the two pads, etc.

[0014] Since the bonding pads are made of metal, and more specifically of copper within a layer of dielectric material using the Damascus process, they are therefore inherently electrically conductive. The bonding of the pads is described as "hybrid" because the bonding interface between the pads is heterogeneous: it comprises portions of metal corresponding to the bonding pads, on the one hand, and portions of dielectric material corresponding to the areas between said pads, on the other.

[0015] Another advantage of making connecting pads out of metal is the possibility of including the connecting pads in the routing map of the electrical signals for the operation of the finally obtained 3D microstructure. This routing can indeed be carried out by using at least some of the connecting pads to pass current between the lower and upper plates, and vice versa, of the 3D microstructure.

[0016] Among the connecting pads, there are then: • Bonding pads of a first type, which are exclusively dedicated to bonding the wafers, and which are formed by dummy metallization elements (known to those skilled in the art as "dummies"). These pads are not connected to any elements of the microelectronic device fabricated in the active area of ​​the wafer, nor to any other passive elements or vias that might be fabricated in the horizontal or vertical interconnect layers, respectively, corresponding to lower metallization levels of the interconnect structure. In other words, they are completely electrically isolated from other conductive elements belonging to active or passive devices of the wafer by the surrounding dielectric material. Therefore, they perform no function in the operation of the final microelectronic device beyond their basic role as a bonding support.Therefore, we will say that they are non-functional connecting pads; as well as, . • A second type of connecting pad, which serves both as a bonding support like the pads of the first type described above, and also provides an electrical connection between the two wafers assembled vertically by this bonding. They therefore contribute to the operation of the final microelectronic device. To make these connecting pads functional, vias are created in at least the directly lower vertical interconnect layer during the BEOL phase of the individual wafer fabrication (i.e., before they are bonded).These vias provide the electrical connection between, on one side, the functional pads in question and, on the other side, elements located below, for example, active devices (such as transistors or photodiodes) fabricated during the FEOL phase in the active area of ​​the corresponding wafer, and / or passive devices (such as conductive traces, capacitors, inductors, etc.) fabricated during the BEOL phase in the underlying horizontal interconnect layer of the corresponding wafer's interconnect structure. The vias connecting the second type of bonding pads are therefore fabricated in a dedicated metallization layer, which we will call the HBV layer (from the English "Hybrid Bonding Vias").

[0017] In summary, the first type of connecting pads (non-functional pads, or "dummies") of each of the two plates are made in the last layer of metallization of the interconnecting structure (i.e., the nth layer for an n-layer interconnect structure) corresponding to the HBM metallization level, being isolated from any underlying element of said wafer by the dielectric material of the penultimate metallization layer, which is a vertical interconnect layer corresponding to the HBV metallization level; whereas the connecting pads of the second type (functional pads) are also made in the last metallization layer of the interconnect structure but are coupled to active elements of the active zone of the substrate or to passive elements of the antepenultimate layer of the interconnect structure (which is a horizontal interconnect layer) by vias made in the penultimate layer of said structure (which is a vertical interconnect layer corresponding to the HBV metallization level). .

[0018] Furthermore, the number of bonding pads per unit area (including non-functional bonding pads, on the one hand, and functional bonding and connection pads, on the other), as well as their respective positions on the upper surface of the boards, are dictated by manufacturing and reliability constraints of the microelectronic devices. These constraints are defined in a Design Rules Manual (DRM). Adherence to such design constraints enables the development of manufacturable, functional, and reliable integrated circuits with the lowest possible energy budget and the best possible economic competitiveness.

[0019] According to these design rules, a minimum density of bonding pads and a roughly homogeneous distribution of said bonding pads on the upper surface of the pads to be bonded are required. This makes it possible to obtain, by chemical mechanical polishing (CMP), a top surface of the vertically assembled pads that is sufficiently flat to create a 3D microstructure without bonding defects. If these design rules are not followed, it is difficult to obtain pads with a perfectly flat top surface. Indeed, CMP polishing generates differences in topography between areas of varying metal density depending on the CMP brine (CMP slurry) used (erosion phenomenon). These eroded areas then appear as hollows on the surface and are therefore not bonded. These surface defects thus materialize as unbonded areas, i.e.Interface bubbles called "voids" weaken the 3D microstructure and render the affected chips non-functional (because electrical contact is no longer ensured).

[0020] The bonding pitch defines the upper limit of the spacing between the bonding pads in the horizontal XY plane of the wafer, that is, the maximum center-to-center distance between the nearest adjacent bonding pads in said horizontal XY plane. This is one of the DRM parameters to be respected during the design of the integrated circuit. The finer the bonding pitch, the higher the interconnection density, and vice versa. The invention applies in particular to embodiments with hybrid bonding of wafers with high interconnection density, i.e., with a fine bonding pitch, that is, one that is less than 10 micrometers (pm), for example, on the order of 5 pm.

[0021] In the existing art described above, the differentiation between functional and non-functional bonding pads results from the selective formation, prior to hybrid bonding, of vias in the vertical interconnecting layer corresponding to the metallization level known as "HBV," directly below the last layer of the interconnecting structure corresponding to the metallization level known as "HBM," and in which said bonding pads are produced in compliance with the DRM requirements relating to high interconnecting density. This penultimate HBV layer is a vertical metallization layer that is produced for this sole purpose in the interconnecting structure of each of the wafers to be vertically assembled.

[0022] The scientific article by Kim et al., "Multi-Stack Wafer Bonding Demonstration Utilizing Cu to Cu Hybrid Bonding and TSV Enabling Diverse 3D Integration," IEEE 71st Electronic Components and Technology Conference (ECTC) - 2021, discloses an integration by vertical stacking of three wafers with, in this order: a bottom wafer, an intermediate wafer, and a top wafer. Unlike what is described for the bond between the intermediate and bottom wafers, the bond between the top and intermediate wafers is achieved without a via, in the usual sense of the term.In other words, neither in the interconnection structure of the upper plate nor in that of the intermediate plate intended to be interconnected with said upper plate, is there a via between metallic connecting pads made in these interconnection structures on one side, and elements (active or passive) made in lower metallization levels of the plate in question on the other. The connecting pads of the intermediate and upper plates disclosed in this document are all electrical connection pads between said intermediate and upper plates, i.e., functional connecting pads, and are also used as bonding pads.In fact, everything happens as if the connecting pads all had the function of electrical connection pads (that is to say the basic function of a via, in reality, but at the interface between the two stacked plates), being . brought into electrical contact two by two by the effect of vertical bonding between the two plates.

[0023] However, this integration is not compatible with design rules such as those imposed by the CMP for hybrid bonding applications, as presented above. In particular, the Kim et al. 2021 document does not address the issue of the bonding step size in the integration under consideration. For example, it does not disclose that the bonding pads should be present in a minimum number per unit area and / or should adhere to a specific layout topology (i.e., a spatial distribution) on the upper surface of the semiconductor devices corresponding to the top and middle plates. Thus, the bonding support function provided by the vias, as disclosed in this document, does not appear to be linked to specific morphological considerations related to bonding pad layout constraints. On the contrary, the Kim et al. 2021 document...The 2021 standard simply teaches the use of vias, which are primarily intended for electrical connections between wafers, as hybrid bonding supports, thus making them functional bonding pads. However, nothing in the document suggests the existence of non-functional bonding pads. Yet, it appears that the type of integration described is not viable for fine bonding pitches (i.e., on the order of 5 pm) or even standard ones (e.g., up to 10 pm). Indeed, for microstructures with high interconnection density, bonding pads cannot, in practice, be limited to functional bonding pads whose number, location, and distribution are dictated solely by the routing plan, without addressing the DRM requirements related to the interconnection density between wafers.

[0024] Therefore, this type of integration, lacking a layer of the interconnect structure dedicated to forming connecting vias that are not also electrical connection pads (i.e., vertical integration without "dummies" pads), is only feasible if only pads already designed to perform an electrical connection function in the 3D microstructure can be used for hybrid bonding. In practice, this solution may find applications only in simple test structures (or "daisy chains"), for laboratory applications where the risk of bonding defects is acceptable. However, it is not usable for integrating a 3D microstructure for the industrial-scale fabrication of integrated circuits intended for commercial applications.In this case, the Drawing Rules Manual (DRM) mandates a minimum density and a substantially homogeneous distribution of adhesive pads, designed to ensure sufficient interconnection density to prevent bonding defects. Such density and distribution are not generally found when the adhesive pads are composed exclusively of [material not specified in the original text]. functional links planned for other reasons, namely reasons related to the routing plan of the 3D microelectronic device. Description of the invention

[0025] The invention aims to offer an alternative to the existing art described above, making it possible to do without the HBV layer while respecting the DRM requirements regarding the density and homogeneity of the distribution of bonding pads.

[0026] To this end, the invention has as its first object a three-dimensional, 3D, microelectronic structure for an integrated semiconductor product, said 3D microelectronic structure comprising a first microelectronic device fabricated on an upper wafer, and a second microelectronic device fabricated on a lower wafer to which the upper wafer is bonded by hybrid bonding after vertical inversion, wherein the lower wafer and the upper wafer each comprise a substantially planar substrate and an interconnection structure formed above said substrate, wherein: • the respective interconnection structure of each of the upper and lower plates is a vertical stack of at least two directly superimposed interconnection levels, each comprising a hybrid layer essentially composed of a dielectric material, namely, respectively: • a higher interconnection level (HBM), with metallic bonding pads formed in the dielectric material and adapted to cooperate with corresponding metallic bonding pads of the other wafer for hybrid bonding of the upper wafer to the lower wafer; and, • a horizontal interconnection level (MX) that is directly below the upper interconnection level, with horizontal metallization elements, • the respective metallic connecting pads of each of the upper and lower plates are distributed substantially homogeneously on the upper surface of the upper interconnection level of the interconnection structure of said plate, with a bonding pitch, defined as the maximum spacing between horizontally adjacent connecting pads in the plane of said upper surface, which is less than a determined associated threshold; • the respective metallic connecting pads of each of the upper and lower plates include connecting pads of a first type, which are electrically isolated from any horizontal metallization element of the horizontal interconnection level of the interconnection structure of said plate; and, • the respective metallic connecting pads of each of the upper and lower plates further include connecting pads of a second type, which are electrically coupled each to at least one underlying horizontal metallization element formed in the horizontal interconnection level of the interconnection structure of said plate.

[0027] As a person skilled in the art will have understood, the first microelectronic device formed on the upper wafer and the second microelectronic device formed on the lower wafer are assembled vertically one above the other by full-wafer hybrid bonding, via a hybrid bond at the interface between the upper layer of the respective interconnect structure of each of said upper and lower wafers.

[0028] Some preferred but not limiting aspects of the process are the following.

[0029] The horizontal interconnection level of the interconnection structure of each of the lower and upper plates may include a passivation film of electrically insulating material which covers the layer of dielectric material of said horizontal metallization level, the first type of connecting pads of each of the upper and lower plates being electrically insulated from any horizontal metallization element of the horizontal interconnection level of the interconnection structure of said plate, at least by the insulating material of the passivation film covering the layer of dielectric material of said horizontal metallization level.

[0030] The dielectric material layer of the upper interconnection level of the interconnection structure of each of the upper and lower plates may be a hybrid patterned dielectric material layer, said patterns defining: • solid areas of said dielectric material; • the first vertically filled through-zones containing metallic material and the insulating material of the horizontal interconnection layer's passivation layer, said first through-zones forming the first-type connection pads of the upper interconnection level; and, • Second vertically traversing zones, filled with metallic material, and at which the passivation layer of the horizontal interconnection level has an opening, said second traversing zones forming the second-type connection pads of the upper interconnection level, each in electrical continuity with one of the horizontal metallization elements of the horizontal interconnection level through said opening of the passivation layer.

[0031] In embodiments, the associated threshold of the gluing step is less than or equal to 10 pm, preferably on the order of 5 pm.

[0032] The dielectric material of the hybrid interconnecting layers of the interconnecting structure of each of the upper and lower platelets is, for example, Silicon Dioxide (SiO2).

[0033] The constituent material of the metallic connecting pads of the upper interconnection level and / or the constituent material of the horizontal metallizations of the horizontal interconnection level of the interconnection structure of each of the upper and lower plates, may be a metal selected from the group comprising copper (Cu), gold (Au), titanium (Ti), aluminum (Al), niobium (Nb) and platinum (Pt), or an alloy based on at least one of said metals.

[0034] In embodiments, the electrically insulating material of the passivation film of the horizontal interconnection level of the interconnection structure of each of the upper and lower plates is a Silicon Nitride (SiN) or a Silicon Carbonitride (SiCN).

[0035] The substrate of the upper wafer and / or the substrate of the lower wafer may each comprise an active zone with active elements in the upper part of said substrate, and in which: • The connecting pads of the first type of the interconnect structure of each of the upper and lower wafers are electrically isolated from the active elements of the active zone of the substrate of said wafer, whereas, • at least some of the second type of connecting pads of the interconnect structure of the upper and / or lower wafer are electrically coupled to at least one of the active elements of the active area of ​​the substrate of said wafer.

[0036] The invention also relates to a method for producing a three-dimensional, 3D microelectronic structure, according to the first aspect above, comprising the hybrid bonding of an upper wafer onto a lower wafer after vertically flipping of said upper wafer, in which the prior fabrication of the interconnection structure of each of the lower and upper wafers comprises the formation of a vertical stack of at least two interconnection levels directly superimposed above the substrate of said wafer, namely, respectively: • a horizontal interconnection level (MX), with horizontal metallization elements formed in the dielectric material of a corresponding hybrid layer; and, directly above said horizontal interconnection level (MX), • a higher interconnection level (HBM) with metallic bonding pads formed in the dielectric material of a corresponding hybrid layer, and adapted to cooperate with corresponding metallic bonding pads of the other wafer, for hybrid bonding of the upper wafer (1) to the lower wafer, and wherein: • the respective metallic bonding pads of the upper metallization level of the interconnecting structure of each of the upper and lower plates are made with a substantially homogeneous distribution on the upper surface of said upper metallization level, and with a bonding pitch, defined as the maximum spacing between horizontally adjacent bonding pads in the plane of said upper surface, which is less than a determined associated threshold; • among the respective metallic connecting pads of each of the upper and lower plates, connecting pads of a first type are each made with electrical insulation with respect to any horizontal metallization element of the horizontal interconnection level of the interconnection structure of said plate; • among the respective connecting pads of each of the upper and lower plates, in addition, connecting pads of a second type are made each in electrical continuity with at least one underlying horizontal metallization element formed in the horizontal interconnection level of the interconnection structure of said plate.

[0037] In embodiments of the method, the formation of the upper interconnection level of the interconnection structure of each of the upper and lower plates may include: • the deposition of a passivation film in electrically insulating material which covers a hybrid layer in dielectric material comprising horizontal metallization elements of the horizontal metallization level of the wafer; • the formation of a layer of dielectric material and a first photolithographic etching, to etch said layer of dielectric material with a stop on the passivation film of the horizontal metallization level in order to form patterns in said layer of dielectric material corresponding to the metallic bonding pads of the upper metallization level of the wafer; then, • a second photolithographic etching, to etch the passivation film of the horizontal metallization level in order to open said film in only a part of the patterns previously formed in the dielectric material layer which correspond to the metallic bonding pads of the second type of the upper metallization level of the wafer; then, • the filling, with metal, simultaneously of all the patterns previously formed in the layer of dielectric material, namely both the patterns corresponding to the metallic bonding pads of the first type and the patterns corresponding to the metallic bonding pads of the second type of the upper metallization level of the wafer.

[0038] The patterns in the dielectric material layer corresponding to the metallic bonding pads of the upper metallization level of the wafer can, for example, be filled with metal by electrochemical deposition.

[0039] Thus, the first-type bonding pads of each wafer are formed in the upper layer of the interconnect structure and are electrically isolated from any metallization element formed in any interconnect layer corresponding to a lower metallization level in the stack of layers forming the interconnect structure, as well as from any active element in the active zone of the lower wafer. This isolation is provided by the insulating material of the passivation layer associated with the horizontal interconnect layer of the interconnect structure that is directly below said upper layer. These first-type bonding pads are therefore non-functional pads, i.e., dummy metallizations ("dummies"), which serve only for hybrid bonding.

[0040] In contrast, the connecting pads of the second type are bonding and electrical connection pads formed in the upper layer of the interconnection structure, in electrical continuity with a metallic element of at least one other horizontal interconnection layer of the interconnection structure, which is the metallization layer directly below the upper layer. These connecting pads of the second type are therefore functional pads, serving both for the hybrid bonding of the upper plate, which is inverted vertically onto the lower plate, and for the electrical connection between the two devices thus assembled vertically.

[0041] The embodiment of the semiconductor product according to the first aspect of the invention above, and the implementation of the method according to the second aspect of the invention above, make it unnecessary to create a vertical interconnect layer with vias directly below the top layer of each of the two 2D microelectronic devices to be stacked. This embodiment can therefore be dispensed with, by having both functional and non-functional connecting pads which, together, allow the desired interconnection density to be achieved. Thus, it is possible to respect the drawing rules (DRM) to obtain good CMP performance and therefore good quality bonding of the two stacked microelectronic devices.

[0042] According to another advantage, the electrical resistance of a functional connecting pad made according to embodiments of the proposed method is significantly lower than that of vertical electrical connections made by vias according to the existing art. The reduction in interconnect resistance reduces energy dissipation by Joule effect in the operating integrated circuit, and therefore limits the temperature rise. This reduction also improves the battery life of small portable devices (such as smartphones) incorporating the integrated circuit when they are operating on battery power.

[0043] It should be noted that the electrical resistance of an interconnection is inversely proportional to the contact area between the two interconnecting elements in electrical contact with each other, all other things being equal: the larger this area, the greater the amount of current that can pass through the interconnection, and therefore the lower the electrical resistance. Now, a person skilled in the art will appreciate that: • In the case of conventional 3D integrations where the interconnections include circular cross-section vias, the current is limited by the small surface area of ​​the vias compared to that of the bonding pads. For microstructures with a bonding pitch, for example, of 5 pm, the diameter of the circular cross-section of a via can be 0.5 pm, so that the cumulative surface area of ​​the four vias made for a given bonding pad is equal to 4 x 3.14 x (0.25)², or 0.785 pm²; whereas, • In the case of an interconnection achieved by implementing the method according to the invention, the total surface area of ​​the pads (considering optimal alignment between the respective pads of the two 2D microelectronic devices) constitutes the electrical connection surface for the passage of electrons. The square cross-sectional contact area can then be equal to 2.5 x 2.5 µm, or 6.25 µm², which represents approximately eight times the cumulative surface area of ​​four vias conforming to a conventional solution, thus allowing for a current flow that can be eight times higher. Even in the case of misalignment, for example with a 50% misalignment, the gain in contact area represents a factor of four, meaning that the contact resistance of an electrical connection element is reduced by at least four times compared to existing art.

[0044] Furthermore, since the connecting pads are directly connected to the metal lines of the horizontal interconnecting layer, which is directly below the upper layer of the interconnecting structure, the formation of Passivation layers of titanium nitride (TiN), which are conventionally used in prior art designs, have the disadvantage of being more resistive than the metal. For this reason as well, the interconnection resistance is improved (it is lower) thanks to the implementation of the invention.

[0045] According to yet another advantage, the thickness of each of the pads can be less than in prior art microstructures, since there is no need for an HBV-level interconnecting layer to create vias connecting the functional bonding pads. Each pad is therefore subjected to less mechanical stress, which provides better bonding conditions between the two pads. Consequently, the risk of bonding defects is also reduced.

[0046] Overall, and as will be explained in the detailed description of the process implementation methods, the proposed manufacturing process saves nine technological manufacturing steps compared to existing state-of-the-art processes. The environmental and economic impact, as well as the time savings compared to known processes, are therefore considerable. In particular, the shorter cycle time results in fewer water refills and thus a reduced risk of outgassing during annealing. Furthermore, two fewer annealing cycles are required, leading to a reduction in the overall thermal budget. Brief description of the drawings

[0047] Other aspects, objects, advantages, and features of the invention will become clearer upon reading the following detailed description of preferred embodiments thereof. This description is given by way of non-limiting example. It is made with reference to the accompanying drawings, in which:

[0048] [Fig.1A] is a vertical cross-sectional view of an example of a 2D microelectronic device, adapted for the realization of a 3D microstructure by hybrid bonding with another similar device, according to the existing art;

[0049] [Fig.1B] is a schematic representation illustrating the principle of hybrid bonding, of type W2W, of two 2D microelectronic devices like that shown in [Fig.1A], to arrive at a 3D microstructure;

[0050] [Fig.1C] is a vertical cross-sectional view of the 3D microstructure obtained by the vertical assembly of two 2D microstructures such as that shown in [Fig.1A] by hybrid bonding as illustrated by [Fig.1B], in accordance with the prior art;

[0051] [Fig.1D] is a top view of an example of a 3D microelectronic device according to the prior art, similar to that shown in section in [Fig.1C];

[0052] [Fig.2] is a vertical cross-sectional view of an example of a microstructure according to the second object of the invention;

[0053] Figures [Fig.3A] to [Fig.31] are vertical cross-sectional views of an example of a 2D microelectronic device at various stages of its realization according to a process conforming to implementations of the first aspect of the invention, to allow the realization of the 3D microstructure of [Fig.2] by the vertical assembly of two such identical or similar 2D microelectronic devices;

[0054] [Fig. 4] is a step diagram illustrating groups of steps of the process according to implementations of the process according to the first aspect of the invention, and steps of a process according to the prior art; and,

[0055] [Fig.5] gives a comparison table, by matching, of the steps of a process according to the prior art and the steps of the process according to implementations of the first aspect of the invention, respectively. DETAILED DESCRIPTION OF IMPLEMENTATION METHODS

[0056] In the figures and throughout the description, the same numerical references designate identical or similar elements. Furthermore, the various elements are not drawn to scale, in order to enhance the clarity of the figures. Moreover, the different embodiments and variants presented are not mutually exclusive and may be combined.

[0057] In what follows, the terms "approximately", "around", and "in the order of" mean to the nearest 10%, and preferably to the nearest 5%. Furthermore, the expressions "between A and B", and equivalent expressions mean that the bounds A and B are inclusive, unless explicitly stated otherwise.

[0058] By the expression "formed from", used in reference to a material and an element of interest, it is understood that the material is a compound formed from a plurality of elements of which at least the said element of interest is included.

[0059] The expression "material comprising predominantly" an element of interest means a material of which at least 50% by volume is formed by, or comprises, said element of interest.

[0060] The term "wafer" is an English term that designates a very thin plate (also called a "wafer" due to its small thickness) of single-crystal semiconductor material, on which microelectronic devices can be fabricated. Wafers are thus used to manufacture microelectronic devices. Wafers are made of a doped semiconductor material, such as silicon (Si), gallium arsenide (GaAs), or indium phosphide (InP). Wafers generally have dimensions ranging from 25.4 mm (1" technology) to 300 mm (12" technology), with a thickness of approximately 0.7 mm. Wafers are used in the microelectronics industry as a substrate for manufacturing microstructures. This fabrication employs design techniques such as, for example, and without limitation: doping, etching, and the deposition of other materials. materials and photolithography. The doped semiconductor material of which the wafer is made therefore serves as a substrate for the creation of the microstructures forming the active microelectronic devices which are part of the composition of integrated circuits, transistors, power semiconductor products, MEMS or NENS, etc.

[0061] In the manufacture of an integrated circuit, the FE (Front End) phase refers to all the technological manufacturing steps of the circuit before it is packaged. The FE includes the FEOL (Front End Of The Line) phase as well as the BEOL (Back End Of The Line) phase. The FEOL refers to the first phase, in which all the manufacturing steps of the active components (transistors), for example in CMOS technology, are carried out, in the active area of ​​the wafer up to (but not including) the first level of metallization of the interconnect structure placed on top.BEOL refers to the second phase of integrated circuit fabrication, which begins with the first layer of metallization. This layer stack forms the interconnect structure, through which the active components in the active area of ​​the wafer are interconnected according to a routing plan that ensures the wiring of the active components on the wafer. In this second phase, individual microelectronic devices forming the passive components (capacitors, inductors, resistors, etc.) can also be fabricated at different metallization levels of the interconnect structure. The metals commonly used are copper (Cu) and aluminum (Al). BEOL begins when the first metal layer is deposited on the wafer.By extension, BEOL sometimes refers to the interconnect structure which includes the insulating (dielectric) layers, the metal traces (horizontal electrical connections), the vias (vertical electrical connections between the traces), and the bonding sites for the connections between the chip and the package of the integrated circuit.

[0062] The term "chemical-mechanical polishing" or CMP (from the English "Chemical-Mechanical Polishing"), already used in the introduction, refers to a surface smoothing process of a wafer using the combined action of mechanical and chemical forces, resulting in the removal of the material(s) on the surface of the wafer and the erasure of any surface topography, with the result of the planarization of the surface of the wafer exposed to this process.

[0063] The "Damascene process" is a technique for forming metallic elements (also called "metallizations") in copper, which consists of etching trenches and via holes in a layer of dielectric material, then filling the trenches and via holes with copper to form conductive tracks and vias, respectively, and finally to flatten the copper using chemical mechanopolishing (CMP).

[0064] The "annealing" of a material is an operation corresponding to a heating cycle, consisting of a step of gradually increasing the temperature to temperatures ranging from approximately 250°C to 450°C, followed by controlled cooling. Annealing allows the physical characteristics of the material subjected to this heat treatment to be modified.

[0065] Electrochemical deposition (ECD) is a deposition technique used for the rapid filling of trenches or via boreholes with a metal such as copper. Its operating principle is as follows: the wafer is configured as a negative electrode (cathode) and is immersed in an electrolyte, i.e., an electrolytic solution containing metallic salts. Copper is deposited from an anode, i.e., a positive counter-electrode, made of copper. To do this, the metal ions in the anode are reduced by applying a potential difference between the anode and the cathode. For the reaction to occur homogeneously over all desired portions of the wafer surface, these portions must be conductive.In other words, it is therefore necessary that the resistivity of the bonding layer on the targeted portions of the wafer be as low as possible.

[0066] The term "photoresist" refers to a material, more particularly a polymer resin, which is sensitive to light and is used to form a pattern on the substrate, using an optical mask made up of opaque and transparent areas which define the pattern that one wishes to reproduce on the wafer through which the photoresist is illuminated and has its properties modified at the level of the transparent areas of the optical filter.Thus, for example, a "positive" photoresist is a light-sensitive polymer which, when exposed to ultraviolet (UV) light, transforms into a soluble material: the areas exposed to this illumination can then be dissolved using a solvent, leaving behind a layer with a recessed pattern which can be used as a mask for the formation of a structure through the mask thus formed, for example by etching an underlying material which is selective to the mask material, by ion implantation, or by deposition of a new material in the areas exposed by the mask.

[0067] Finally, a three-dimensional orthogonal direct frame (X,Y,Z) is defined here and for the remainder of the description, where the X and Y axes form a plane parallel to the principal plane of the "handle" plate under consideration, and where the Z axis is oriented substantially orthogonally to the principal plane of said plate, this Z axis being oriented along the direction of gravity. In the remainder of the description, the terms "vertical" and "vertically" are understood as relating to an orientation substantially parallel to the Z axis, and the terms "horizontally" and "horizontally" as relating to to an orientation substantially parallel to the (X,Y) plane. Furthermore, the terms "above" and "below" and their derivatives (such as "above" and "below", or "over" and "underneath"), as well as the terms "lower" and "upper", used to qualify an element of the microstructure considered, are understood as being relative to an increasing positioning when moving away from the wafer upwards, i.e., along the vertical +Z direction.

[0068] The terms "rear" and "front," on the other hand, are used with reference to the face of a wafer through which the various treatments are, or have been, carried out to produce the microstructure in question. Since these treatments are systematically carried out from above when the wafer is placed flat in a chamber used to perform the treatment, the "front" face is generally (and by default) the upper face of the wafer. However, when a wafer or a chip cut from a wafer is turned vertically, its front face becomes the lower face and its rear face becomes the upper face.The term "rear" applied to the semiconductor substrate of an individual wafer or chip is also used in reference to this convention, in the sense that it designates the part of the substrate that is furthest from the face of said wafer or chip where treatments have been carried out in the substrate, and which is always referred to as the rear face even if the wafer or chip has been turned vertically so that this face is now on top and facing upwards.

[0069] By "layer", we mean an extent of a material whose thickness along the Z axis is less, for example ten times or even twenty times, than its longitudinal dimensions of width and length in the XY plane.

[0070] By "plot" is meant a volume of a crystalline material, for example based on a specific metal such as copper or aluminum, whose thickness along the Z-axis is substantially equal to its longitudinal dimensions of width and length in the XY plane, and whose longitudinal dimensions are less than or equal to the thickness along the Z-axis of a layer in which it is formed. The shape of the plot, in a horizontal cross-section (parallel to the XY plane), may be polygonal (for example, a square or a rectangle), or curved (for example, a circle or an ellipse).

[0071] Specific embodiments will be described with reference to the non-limiting example of application to the fabrication of a 3D microelectronic structure intended for the manufacture of an integrated semiconductor product, for example, using CMOS technology. The embodiments of this 3D microstructure and the implementation methods of the process described can be adapted to the specific characteristics of each application concerned, without departing from the principles of the invention.

[0072] We will first describe, with reference to the diagrams in [Fig.1A] to [Fig.1D], the principle of 3D assembly by hybrid bonding according to the prior art.

[0073] Direct bonding can be used in 3D integration. Two dielectric materials are bonded together to assemble two separate wafers. However, only a mechanical bond is established, and there is no electrical continuity at the bond interface. Electrical connections between the upper and lower wafers can be restored after bonding by forming through-vias (TSVs), which are high aspect ratio vias that span the SiO2 and / or Si layers from one side of the bond interface to the other. This technique offers only a low interconnection density between the wafers. Furthermore, its implementation is relatively lengthy and complex, as the TSV fabrication process involves many etching and deposition steps.

[0074] Hybrid bonding constitutes another approach that is also well known, in itself, to the person skilled in the art. According to this approach, two wafers are treated separately, following a classic integration process until the last of the standard metallization levels of their respective interconnection structure is achieved, namely the n stacked metallization levels also called levels M1, M2, ..., Mn. After this step, a penultimate metallization level called the "hybrid bonding via level" (or HBV level, from the English "Hybrid Bonding Vias"), as well as a final (Le., last) metallization level called the "hybrid bonding metallization level" (or HBM level, from the English "Hybrid Bonding Metal"), are added vertically to the interconnection structure of each of the wafers, by continuing the Damascus process after the n underlying metallization levels (or levels M1, M2, ..., Mn) have been achieved.The HBM level constitutes the bonding layer of the wafer for hybrid bonding with the other wafer, and contains bonding pads for this purpose. The HBV level, which is directly below the HBM level, contains exclusively vertical metallizations for the electrical connection of some of the HMB level's bonding pads with lower metallization levels M1, M2, ..., Mn. The difference from the direct bonding mentioned above is the presence of copper bonding pads in the respective bonding layers of the two wafers, with a high density. The dielectric material in these layers is SiO2 deposited by chemical vapor deposition (PECVD). The very high density of bonding pads present in this SiO2 layer offers numerous advantages, not only in terms of electrical connection between the two wafers once assembled by hybrid bonding, but also in terms of the quality of the bond obtained.

[0075] With reference to [Fig. 1A], a first microelectronic device 100 according to the existing art, for example a CMOS device, comprises a substrate 101. The substrate 101 is, for example, a silicon substrate. On top of the substrate 101, the device 100 comprises a layer 102 of electrically insulating (dielectric) material, such as silicon dioxide (SiO2). The layer 102 is itself covered by a passivation layer 103, for example a Silicon Nitride (SiN) layer.

[0076] The microelectronic device 100 includes an active area (not shown) in the upper part of the substrate 101, directly below the insulating layer 102. This active area may include active components, such as transistors, photonic devices such as photodiodes, etc. Such components, where appropriate, are fabricated using, for example, the manufacturing technological steps that are the classic steps of CMOS microelectronics, in order to fabricate an integrated circuit for a specific application. This phase of circuit fabrication (or FEOL phase) will not be addressed in this description, as the invention is implemented during the subsequent BEOL phase, namely the phase of fabricating the interconnect structure. This interconnect structure will now be described, again with reference to [Fig. 1A].

[0077] The microelectronic device 100 comprises an interconnection structure formed by a stack of n layers, each corresponding to a respective metallization level, where n is an integer strictly greater than one. These n interconnection layers are essentially made of an electrically insulating (dielectric) material, such as silicon dioxide (SiO2). They contain metallic elements, namely conductive tracks or vias. These metallic elements (also called "metallizations" for short) are produced by depositing metal into trenches or via holes, respectively, previously formed by any suitable process, in the dielectric material of the corresponding interconnection layer. The trenches and via holes are generally formed by photolithographic etching and then filled with metal.The metal in question is usually copper (Cu), but it could also be another metal, such as aluminum (Al). The layers of the interconnect structure correspond to respective metallization levels, commonly designated by the acronyms M1, M2, ..., Mn in the relevant literature. There is an alternation of horizontal metallization levels, comprising conductive tracks created by depositing metal in trenches formed in the dielectric material of the corresponding layer, and vertical metallization levels, comprising vias created by depositing metal in via holes formed in the dielectric material of the corresponding layer.The vias of a vertical metallization level are arranged to couple conductive tracks of one metallization level above (if applicable) with conductive tracks of one metallization level below and / or with active elements of the active zone of substrate 101.

[0078] In the example of [Fig.1A], n is equal to three (n=3): the interconnection structure comprises three layers 104, 107 and 110 stacked vertically, in that order, above the insulating layer 102 with which the substrate 101 is coated. They are formed successively above the substrate 101, one after the other, starting with the lowest layer and ending with the highest layer. In this example, layer 104 is the lower layer of the interconnection structure, or lowest layer, i.e. also the one that is closest to the substrate 101. It corresponds to the first level of metallization, denoted MX in the figure and thereafter, which is formed directly above the substrate 101. On the opposite side along the vertical direction Z, layer 110 is the upper layer of the interconnection structure, or highest layer, i.e. also the one that is furthest from the substrate 101.It corresponds to the final metallization level, which, in the context of this description, is designated by the acronym HBM (for "Hybrid Bonding Metal"). Finally, layer 107 is the penultimate layer of the interconnecting structure, formed directly below the upper layer 110 with which it cooperates directly from a functional point of view, and is designated by the acronym HBV (for "Hybrid Bonding Vias") in the context of this description. The function of these three interconnecting layers, i.e., metallization levels MX, HBM, and HBV, is detailed below.

[0079] In the example shown in [Fig. 1A], the first interconnecting layer 104 of the interconnecting structure, i.e., the one closest to the substrate 101, corresponds to a horizontal metallization level MX. In the example shown, this metallization level MX comprises a conductive track 105 formed in a trench, i.e., a through-cut formed in the dielectric material, which here extends along the longitudinal direction X. Where applicable, this conductive track 105 can be electrically connected to one or more active components made in the active zone of the substrate 101 of the device 100. More generally, the horizontal metallizations formed in the metallization level MX of the first layer 104 serve to connect elements of the active components made in the active zone of the substrate 101. To this end, they are coupled to them by vias (not shown).These vias pass through the insulating layer 102 which is directly below the layer 104 as well as the passivation layer 103 which separates the two dielectric material layers 102 and 104.

[0080] The last layer 110 of the interconnection structure shown in [Fig.IA], which corresponds to the HBM metallization level, includes metallic bonding pads whose function is to ensure the hybrid bonding of the wafer 100 with another wafer 200. More specifically, it includes bonding pads of a first type 111a, as well as bonding pads of a second type 111b. All these pads are used to connect the microelectronic device corresponding to wafer 100 to another microelectronic device corresponding to wafer 200 via hybrid bonding. Structurally, these two types of pads are identical, and they are made of the same metal, namely copper in this example, and manufactured using the same Damascus process. The difference between these two types of pads is purely functional.

[0081] Indeed, on the one hand, the connecting pads 11a of the first type serve only, i.e., exclusively as a support for the hybrid bonding of the wafer 100 onto the other wafer 200, as shown in [Fig.1B], in cooperation with corresponding connecting pads 21a of said other wafer 200. As a result, the connecting pads 111a of the first type will also be called "bonding pads only" in the following, or even "non-functional pads" because they play no role in the operational functioning of the integrated circuit.

[0082] On the other hand, the connecting pads 111b of the second type serve not only for gluing the two plates 100 and 200 together, like the gluing pads 11a only, but they also serve for electrical connection between said plates, in cooperation with corresponding pads 211b of the other plate 200. In what follows, the connecting pads 111b of the second type are called "gluing and electrical connection pads", or "functional pads" because they play a role in the operational functioning of the integrated circuit by ensuring the passage of electrical signals from one plate to the other.

[0083] Finally, the penultimate layer 107 of the interconnection structure of [Fig.1A], that is to say the interconnection layer directly below the upper interconnection layer 110, which corresponds to the metallization level HBV, includes vias 108. These vias 108 are vertical metallization elements adapted to achieve electrical coupling between a functional connecting pad of the metallization level HBM in the upper interconnection layer 110, on the one hand, and a metallization element of the metallization level MX in the lower interconnection layer 104, on the other hand.

[0084] In the example shown in [Fig. 1C], such vias 108 are made in electrical continuity with the bonding and electrical connection pads 111b of the wafer 100 of the HBM metallization level formed directly above the HBV metallization level, and also in electrical continuity with the conductive track 105 in the MX metallization level below the HBV metallization level. The vias 108 function to electrically connect the metallization elements to which they are respectively coupled, i.e., with which they are in electrical continuity. Where appropriate, such vias 108 can ensure the electrical continuity of the second-type connecting pads 111b directly with metallization elements distributed in metallization layers even lower than layer 104 of [Fig.1A] in the stack of the n interconnecting layers, and even directly with active elements made in the active zone of the substrate 101. These vias 108 can cross one (or more) intermediate layer(s) of silicon dioxide (SiO2) based dielectric material before reaching a horizontal metallization in an interconnecting layer corresponding to a horizontal metallization level located lower in the stack, or an active element of the active zone of the substrate 101.

[0085] A person skilled in the art will appreciate that several horizontal metallization levels, such as the MX metallization level, can be formed in respective interconnecting layers that are stacked before forming the penultimate layer 107 and the last layer 110 of the interconnecting structure, which correspond to the HBV and HBM levels, respectively. Where appropriate, the horizontal metallizations formed in these respective interconnecting layers can be linked together by vertical metallizations, i.e., by vias that are made in dedicated interconnecting layers corresponding to respective vertical metallization levels, intercalated between the corresponding horizontal interconnecting layers.

[0086] Figure [1B] symbolically illustrates the hybrid bonding of plate 100 from Figure [1A] onto the other plate 200. This could be a plate-level hybrid bond, i.e., a W2W type bond, but it could also be a D2W type hybrid bond or even a D2D type hybrid bond. Figure [1C] illustrates the 3D microstructure obtained by this vertical assembly. As symbolically represented by an arrow, the upper plate 100 is turned vertically and is set in the horizontal plane XY (that is, it is aligned both along the longitudinal direction X and along the transverse direction Y) with respect to the lower plate 200. This result is obtained by referencing its connecting pads 111a of the first type as well as its connecting pads of the second type 111b, with the corresponding connecting pads of the lower plate 200.This operation is carried out using methods and equipment known to those skilled in the art, and whose detailed description would be beyond the scope of this description. The bonding of the upper plate 100 to the lower plate 200, as shown in [Fig. 1B], is achieved by the effect of Van der Waals forces, covalent bonds and hydrogen bonds formed during contact, due to the particularly smooth and flat surface of the respective upper faces of the plates 100 and 200.

[0087] Figure [1D] is a top view of a 3D microstructure obtained by a vertical integration method according to the existing art, which has been presented above. This The microstructure may correspond to the microstructure shown in [Fig. 1C], or to any structurally comparable microstructure. With reference to [Fig. 1D], we distinguish: • metallic lines 205 which are made in the metallization level MX of the interconnection structure of the lower plate 200; • a metallic line 105, shown here in slight transparency to reveal what is underneath, and which is made in the metallization level MX of the interconnection structure of the upper plate 100; • the connecting pads 11la and 111b of the upper plate 100, which include adhesive pads only or pads of the first type 111a, as well as adhesive pads and electrical connection pads or pads of the second type 111b (which are surrounded by dotted circles in the figure, in order to better distinguish them). These connecting pads 11la and 111b coincide spatially, in the horizontal XY plane, with the corresponding connecting pads of the lower plate 200 in the top view of [Fig.1D], assuming a perfect horizontal alignment between the two plates 100 and 200. In other words, the connecting pads 11la and 111b of the upper plate 100 are perfectly aligned along the X direction as well as along the Y direction with the corresponding connecting pads 211a and 221b (see [Fig.1C]) of the lower plate 200.Consequently, they obscure these in an observation direction along the vertical Z direction, from top to bottom. The connecting pads 21la and 221b (see [Fig.lC]) of the lower plate 200 are therefore not visible in [Fig.lD]. • The vias 108, which are produced in the HBV metallization level of the interconnecting structure of the upper plate 100, are represented by small squares in the bonding and connection pads 111b. Here too, and still assuming perfect horizontal alignment between the two plates 100 and 200, the vias 108 of the upper plate 100 obscure the corresponding vias 208 of the lower plate 200. In the example shown, there are four square-section vias to connect a pair of connection pads 108 and 208, in order to allow the passage of four times the current that would be carried by a single via of the same cross-section. The number and cross-sectional shape of the vias can vary from one application to another. For example, rectangular, circular, or elliptical cross-section vias may be preferred. A number of vias less than four, for example a single via with a relatively larger cross-section, can also be envisaged. instead of the four vias of relatively smaller cross-section which are represented in the example in [Fig.1D].

[0088] In [Fig. 1D], the bond pitch, defined as the center-to-center spacing between two adjacent bonding pads (whether of the first type 111a or the second type 111b), both along the X and Y directions, is denoted by the letter "P". As can be seen in the figure, which represents an embodiment according to the prior art, but as is also the case for an embodiment implementing the invention, the bonding pads 111a and 111b are present with a relatively high density, resulting in a bond pitch P that is less than a predetermined threshold. This threshold is equal to or less than 10 micrometers (pm), for example, approximately 5 pm. Furthermore, their distribution on the surface of the wafer 100 is substantially uniform, for the reasons already mentioned above.These constraints are usually specified in the applicable DRM, to which the designer of the relevant electronic circuit can refer.

[0089] An example of implementing the method for fabricating a 3D microstructure by vertical integration of two separate wafers 1 and 2 according to the invention will now be described with reference to the step diagram in [Fig. 4]. Implementing the method makes it possible to fabricate the example of a 3D microstructure shown in [Fig. 2], comprising the upper wafer 1 inverted and bonded to the lower wafer 2. In this description, reference will also be made to the cross-sectional views in [Fig. 3A] to [Fig. 31]. These latter figures show one of the wafers during fabrication, in this case the upper wafer 1, after the implementation of specific steps or groups of steps of the method for said wafer 1 individually, before the hybrid bonding of the two wafers 1 and 2.It should be noted that, in the highly simplified example considered here, the fabrication of the lower plate 2 of the 3D microstructure is identical or comparable to that of the upper plate 1, which will therefore be the only one described here in order to avoid unnecessarily lengthening this description. Furthermore, and again for the sake of simplification, the respective metallization structures of the upper plate 1 and the lower plate 2 shown are structurally identical. This is, however, only a non-limiting example.

[0090] Fig. 2 shows the 3D microstructure resulting from the hybrid bonding of the wafer 1 having an original interconnection structure obtained by implementing the process according to the second aspect of the invention, on another wafer 2 (or lower wafer) having an interconnection structure obtained in a similar way.

[0091] The 3D microstructure of [Fig. 2] contains a first microelectronic device fabricated on an upper wafer 1, and a second microelectronic device fabricated on a lower wafer 2 on which the upper wafer 1 is bonded by hybrid bonding after vertical inversion. The lower plate 2 and the upper plate 1 each comprise a substantially planar substrate, respectively 11 and 21, as well as an interconnection structure formed above said substrate.

[0092] The respective interconnection structure of each of the upper plate 1 and lower plate 2 is a vertical stack of at least two superimposed interconnection levels, each comprising a hybrid layer essentially composed of a dielectric material, namely, respectively: • a higher interconnection level (HBM), with metallic bonding pads 17b and 17c, formed in the dielectric material and adapted to cooperate with corresponding metallic bonding pads 27b and 27c, respectively, of the other wafer 2 for the hybrid bonding of the upper wafer 1 onto the lower wafer 2; and, • a horizontal interconnection level (MX) which is directly below the upper interconnection level HBM, with horizontal metallization elements 15 and 25.

[0093] The adverb "essentially" used above with reference to the composition of the hybrid layer of each of the HBM and MX levels should be understood to mean that one and / or the other of these levels may further include, for example, a passivation layer intended to passivate the dielectric material that forms part of the composition of said level. Furthermore, the expression "directly below" used above with respect to the horizontal interconnection level MX should be understood to mean that there is no other interconnection level between the HBM level and said MX level, and therefore no vertical interconnection level. In other words, those skilled in the art will understand that this means that the first metallization level (here, the MX level) that comes below the hybrid bonding level HBM in the stack of interconnection levels is a horizontal metallization level and not a vertical metallization level.However, this does not preclude the horizontal interconnection level MX from including, above said level and therefore below the metallization level HBM, a passivation layer, for example a Silicon Nitride (SiN) layer, as will be explained later. In other words, this does not imply that all dielectric and / or metallic portions of the HBM level are in direct contact with dielectric and / or metallic portions of the MX level.

[0094] The metallic connecting pads 17b, 17c and 27b, 27c of each of the upper plate 1 and lower plate 2, respectively, are distributed substantially homogeneously on the upper surface of the upper interconnection level HBM of the interconnection structure of said plate. They are also made with a pitch The bonding spacing, defined as the maximum spacing between horizontally adjacent bonding pads in the plane of said upper surface, is less than a predetermined threshold. This threshold may be less than or equal to 10 pm, providing a high density of interconnection between the two plates 1 and 2 via the bonding pads. Preferably, it may be on the order of 5 pm, for example.

[0095] The respective metallic connecting pads 17b, 17c and 27b,27c of each of the upper 1 and lower 2 plates comprise connecting pads 17b and 27b of a first type, respectively, which are electrically isolated from any horizontal metallization element such as the metallizations 15 and 25, respectively, of the horizontal interconnection level MX of the interconnection structure of said plate. Furthermore, the respective metallic connecting pads 17b, 17c and 27b,27c of each of the upper 1 and lower 2 plates further comprise connecting pads 17c and 27c of a second type, respectively, which are each electrically coupled to at least one underlying horizontal metallization element formed in the horizontal metallization level MX of the interconnection structure of said plate.

[0096] In other words, the interconnection structure of each of the upper plates Plates 1 and 2 of the microstructure in [Fig. 2] do not include a vertical metallization level directly below the HBM level, unlike the 3D microstructure in [Fig. 1D] conforming to the existing art, which was described above and which had such a vertical metallization level, namely the HBV level. Instead, the second-type connecting pads 17c or 27c, respectively, of the HBM metallization level of the interconnecting structure of each of plates 1 and 2, ensure the electrical connection of said plate to the other plate. This eliminates one metallization level in each of plates 1 and 2, and therefore two metallization levels for the 3D microstructure formed by these two stacked plates. For each of these levels, a layer of insulating material (e.g., SiO2) and its associated passivation layer (e.g., SiN) are thus avoided.This reduces the stress level of the 3D microstructure, as this depends on the number of layers in the interconnecting structures of the wafers. Naturally, this also reduces the costs and budgets for thermal, water, etc., for the fabrication of the individual 2D semiconductor devices, each of which is fabricated on one of the wafers 1 and 2.

[0097] In some embodiments, the horizontal interconnection level MX of the interconnection structure of each of the lower plate 1 and upper plate 2 comprises a passivation film 16 or 26, respectively, made of electrically insulating material, which covers the dielectric material layer of said horizontal metallization level MX. The first-type connecting pads 17b and 27b of each of the upper plate 1 and lower plate 2, respectively, are then electrically isolated from any horizontal metallization element of the interconnection level. horizontal MX located below in the interconnection structure of said wafer, at least by the insulating material of this passivation film 16 or 26 covering the layer of dielectric material of said horizontal metallization level MX.

[0098] In embodiments, the dielectric material layer 17 or 27 of the upper interconnection level HBM of the interconnection structure of each of the wafers 1 and 2, respectively, is a hybrid patterned dielectric material layer, said patterns defining: • areas 17a or 27a filled with said dielectric material, i.e. areas of layer 17 or 27 which have not been etched; • the first vertically through holes 17b or 27b, filled with metallic material and at which the insulating material of the passivation layer of the horizontal interconnect level MX is present. These first through holes, once filled with metal, form the first type of bonding pads (also designated by references 17b and 27b in what follows) of the upper interconnect level HBM of the wafer; and, • the second vertically through holes 17c or 27c, filled with metallic material, and at which the passivation layer 16 or 26 of the horizontal interconnect level MX has an opening because the Silicon Nitride (SiN) of said passivation layer 16 or 26, respectively, has been removed there by etching.These second through holes, once filled with metal, form the second type of bonding pads (also designated by references 17c and 27c hereafter) of the upper HBM interconnect level of the wafer. They are each in electrical continuity with one of the horizontal metallization elements 15 or 25 of the horizontal MX interconnect level of the wafer 1 or 2, respectively, through the opening in the passivation layer 16 or 26, respectively, of said horizontal MX interconnect level.

[0099] As those skilled in the art will understand, it is therefore the passivation layer 16 of the metallization level MX which, depending on the openings made or not in said layer, and more specifically at the holes 17c and 17b made in the layer 17 corresponding to the upper metallization level HBM to receive the metal of the functional connecting pads 17c or the non-functional connecting pads 17b, respectively, makes it possible to differentiate the function of said functional connecting pads 17c from that of the non-functional connecting pads 17b. Indeed, the Silicon Nitride (SiN) of the passivation layer, when it is still present, prevents electrical continuity between the relevant connecting pad of the metallization level HBM and any metallization element in the horizontal metallization level MX directly below said level HBM.

[0100] In embodiments, the dielectric material of the hybrid interconnecting layers of the interconnecting structure of each of the upper plate 1 and lower plate 2 is Silicon Dioxide (SiO2). The constituent material of the metallic bonding pads 17b, 17c and 27b,27c of the upper interconnecting level HBM and / or the constituent material of the horizontal metallizations 15 and 25 of the horizontal interconnecting level MX of the interconnecting structure of the plate 1 and 2, respectively, may be copper (Cu) or a copper-based alloy. Finally, the electrically insulating material of the passivation film 16 or 26 of the horizontal interconnection level (MX) of the interconnection structure of each of the wafers 1 and 2 can be a nitride, such as silicon nitride (SiN) or another dielectric, for example a carbon derivative of a nitride such as silicon carbonitride (SiCN).

[0101] Thus, after the vertical rotation and bonding of plate 1 to plate 2, forming the microstructure shown in [Fig. 2], the bonding interface 60 is a hybrid interface. Indeed, it comprises: • a SiO2 / SiO2 interface at the level of zones 17a and 27a opposite each other; and, • a Cu / Cu interface at the level of the non-functional bonding pads 17b and 27b opposite, as well as at the level of the functional bonding pads 17c and 27c opposite.

[0102] The substrate 11 of the upper plate 1 and / or the substrate 21 of the lower plate 2 may each comprise an active zone with active elements in the upper part of said substrate. In this case: • the non-functional connecting pads 17b and 27b of the interconnect structure of each of the wafers 1 and 2 are electrically isolated from the active elements of the active area of ​​the substrate 11 or 21, respectively, of said wafer; whereas, • at least some of the functional bonding pads 17c and 27c of the interconnect structure of the upper wafer 1 and / or the lower wafer 2 are electrically coupled to at least one of the active elements of the active area of ​​the substrate 11 or 21, respectively, of said wafer.

[0103] Methods of implementing a process for realizing the 3D microstructure of [Fig. 2], which was presented above, will now be described. This process comprises fifteen essential technological steps, which will be referred to hereafter as numbers 1 to 15. The grouping of some of these steps into some of the step blocks of the step diagram in [Fig. 4] is solely for the purpose of simplifying the following description. In particular, the figures representing the microstructure during realization are limited to the representation of the platelet at the end of each of the groups of steps considered, where a representation Providing separate explanations at the end of each group stage would not add anything to the clarity of the presentation.

[0104] As mentioned in the introduction, the process is essentially implemented during the BEOL phase of manufacturing each individual wafer, which are then vertically joined to one another by hybrid bonding. More specifically, the process offers an alternative to manufacturing the penultimate and final layers of the interconnect structure, which correspond to the HBV (vertical interconnect) and HBM metallization levels, respectively, of a wafer according to the existing art, and which were presented above with reference to [Fig. 1A]. These two layers are replaced, according to the invention, by a single bonding layer that alone performs the respective functions of the HBV and HBM metallization levels of two wafers vertically assembled according to the existing art.It is recalled that, in interconnection structures according to the existing art, the last layer (HBM metallization level) is the one in which the bonding pads (non-functional pads and functional pads) for hybrid bonding are made, while the penultimate layer (HBV vertical metallization level) is the one in which the vias are made which vertically interconnect the functional bonding pads (and only these, i.e., not the non-functional bonding pads) with horizontal metallizations made in one or more metallization levels lower in the interconnection structure, and / or with active elements made in the active zone of the underlying substrate.

[0105] At the end of the FEOL phase of wafer 1 manufacturing, which is followed by the BEOL phase, said wafer is as shown in [Fig. 3A]. Wafer 1 comprises a substrate 11 which is coated with a layer of insulating material 12, itself covered with a passivation layer 13.

[0106] The substrate 11 is, for example, a bulk silicon substrate. In its upper part, located beneath the insulating layer 12, the substrate 11 includes active components, not shown, such as transistors or photodiodes. These components were fabricated, for example, using CMOS technology, during the FEOL phase of wafer 1 fabrication. The low resistivity of a bulk silicon substrate is advantageous for latch-up purposes of such MOS transistors. In one example, the substrate 11 is a DSP (Double Side Polished) substrate, which has the advantage of being directly usable due to the highly polished surface finish of its upper and lower faces.

[0107] The electrically insulating (dielectric) material of the insulating layer 12 can be silicon dioxide (SiO2), for example. Thin films of dioxide Silicon dioxide spontaneously develops on silicon wafers through thermal oxidation, forming a very thin layer of approximately 1 nm of native oxide. Layer 12 can then be obtained by growing a layer of silicon dioxide from this thin layer of native oxide, for example by heating the wafer to temperatures between 600 and 1200 °C in the presence of oxygen (dry oxidation) or water (wet oxidation), according to one of the following chemical reactions, respectively: • Si + O2 -> SiO2; or, • Si + 2 H2O -> SiO2 + 2 H2, Wet oxidation has a faster growth rate, but the SiO2 layer obtained is less dense than a layer obtained by dry oxidation.

[0108] The passivation layer 13 is, for example, a silicon nitride (SiN) layer. Its function is to stabilize the state of the insulating layer 102 after the formation of said layer, and to prevent contamination of the active area of ​​the substrate, in particular by diffusion of copper or water. The silicon nitride layer 13 can be deposited by low-pressure chemical vapor deposition (LPCVD) or by plasma-enhanced chemical vapor deposition (PECVD), followed by chemical treatment with phosphoric acid (H3PO4). The formation of the passivation layer 13 completes the FEOL phase of the manufacturing process. The subsequent manufacturing steps belong to the BEOL phase of said manufacturing process.

[0109] The BEOL phase of manufacturing begins with the first metallization level of the interconnect structure, which is carried out on the front (top) face of the wafer 1. With reference to [Fig. 3B], in the highly simplified example shown in that figure, the interconnect structure comprises only a single metallization level MX dedicated to the formation of horizontal metallizations in a layer 14 of dielectric material. Reference numeral 15 designates such a horizontal metallization, which is, for example, a conductive track extending in the horizontal plane XY, here along the longitudinal direction X, for example, to electrically connect active elements (not shown) made in the active layer of the underlying substrate 11.

[0110] Of course, the invention is not intended to be limited either by the number of metallization levels formed by respective interconnecting layers stacked to contain horizontal metallizations such as the metal track 15, or by the number or configuration of such tracks, or of course by their function in the electronic circuit concerned. These may include, in particular, conductive tracks for electrical connection between various active elements, but also passive elements such as inductors, capacitors, etc., made in the form of copper patterns extending into one or more corresponding metallization levels of the Interconnection structure. Where appropriate, horizontal metallizations carried out in their respective horizontal metallization levels can be electrically connected together by vertical metallizations, i.e., vias. These vias are carried out in vertical metallization levels interposed between the corresponding horizontal metallization levels.

[0111] The metallizations in the MX metallization level have an average dimension in the horizontal XY plane which is between a few tens of nanometers and a few tens of microns, for example between 20nm and 20pm, preferably between 200nm and 1Opm, and preferably even more between 800nm ​​and 5pm, for example on the order of 1pm or 2pm.

[0112] The method according to the invention includes steps for achieving the bonding of the plate 1, as an upper plate for example, with another plate 2 which is then a lower plate in this example, after vertical flipping and hybrid bonding of said upper plate 1 on said lower plate 2. By this bonding, the upper and lower plates are mechanically linked by the effect of Van der Waals forces and are at the same time electrically connected to each other, by non-functional bonding pads (bonding pads only) and by functional bonding pads (bonding and electrical connection pads), respectively.According to embodiments of the invention, the bonding structure providing this dual function comprises only one level of metallization, denoted HBM (for "Hybrid Bonding Metal"), instead of both the horizontal metallization level HBM and the vertical metallization level HBV provided for in the prior art embodiments illustrated by Figures 1A-1D described above, in which the HBV level includes the vias which provide the electrical connection of the functional bonding pads to horizontal metallizations formed in lower horizontal metallization layers.

[0113] In a first step (step 1), illustrated by block 41 of the diagram in [Fig. 4], a passivation layer 16 is formed over the corresponding layer 14, where applicable (i.e., when there are several vertically stacked metallization levels), to the highest horizontal metallization level MX, in which horizontal metallizations for interconnecting the active and / or passive components of the electronic circuit are carried out. The result of step 1 is shown in [Fig. 3C].

[0114] The passivation layer 16 is, for example, a layer of silicon nitride (SiN) or silicon carbonitride (SiCN). It stabilizes the state of the silicon dioxide (SiO2) in the metallization level MX, i.e., significantly slows its corrosion rate, that is, its natural oxidation rate, and prevents the formation It prevents scratches on the surface of the copper conductive tracks. It also protects metallizations, such as conductive track 15, from micro-scratches during handling of the wafer from one processing station to another in the cleanroom. A thin layer of silicon nitride 16 (on the order of 200 nm, for example) can be formed by chemical vapor deposition (CVD) involving gas mixtures such as Si / NH4, SiC14 / NH3, or SiH2C12 / NH3, and chemical treatment with phosphoric acid (H3PO4). The CVD deposition can be a low-pressure chemical vapor deposition (LPCVD) process that operates at relatively high temperatures (between 700 and 900°C, on the order of 775°C, for example). Alternatively, the silicon nitride passivation layer 16 can be formed by plasma-enhanced chemical vapor deposition (PECVD), which is operated at a relatively moderate temperature (between 200 and 350°C, on the order of 200°C for example) and under vacuum.In one example, the silicon nitride layer 16 can have a thickness of approximately 50 nm.

[0115] With reference to [Fig.4], a group of 42 subsequent steps is then implemented to arrive at the microstructure illustrated by [Fig.3D]. The steps in this group of 42 steps comprise steps 2, 3 and 4 of the process, which are implemented successively and in that order.

[0116] In step 2 of the process, a conformal layer 17 of TEOS (abbreviated as tetraethyl orthosilicate) is deposited on the upper face of the microstructure of [Fig. 3C]. TEOS, whose full name is "tetraethyl orthosilicate" and whose chemical formula is Si(OCH2CH3)4 or more simply Si(OEt)4, is used as a precursor of silicon dioxide (SiO2).

[0117] In step 3 of the process, annealing is carried out, i.e., the microstructure coated with the conformal layer of TEOS is heated to a temperature, for example, of approximately 400°C, to transform the TEOS layer 17 into a layer of silicon dioxide (SiO2). In one example, the silicon dioxide layer 17 thus formed can have a thickness of approximately 900 nm. This layer 17 acts as an electrical insulator. It can, in fact, block the electric current to or from the metallizations in the underlying layer 14 of the interconnecting structure.

[0118] A person skilled in the art will appreciate that there are other means of producing the dielectric layer 17, but the layer obtained as proposed above (with steps 2 and 3 above) has the advantage of exhibiting high chemical stability.

[0119] In step 4, a mask 31 of photosensitive resin or "photoresist" is formed to obtain a protective coating on the surface of the microstructure, in preparation for the execution of a first photolithography operation 5 (denoted "HBM 1" in [Fig. 4] and subsequently), to be carried out to achieve the HBM metallization level with non-functional bonding pads 17b and functional bonding pads 17c for hybrid bonding. This HBM 1 photolithography aims to create a mask by etching the silicon oxide layer 17 through the photo-resin mask 31, which mask can then be used to open the silicon nitride layer 16 in order to expose the portions of the metallizations of the MX layer intended to be electrically connected to the functional bonding pads 17c.

[0120] More specifically, step 4 includes: • the spreading of the photoresist, for example by a spin coating process, the principle of which consists of spreading a small quantity of resin mixed with a solvent, which temporarily gives it a certain fluidity, onto the wafer using centrifugal forces. The resin is placed in the center of the wafer before it is spun; then the development of the photoresist, which includes • the exposure of said resin to optical radiation, for example radiation in the ultraviolet (UV) range, through a suitable optical mask. Such a mask comprises opaque and transparent areas, which define the etching patterns, either in positive or negative depending on the nature of the photoresin in question. It allows the patterns to be defined that one wishes to reproduce on the wafer 1, in the SiO2 layer 17, by etching through the resin layer thus developed, which forms an etching mask; and, • Selective removal, for example by chemical etching, of exposed or unexposed resin portions, depending on the nature (positive or negative) of the photoresist. The removal process used can be chemical vapor etching, for example under oxygen plasma, which allows for very thorough removal of all traces of organic materials such as photosensitive resins.

[0121] The optical mask used to reveal the photoresin of layer 31 in step 4 has patterns that correspond to the implantation scheme of the bonding pads for hybrid bonding, including the non-functional bonding pads 17c as well as the functional pads 17b. In other words, the first HBM lithography 1 makes it possible to form, in the layer 17 of dielectric material, the boxes 17a in which all the metal bonding pads for hybrid bonding of the wafer 1 to the other wafer 2 will then be made, whether they are functional or non-functional, that is to say whether they serve only for bonding, or both for bonding and electrical connection, respectively, between the two wafers 1 and 2.

[0122] It does not appear necessary to detail further the above sub-steps of step 4 which allow obtaining the HBM 1 photolithography mask (also called HBM 1 mask for short), which are well known in themselves to the person skilled in the art.

[0123] Following the group of steps 42 comprising steps 2, 3 and 4 described above, the photoresin mask 31 is as shown in the aforementioned [Fig. 3D]. In the configuration of [Fig. 3D], the HBM mask 1 exposes layer 17 only through its open areas 31a (or apertures), and it masks layer 17 outside of said areas 31a.

[0124] In step 5, which is part of the group of steps 5 and 6 shown in block 43 of the flowchart in [Fig.4], the layer 17 of dielectric material (SiO2) is etched through the HBM 1 mask, stopping on the silicon nitride layer 16.

[0125] This can be chemical etching (or wet etching) using a hydrofluoric acid (HF) solution, for example, or physical etching (or dry etching), i.e., plasma etching. Etching can also be reactive ion etching (RIE), which is a variation of plasma etching combining the selectivity of chemical etching and the anisotropy of physical etching. In some embodiments, the plasma can then be a fluorocarbon plasma, based on a gas such as carbon tetrafluoride (CF4), for example, or on sulfur hexafluoride (SF6), or on nitrogen trifluoride (NF3), or any combination of these gases. The insulating material layer 17, partially protected by the HBM etching mask 1 formed by the partially open silicon dioxide layer 31 as described above, is placed in a chamber in which a vacuum is created.This chamber is equipped with two horizontal and parallel electrodes, the lower electrode serving as a platform to receive wafer 1. Once a vacuum has been created in the chamber, gas is introduced. Then, a strong radio frequency (RF) electric field, for example, of a hundred volts per meter or more, is applied to the lower electrode. This generates a plasma in the chamber, that is, a partially ionized gas. Indeed, some electrons from the gas molecules are stripped by the electric field, which ionizes these molecules. The upper surface of the wafer is then bombarded with ions, which disintegrates it.

[0126] The advantage of such etching is that it is highly anisotropic, the ion bombardment occurring only in the direction between the electrodes, i.e., the direction normal to the plane of the wafer 1. The boundary between the etched and unetched areas is therefore perfectly straight and vertical. However, this etching is not very selective, meaning that it destroys the material of the HBM mask 1 formed by layer 31 along with the areas of the protective layer 17 underneath. underlying which are exposed by the openings 31a through said mask. The etching is complete when the Silicon Nitride (SiN) of layer 16 is reached at the openings 31a of the HBM 1 mask.

[0127] In step 6, the removal ("stripping" in English) of the resin residues from the HBM 1 mask is carried out. This can be done by chemical etching, for example with a solution based on sulfuric acid (H2SO4) and hydrogen peroxide or hydrogen peroxide (H2O2).

[0128] It should be noted that even if etching step 5 leaves the surface of the HBM 1 mask relatively damaged, this is not a real drawback since, in step 6 following the completion of the etching, the residues of the HBM 1 etching mask are removed. To limit the risk of destroying the mask before the end of the etching process, the ion bombardment of step 5 can be temporarily interrupted during the etching process to anneal the wafer in order to reharden the HBM 1 mask by reforming the crystal lattice of layer 31, before resuming the ion bombardment etching. This process can possibly be repeated several times in succession until the etching is complete, i.e., until the Silicon Nitride 16 layer is reached.

[0129] At the end of the group of steps 43 comprising steps 5 and 6 presented above, the microstructure is as shown in [Fig.3E].

[0130] In step 7, which is the only step in block 44 of the step diagram in [Fig. 4], a new layer of photoresin 32 is spread to form an etching mask for the execution of a second lithography, labeled "HBM 2". With reference to [Fig. 3F], the photoresin layer 32 is conformally deposited on the front face of the wafer, for example by centrifugal coating (see above, regarding the photoresin layer 31 for forming the etching mask HBM 1). As can be seen in this figure, the layer 32 conforms to the relief resulting from the openings 17a formed in the dielectric material layer 17 by the first lithography HBM 1. In other words, said layer 17 has a thickness such that the free face of this layer conforms to the hollows and / or protrusions of the microstructure on which it is deposited.

[0131] The photoresin of layer 32 is then developed in step 7a to form a new etching mask, which is then used to perform a second lithography, referred to as "HBM 2". This HBM 2 lithography is then performed in step 8 to etch the Silicon Nitride layer 15. In what follows and in the figures of the drawings, this mask is referred to as "HBM 2 mask" for short.

[0132] In the step diagram of [Fig.4], steps 7a and 8 are grouped together in step block 45, because the overall result obtained after execution of these two steps is shown in [Fig.3G].

[0133] As shown in this figure, the optical mask used to reveal the photoresin of layer 32 in step 7a has patterns that correspond to the arrangement of the functional bonding pads 17c. In other words, the optical mask used to reveal the photoresin of layer 32 in step 7a has patterns that correspond to the interconnection patterns defined by the arrangement of the functional bonding pads 17c, which are intended for the electrical connection of wafer 1 with the other wafer 2, by hybrid bonding of said wafers 1 and 2. Put another way, the second HBM lithography 2 makes it possible to open the bottom of some of the cells 17c among the cells 17a that were formed in the layer 17 of dielectric material by the first HBM lithography 1.

[0134] This result is obtained in step 8 by partially etching the Silicon Nitride layer 16 at the bottom of said boxes 17c only, through the etching mask HBM 2. By this partial opening of the layer 16 in the etching step 8, the metal of some of the horizontal metallizations of the metallization level MX in the dielectric layer 14 is exposed at the bottom of the boxes 17c, such as the conductive track 15 in the example shown in [Fig.3G]. As will be understood, these are the metallizations which, according to the routing plan of the 3D microelectronic device, need to be taken up at the bonding interface between wafers 1 and 2. The functional bonding pads 17c can then be formed by filling the 17c boxes with metal, with coupling, i.e. with electrical continuity up to horizontal metallizations of the metallization level MX, in order to ensure the desired electrical connection between the two wafers 1 and 2.Of course, in addition to ensuring this electrical connection, the functional 17c pads thus produced can serve as a support for the hybrid bonding of said plates.

[0135] The other cells 17b among the cells 17a formed by the first lithography HBM 1, i.e., the cells other than the aforementioned cells 17c, are not opened to the metal of the hybrid layer 14 by the execution of the etching 8 corresponding to the second lithography HBM 2. The Silicon Nitride layer 16 is left intact, being protected by the etching mask HBM 2. These other cells 17b are those in which the non-functional bonding pads will subsequently be made by metal deposition, without coupling, i.e. without electrical continuity with the metal of the horizontal metallizations of the metallization level MX.Electrical insulation between the non-functional connecting pads 17b and any horizontal metallization of the MX metallization level in the hybrid layer 14 is ensured by the Silicon Nitride layer 16 (insulating material) which remains intact at the bottom of the boxes 17b after the etching carried out in step 8 through the etching mask HBM 2.

[0136] The etching of Silicon Nitride layer 16 carried out in step 8 through the etching mask HBM 2 can, like the etching of the first lithograph, be reactive ion etching (RIE), with a fluorocarbon plasma, for example based on a gas such as carbon tetrafluoride (CF4) and / or sulfur hexafluoride (SF6) and / or nitrogen trifluoride (NF3).

[0137] In step 9, the material is removed from the HBM2 photolithography mask. As with the removal of resin residues from the HBM1 etching mask in step 6, this removal can be achieved by chemical etching with a solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). Following this removal, which is represented by block 46 in the step diagram of [Fig. 4], the microstructure illustrated in [Fig. 3H] is obtained.

[0138] Next, a layer of copper is deposited in conformity to fill the cavities 17c to form the functional pads 17c, as well as the cavities 17c to form the non-functional pads 17b. Advantageously, a single deposition step ensures the simultaneous formation of all the bonding pads, namely the non-functional bonding pads 17b and the functional bonding pads 17c. This deposition can be achieved, for example, by an electrochemical deposition (ECD) process. This is the subject of steps 10, 11, 12, and 13, which will now be presented. These steps are part of the group of steps represented by block 47 in the step diagram of [Fig. 4].

[0139] In this example, the filling of the boxes 17c and 17b with copper to make the functional connecting pads 17c and the non-functional connecting pads 17b, respectively, is carried out in two steps.This two-step implementation method makes it possible to overcome the problems of uniformity in the copper deposition, which result in particular from the differences in the respective resistivities of the materials present on the surface to be coated: the resistivity of the Silicon Dioxide (SiO2) layer 17 is generally between 1012 and 1016 ohms centimeters (Q cm) and the resistivity of the Silicon Nitride (SiN) layer 16 which is exposed in the bottom of the boxes 17b is on the order of 1016 Q cm, while the resistivity of the horizontal metallizations of the metallization level MX which are exposed in the bottom of the boxes 17c is 17x10 7 Q cm, or 1.7 pQ cm. In a first step, a copper film is deposited, namely a thin layer of copper adapted to properly line the entire interior of the boxes 17c and 17b to be filled. and to serve as a copper underlayer.This thin layer then acts as an adhesion layer, also called a germination film (called "seed layer" in English), for the growth of a thicker layer of solid copper, for example by ECD.

[0140] For electrochemical deposition, the wafer is immersed in an electrolytic solution comprising copper precursor ions, the wafer 1 (and therefore in particular the copper adhesion layer) being configured as a cathode, i.e. , at the negative terminal. Alternatively, or in addition, copper is deposited onto the bonding layer from a copper source configured as an anode, i.e., at the positive terminal, when an electric current is passed between said positive and negative terminals. In all cases, since the electrochemical deposition reaction is driven by an electric current, it is very sensitive to the ohmic drop across the surface to be coated. To avoid any risk of void formation in the patterns formed by the cells 17b and 17c during their electrochemical filling, it is therefore ideal to have previously formed a perfectly conforming bonding layer, that is, one of the most constant thickness possible while conforming to all the hollows and / or protrusions present on the surface of the microstructure. This promotes the filling of the bottom of the cells 17b and 17c, and prevents said cells from closing prematurely by creating a cavity within them.It would be beyond the scope of this description to detail the technological steps required to achieve this result. A person skilled in the art, based on their general knowledge, will be able to refer as needed to the relevant technical literature, particularly but not exclusively concerning so-called "super-fill" deposition techniques, for example.

[0141] In practice and with reference to the step diagram in [Fig.4], in step 10 a very thin copper sublayer is first deposited on the microstructure by physical vapor deposition (or PVD) at low and medium temperature, or by chemical vapor deposition (or CVD) at medium and high temperature, to form the copper nucleation layer.

[0142] This chemical deposition is achieved in the presence of a solution containing a precursor (or "seed") of the metal to be deposited. A metal precursor consists mainly of ions of that metal. Rather than a monolithic coating, it may be advantageous to create the nucleation layer as a film made of an alloy combining different materials, each contributing its respective advantages (adhesion, melting point, density, coefficient of thermal expansion, electrical resistivity, etc.). The behavior of the precursors during deposition (volatility, vapor pressure, stability, etc.) is also a criterion for selecting the precursor ion(s). In summary, the ionic compounds in the group of materials considered for forming the nucleation film are selected by taking into account thermodynamic, mechanical, and physical criteria.In the application covered by the invention, namely the filling with copper of the bonding motifs in the HBM metallization level of wafers to be assembled by hybrid bonding, a Ti-TiN-Cu system proves to be a good candidate for copper deposition in the physical or chemical vapor phase. the corresponding solution consists mainly of copper ions, as well as titanium ions and titanium nitride ions.

[0143] As an alternative to a PVD or CVD process, the adhesion layer can be formed by reducing a solution of ionic precursors of copper and, where applicable, of other metals selected to compose a copper alloy. In order to promote conformal deposition, it may be chosen to proceed by the formation of an oxide, and in particular a copper oxide only, which is more thermodynamically favorable than the formation of metallic copper, and then to reduce this oxide, for example, during annealing under a reducing atmosphere.

[0144] In all embodiments, the thickness of the deposited copper nucleation layer is a few tens of nanometers. As explained above, this nucleation layer serves to initiate the electrolytic growth of copper during the implementation of an electrolytic copper deposition (ECD) process. In some embodiment examples, the thickness of the nucleation layer can be approximately 90 nm.

[0145] In step 11, the actual bulk copper layer is deposited, for example by the ECD process. This is achieved, for example, by immersing the wafer in the electrolyte and applying a voltage between the wafer configured as the cathode and an anode, for example a copper source configured as the anode. The patterns corresponding to the cells 17b and 17c, already coated with the nucleation film, are then filled with copper electrochemically.

[0146] To ensure proper pattern filling, several additives can be added to the electrolyte: a suppressor, an accelerator, and a leveler. These additives, detailed below, combine their effects to slow down deposition at the top of the trench and accelerate it at the bottom of the trench: • suppressors are macromolecules, such as polyethylene glycol (PEG), which tend to remain on the surface of the microstructure without diffusing into the trenches, and which react with chlorides added in solution to form a film protecting the surface and limiting the reduction of the metal at that location; • Accelerators inhibit the effect of suppressors, while also tending to position themselves in the trenches. They therefore allow copper growth in the trenches. Accelerators are often sulfide molecules, of which SPS (HSO3(CH2)3S) is a non-limiting example; and, • Leveling agents, such as the JGB (Janus Green B) molecule, have the same type of action as suppressors, but tend to position themselves in areas of high current density (peaks, protrusions, etc.). They therefore limit deposition in the high points of the microstructure.

[0147] To complete the copper deposition by the ECD process, a high-temperature stabilizing anneal can be performed in step 12 to induce melting at the deposition interface. This results in less abrupt, and therefore less brittle, interfaces. This annealing also stabilizes the Cu layer. For example, annealing at 400 °C allows the microstructure to reach thermodynamic equilibrium.

[0148] A person skilled in the art will appreciate that, instead of electrodeposition (ECD), another metal deposition process can also be used, i.e., a different process for depositing bulk copper. As an alternative to the ECD process described above, one can, for example, choose a technique from among autocatalytic transformation, precipitation, crystallization, crosslinking, aggregation, or others.

[0149] In the foregoing, embodiments have been proposed in which the filling metal for the cells 17b and 17c, used to simultaneously form the bonding pads 17b and 17c, respectively, is copper. However, the invention is not limited to this example. Another metal can be deposited in the cells to form the bonding pads, for example, gold (Au), which can also be deposited by electrodeposition (ECD) from a chemical precursor comprising corresponding metal ions, or titanium (Ti), aluminum (Al), niobium (Nb), or platinum (Pt), which can then preferably be deposited by a PVD-type process. This list of metal examples is not exhaustive. If necessary, an adhesion layer (germination film) suitable for the growth of this metal is then formed in step 10.

[0150] In step 13, the excess copper is removed from the upper surface of the HBM metallization layer, for example, by a chemical-mechanical polishing (CMP) process. The CMP process provides a very fine level of nano-topography (less than 5 nm, for example) and ensures a very low level of roughness (less than 0.5 nm, for example) for a defect-free hybrid bond. In other words, the implementation of step 13 results in a wafer 1 with an ultra-polished upper surface. Step 13 completes the group of steps represented by block 47 in the step diagram of [Fig. 4]. The resulting microstructure 1 shown in [Fig. 31] is then obtained.

[0151] In step 14, the upper plate 1 is hybridized onto the lower plate 2 after being vertically inverted. Naturally, the lower plate 2 has undergone the same treatments as the upper plate 1, in parallel. It therefore has an interconnection structure with the same characteristics as the upper plate 1. Its upper surface is also ultra-polished. The bonding is direct – without glue – and is carried out at room temperature. This avoids the risk of degradation and unwanted interaction of an adhesive during subsequent temperature treatment, if necessary.

[0152] In step 15, the resulting 3D microstructure can undergo bond annealing to strengthen the bond interface 60 between wafers 1 and 2 and ensure the electrical connection between the functional bonding pads 17c and 27c of wafers 1 and 2, respectively. For example, bond annealing can be performed at 400 °C for two hours. To assess the quality of the bond, scanning acoustic microscopy (SAM) can be used to detect any voids.

[0153] In a manner known per se, the rear substrate 11 of the upper plate 1 is finally thinned, for example by a process carried out from the front of the 3D microstructure shown in [Fig.2], for example first mechanically and then chemically in order to reduce the risk of damage to the bonding interface 60.

[0154] In the step diagram of [Fig.4], steps 14 and 15 are grouped in block 48. The result obtained at the end of this group of steps 48 is the 3D microstructure of [Fig.2].

[0155] The table in [Fig.5] lists the steps for realizing the 3D microstructure according to implementations of the process according to the invention (right column) for realizing the 3D microstructure of [Fig.2] in which the upper interconnection level HBM of the interconnection structure of the wafer is directly above the horizontal interconnection level MX, comparing them with the steps of a process according to the prior art (left column) for realizing the classic 3D microstructure of [Fig.1C], i.e. having a vertical interconnection level HBV with vertical metallizations (vias) between the upper interconnection level HBM and the horizontal interconnection level MX.

[0156] As a person skilled in the art can see, nine technological steps in production are eliminated, which is a significant gain in terms of energy balance in particular, as well as in terms of processing time in the cleanroom.

[0157] Furthermore, by removing the HBV metallization level from the prior art 3D microstructures, two layers of dielectric material are eliminated (one in each of the upper and lower plates stacked by hybrid bonding), namely two layers of Silicon Dioxide (SiO2), which is an improvement in terms of mechanical stress. Two layers of insulation are also eliminated, namely the Silicon Nitride (SiN) insulating layer covering the dielectric material layer of the HBV metallization level in the upper and lower plates of the prior art 3D microstructures.

[0158] Specific embodiments have just been described. Various variations and modifications will be apparent to those skilled in the art. In particular, it goes without saying that the invention is not limited by the number of metallization levels envisaged. in the interconnection structure, which can comprise several levels, such as the MX metallization level considered here. Furthermore, the invention describes a method for creating a 3D microstructure by vertically integrating more than two wafers. The operations can be repeated to continue the vertical integration, with each iteration involving the bonding of a new wafer onto the microstructure obtained in the previous iteration, by implementing the method of the invention. The only constraints in this regard are those that are classically related to the ability to rework the surfaces to flatten them for further bonding, and of course, to the limit of mechanical stress on the wafers caused by stacking.

Claims

1. Demands Three-dimensional, 3D microelectronic structure for an integrated semiconductor product, said 3D microelectronic structure comprising a first microelectronic device fabricated on an upper wafer (1), and a second microelectronic device fabricated on a lower wafer (2) to which the upper wafer (1) is bonded by hybrid bonding after vertical inversion, in which the lower wafer and the upper wafer each comprise a substantially planar substrate and an interconnection structure formed above said substrate, characterized in that: • the respective interconnection structure of each of the upper (1) and lower (2) plates is a vertical stack of at least two directly superimposed interconnection levels, each comprising a hybrid layer essentially composed of a dielectric material, namely, respectively: • a higher interconnection level (HBM), with metallic bonding pads (17b, 17c) formed in the dielectric material and adapted to cooperate with corresponding metallic bonding pads (27b, 27c) of the other wafer for hybrid bonding of the upper wafer (1) to the lower wafer (2); and, • a horizontal interconnection level (MX) which is directly below the upper interconnection level (HBM), with horizontal metallization elements (15; 25), • the respective metallic bonding pads (17b, 17c; 27b,27c) of each of the upper (1) and lower (2) plates are distributed substantially homogeneously on the upper surface of the upper interconnection level (HBM) of the interconnection structure of said plate, with a bond pitch, defined as the maximum spacing between horizontally adjacent bond pads in the plane of said upper surface, which is below a determined associated threshold; • the respective metallic bonding pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) plates include bonding pads of a first type (17b; 27b), which are electrically isolated from any horizontal metallization element (15; 25) of the horizontal interconnection level (MX) of the interconnection structure of said plate; and, • the respective metallic bonding pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) plates further include bonding pads of a second type (17c; 27c), which are electrically coupled each to at least one underlying horizontal metallization element (15; 25) formed in the horizontal interconnection level (MX) of the interconnection structure of said plate.

2. A 3D microelectronic structure according to claim 1, wherein the horizontal interconnect level (MX) of the interconnect structure of each of the lower (1) and upper (2) wafers comprises a passivation film (16; 26) of electrically insulating material covering the layer (14; 24) of dielectric material of said horizontal metallization level (MX), and wherein the first-type connecting pads (17b; 27b) of each of the upper (1) and lower (2) wafers are electrically isolated from any horizontal metallization element of the horizontal interconnect level (MX) of the interconnect structure of said wafer, at least by the insulating material of the passivation film covering the layer (14; 24) of dielectric material of said horizontal metallization level (MX).

3. A 3D microelectronic structure according to claim 1 or claim 2, wherein the dielectric material layer (14; 24) of the upper interconnect level (HBM) of the interconnect structure of each of the upper (1) and lower (2) wafers is a patterned hybrid dielectric material layer, said patterns defining: solid areas of said dielectric material; • the first vertically filled through zones of metallic material and at which the insulating material of the passivation layer of the horizontal interconnection level (MX) is present, said first through zones forming the first type of connection pads (17b;27b) of the upper interconnection level (HBM); and, • the second vertically filled through zones of metallic material, and at which the passivation layer of the horizontal interconnection level (MX) has an opening, said second through zones forming the second type of connection pads (17c;27c) of the upper interconnection level (HBM), each in electrical continuity with one of the horizontal metallization elements (15;25) of the horizontal interconnection level (MX) through said opening of the passivation layer.

4. 3D microelectronic structure according to any one of claims 1 to 3, wherein the associated threshold of the bonding pitch is less than or equal to 10 pm, preferably on the order of 5 pm.

5. 3D microelectronic structure according to any one of claims 1 to 4, wherein the dielectric material of the hybrid interconnect layers of the interconnect structure of each of the upper (1) and lower (2) wafers is Silicon Dioxide (SiO2).

6. 3D microelectronic structure according to any one of claims 1 to 5, wherein the constituent material of the metallic bonding pads of the upper interconnect level (HBM) and / or the constituent material of the horizontal metallizations (15,25) of the horizontal interconnect level (MX) of the interconnect structure of each of the upper (1) and lower (2) wafers, is a metal selected from the group comprising copper (Cu), gold (Au), titanium (Ti), aluminum (Al), niobium (Nb) and platinum (Pt), or an alloy based on at least one of said metals.

7. A 3D microelectronic structure according to any one of claims 2 to 6, wherein the electrically insulator of the passivation film (16,26) of the horizontal interconnection level (MX) of the interconnection structure of each of the upper (1) and lower (2) wafers is a Silicon Nitride (SiN) or a Silicon Carbonitride (SiCN).

8. A 3D microelectronic structure according to any one of claims 1 to 7, wherein the substrate of the upper wafer (1) and / or the substrate of the lower wafer (2) each comprise an active area with active elements in the upper part of said substrate, and wherein: • the first type of connecting pads of the interconnect structure of each of the upper (1) and lower (2) wafers are electrically isolated from the active elements of the active area of ​​the substrate of said wafer, whereas, • at least some of the second type of connecting pads of the interconnect structure of the upper (1) and / or lower (2) wafer are electrically coupled to at least one of the active elements of the active area of ​​the substrate of said wafer.

9. Method of realizing a three-dimensional, 3D microelectronic structure according to any one of claims 1 to 8, comprising the hybrid bonding of an upper wafer (1) onto a lower wafer (2) after vertical flipping of said upper wafer (1), characterized in that the prior realization of the interconnection structure of each of the lower (1) and upper (2) wafers comprises the formation of a vertical stack of at least two interconnection levels directly superimposed on the substrate of said wafer, namely, respectively: • a horizontal interconnection level (MX), with horizontal metallization elements (15; 25) formed in the dielectric material of a corresponding hybrid layer;and, directly above said horizontal interconnection level (MX), • a higher interconnection level (HBM) with metallic bonding pads (17b, 17c) formed in the dielectric material of a corresponding hybrid layer, and;

10. adapted to cooperate with corresponding metallic bonding pads (27b,27c) of the other plate, for hybrid bonding of the upper plate (1) onto the lower plate (2), said process being further characterized in that: • the respective metal connecting pads (17b, 17c; 27b,27c) of the upper metallization level (HBM) of the interconnection structure of each of the upper (1) and lower (2) plates are made with a substantially homogeneous distribution on the upper surface of said upper metallization level (HBM), and with a bonding pitch, defined as the maximum spacing between horizontally adjacent bonding pads in the plane of said upper surface, which is less than a determined associated threshold; • among the respective metallic connecting pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) plates, connecting pads of a first type (17b; 27b) are each made with electrical insulation with respect to any horizontal metallization element (15; 25) of the horizontal interconnection level (MX) of the interconnection structure of said plate; • among the respective connecting pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) plates, in addition, connecting pads of a second type (17c; 27c) are each made in electrical continuity with at least one underlying horizontal metallization element (15; 25) formed in the horizontal interconnection level (MX) of the interconnection structure of said plate. A method according to claim 9, wherein the formation of the upper interconnection level (HBM) of the interconnection structure of each of the upper (1) and lower (2) plates comprises: • the deposition (41) of a passivation film (16; 26) of electrically insulating material which covers a hybrid layer (14; 24) of dielectric material comprising elements

11. horizontal metallization (15; 25) of the horizontal metallization level (MX) of the plate; • the formation of a layer (17; 27) of dielectric material and a first photolithographic etching (41, 42), to etch said layer of dielectric material with a stop on the passivation film (16; 26) of the horizontal metallization level (MX) in order to form patterns in said layer (17; 27) of dielectric material corresponding to the metallic bonding pads (17b, 17c; 27b, 27c) of the upper metallization level (HBM) of the wafer; then, • a second photolithographic etching (43, 44, 45), to etch the passivation film (16; 26) of the horizontal metallization level (MX) in order to open said film in only a part of the patterns previously formed in the layer (17; 27) of dielectric material which correspond to the second type metallic bonding pads (17c; 27c) of the upper metallization level (HBM) of the wafer; then, • the filling (47), with metal, simultaneously of all the patterns previously formed in the layer (17; 27) of dielectric material, namely both the patterns corresponding to the metallic bonding pads of the first type (17b; 27b) and the patterns corresponding to the metallic bonding pads of the second type (17c; 27c) of the upper metallization level (HBM) of the wafer. Method according to claim 10, wherein the patterns in the layer (17; 27) of dielectric material corresponding to the metallic bonding pads (17b, 17c; 27b, 27c) of the upper metallization level (HBM) of the wafer are filled with metal by electrochemical deposition.

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