Power electronic module with thermal retardation element during a short circuit

Abstract

A power electronic module (10) comprising a substrate (11) including at least one power circuit (11c), said module (10) including at least one primary interconnect joint (13) integral with the power circuit (11c) and at least one semiconductor (12) including a metallized upper surface (12b) and a lower surface (12a) assembled to the power circuit (11c) via the primary interconnect joint (13). The module includes at least one secondary interconnect joint (17) integral with the metallized upper surface (12b) of the semiconductor (12) and at least one protrusion (20) having a thermal retardation capacity and integral with said metallized upper surface (12b) via the secondary interconnect joint (17). Figure for abbreviation: [Fig 1]

Description

Title of the invention: Power electronic module with thermal delay element during a short circuit Technical field of the invention

[0001] The present invention relates to so-called power modules, i.e. modules used in the field of power electronics.

[0002] The invention finds a particular application in the field of aeronautics.

[0003] Power electronics modules are integrated into converters required for the electrification of propulsion and non-propulsion systems on board aircraft. They allow the conversion of electrical energy from the main network (115V AC, 230V AC, 540V DC, ...) into several forms (AC / DC, DC / AC, AC / AC and DC / DC). Prior art

[0004] As is known, a power module comprises semiconductors controlled by external electronics. Such components mainly adopt two stationary states (a conducting state, allowing current to flow, or a blocking state, preventing any current flow) as well as a transient state, through which the component passes to go from the conducting state to the blocking state, or vice versa.

[0005] An external fault in the power module may occur, significantly increasing the value of the current seen by the conducting semiconductors, particularly under the effect of the power supplied by an external voltage source.

[0006] We know the semiconductor component called MOSFET, an acronym for "metal-oxide-semiconductor field-effect transistor" in Anglo-Saxon terms.

[0007] Such a semiconductor can be made using Silicon, such as silicon carbide, a chemical compound of formula SiC.

[0008] Increasing the current value will induce a short circuit in the semiconductor, particularly in the case of a SiC MOSFET, after thermal runaway. This "short-circuit" state is not always desirable, as the user then loses control over the operation of the semiconductor in question.

[0009] It is therefore impossible to control the semiconductor(s) in the open state.

[0010] Furthermore, the energy dissipated in the power module then becomes very significant and can lead to the destruction of all or part of the power electronic module. Failure of the power electronic module results in the loss of equipment availability and constrains the entire upstream and downstream electrical chain.

[0011] Current power modules are primarily designed to meet needs such as: maximum size, mounting type, and compliance with functional, performance, environmental, efficiency, lifespan, and / or reliability requirements. However, they are not always designed to meet a requirement for an open-circuit failure mode in the aforementioned fault scenarios.

[0012] Improving known power modules is a necessity. Description of the invention

[0013] The present invention therefore aims to overcome the aforementioned drawbacks.

[0014] The object of the invention is therefore to avoid the degradation of the semiconductors of a power module in the event of overheating due to a short circuit.

[0015] More particularly, the present invention aims to meet a requirement for obtaining an open circuit type failure mode, in the cases of faults described above.

[0016] The invention relates to a power electronic module comprising a substrate including at least one power circuit, said module including at least one main interconnecting joint integral with the power circuit and at least one semiconductor or semiconductor component extending along an extension plane, for example horizontal, and including a metallized upper surface and a lower surface assembled to the power circuit via the main interconnecting joint.

[0017] The power electronic module includes at least one secondary interconnecting joint attached to the metallized upper surface of the semiconductor and at least one element or protrusion having a thermal retardation capacity and attached to said metallized upper surface via the secondary interconnecting joint.

[0018] It is of interest to a user to be able to have a power electronic module which, subjected to short-circuit conditions, due to an internal and / or external fault, is able to adopt an open circuit, without being subjected to violent degradation, such as an explosion for example.

[0019] The thermal connection between the thermal retarding protrusion and the semiconductor via the additional connecting joint limits the temperature increase of the semiconductor's outer surface. This results in an open-circuit failure mode for the semiconductor.

[0020] The thermal retardation protrusion is an additional element to an electrical connection, which may be of the "wire bonding" type.

[0021] It is preferable that the contact surface between the thermal retardant protrusion and the metallized upper surface of the semiconductor is maximized, with the constraint that this contact surface will be limited by the surface occupied by electrical connections such as, for example, wire bonding type connections.

[0022] The thermal retardation protrusion provides thermal inertia on the metallized outer surface, called metallization, of the semiconductor which is under great stress during an open-circuit operating mode of the semiconductor, thus preventing degradation of said semiconductor.

[0023] Indeed, in the case of a short circuit, the current flowing through the semiconductor is greater than the current for which the semiconductor is designed. The temperature of the areas of the semiconductor carrying the main current increases significantly, despite the short duration of the short circuit. Generally, this is the surface metallization area, that is, the metallized upper surface of the semiconductor, which is poorly thermally connected to the substrate and is a cold source.

[0024] Under the stress of a large amount of energy concentrated at the level of the surface metallization zone of the semiconductor, the metallization can change state and pass from a solid state to a liquid state, then gaseous for part of the constituents of the metallization and finally back to a solid state with surface asperities.

[0025] The dynamics of this transformation are directly related to the rate of temperature rise of the metallization. They therefore depend on the energy to be dissipated, but also on the nature of the heat exchange between the metallization and its environment. The greater the transformation dynamics, the higher the risk of obtaining a semiconductor in an uncontrollable short-circuit state. Conversely, the lower the dynamics, the lower this risk, and it is possible to obtain a semiconductor forced into an open state without undergoing uncontrollable degradation.

[0026] The thermal retarding protrusion establishes effective thermal contact with the semiconductor metallization, which acts as a thermal retarder. The thermal retarding protrusion's ability to perform this thermal retarding function is determined by its thermal conduction performance and the additional thermal inertia provided by the assembly of the semiconductor with the thermal retarding protrusion.

[0027] The realization of such an assembly makes it possible to force the passage of the semiconductor from the short-circuit state to the open-circuit state, ensuring the obtaining of a "clean" degradation within the power electronic module, that is to say, not damaging other components of the power electronic module.

[0028] For example, the thermal retardation protrusion extends in a direction perpendicular to the extension plane of the semiconductor.

[0029] For example, the thermal retarding projection has a cylindrical shape.

[0030] Alternatively, any other shape could be provided for said thermal retardation projection, for example semi-spherical, hollow cylindrical, parallelepiped.

[0031] It could also be envisaged that the thermal retarding projection be in the form of a metal strip.

[0032] The thermal retarding projection is, for example, made of conductive material, for example metallic, for example copper.

[0033] According to one embodiment, the power electronic module comprises a plurality of thermal retardation protrusions distributed over the metallized upper surface of the semiconductor.

[0034] The semiconductor may include a drain disposed on the lower face and a grid and a source disposed on the upper face, the semiconductor further comprising a metallization of the drain, the grid and the source.

[0035] For example, the thermal retardation protrusions are distributed around the semiconductor source.

[0036] For example, the semiconductor drain is connected to the substrate by a main interconnecting joint or solder joint and thus has a good thermal connection with the substrate.

[0037] For example, the semiconductor source is connected to the substrate by wiring, for example by a soldering process technique that creates a wire bond, or "wire bonding" in Anglo-Saxon terms, ensuring an electrical connection between the semiconductor source and the substrate. This connection does not always provide a good thermal connection.

[0038] According to one embodiment, the primary interconnection joint is in the form of a paste, for example, a solder, and the secondary interconnection joint is also in the form of a paste, for example, a solder, the paste forming the primary interconnection joint having a higher liquidus than the paste forming the secondary interconnection joint. This allows the semiconductors to remain in position during the assembly step of the thermal retarding protrusions.

[0039] For example, the main interconnecting joint is connected to the substrate, in particular to the conductive top layer, by brazing.

[0040] By way of non-limiting example, the substrate comprises successively a lower conductive layer, an electrically insulating layer and an upper conductive layer.

[0041] The lower and upper conductive layers are, for example, made of metallic material.

[0042] The electrically insulating layer is, for example, made of ceramic material.

[0043] For example, said electrically insulating layer is arranged between the lower and upper conductive layers.

[0044] The lower and upper conductive layers can be assembled to the electrically insulating layer by one of the various known techniques, such as, for example, by brazing, or "active metal brazing", acronym AMB in Anglo-Saxon terms, or by direct bonding of copper or "direct bonded copper", acronym DBD in Anglo-Saxon terms, or by direct bonding of aluminium or "direct bonded aluminium", acronym DBA in Anglo-Saxon terms.

[0045] Alternatively, other layers forming the substrate could be provided.

[0046] The conductive top layer forms a power circuit on which power semiconductor components are assembled.

[0047] For example, the power electronic module may further include connectors allowing the power electronic module to be connected to external electrical elements.

[0048] According to one embodiment, the power electronic module further comprises at least one connector attached to the power circuit and at least one wiring wire electrically connecting the connector and the semiconductor, in particular the semiconductor source.

[0049] For example, and in no way limiting, the power electronic module includes a housing, for example made of plastic such as polymer surrounding the semiconductor components and attached to the substrate, in particular by bonding with an adhesive.

[0050] For example, the housing can be filled with an encapsulant, for example a gel or an epoxy resin to provide mechanical and electrical protection of the power components and wiring.

[0051] For example, the semiconductor is an electronic chip known as a MOSFET, an acronym for "metal-oxide-semiconductor field-effect transistor" in Anglo-Saxon terms, and may include a silicon carbide, a chemical compound with the formula SiC.

[0052] Alternatively, it could be envisaged that the semiconductors include other materials.

[0053] According to a second aspect, the invention relates to a method for manufacturing a power electronic module comprising a substrate including at least one power circuit, in which: - the substrate is prepared; - at least one main interconnection joint or braze is applied to the power circuit of the substrate; and - at least one semiconductor is assembled to the power circuit of the substrate via the main interconnection joint, for example by brazing or sintering techniques.

[0054] According to the process: - at least one secondary interconnection joint or solder joint is deposited on a metallized upper surface of the semiconductor; and - at least one thermal retarding projection is assembled on said metallized upper surface via the secondary interconnecting joint.

[0055] For example, the thermal retardation protrusion extends in a direction perpendicular to the extension plane of the semiconductor.

[0056] For example, the process further includes a step of electrically connecting the semiconductor, and in particular the source, by means of wiring, for example by a soldering process technique that makes a wire bond. This ensures an electrical connection between the semiconductor source and the substrate.

[0057] Without limiting the process, the method could also include subsequent steps, such as assembling the hood, injecting an encapsulant, etc... Brief description of the drawings

[0058] Other objects, features and advantages of the invention will become apparent from the following description, given solely by way of non-limiting example, and made with reference to the indexed drawings in which:

[0059] [Fig.1], is a schematic cross-sectional view of a power electronic module according to the invention;

[0060] [Fig.2], is a perspective view of the power electronic module of [Fig.1];

[0061] [Fig.3] illustrates the steps of a flowchart for a manufacturing process of the power electronic module of [Fig. 1]; and

[0062] [Fig.4], [Fig.5], [Fig.6], [Fig.7] and [Fig.8] represent the power electronic module of [Fig.1] during the different stages of the manufacturing process of [Fig.3], the module has been shown here without a cover.

[0063] Detailed description of at least one embodiment

[0064] As illustrated in [Fig.1], a power electronic module 10 comprises a substrate 11.

[0065] By way of non-limiting example, the substrate 11 comprises successively a lower conductive layer lia, an intermediate electrically insulating layer 11b and an upper conductive layer 1 le.

[0066] The lower and upper conductive layers 1 la, 1 le are, for example, made of metallic material.

[0067] The electrically insulating intermediate layer 11b is, for example, made of ceramic material.

[0068] Said electrically insulating intermediate layer 11b is arranged between the lower layer 1la and the upper layer 1le conductive.

[0069] The lower layer 1 la and the upper layer 1 le conductive are assembled to the electrically insulating intermediate layer 11b by one of the various known techniques, such as for example by brazing, or "active metal brazing", acronym AMB in Anglo-Saxon terms, or by direct bonding of copper or "direct bonded copper", acronym DBD in Anglo-Saxon terms or by direct bonding of aluminium or "direct bonded aluminium", acronym DBA in Anglo-Saxon terms.

[0070] Alternatively, other layers forming the substrate 11 could be provided.

[0071] The upper conductive layer 1 forms a power circuit on which power semiconductor components 12 are assembled. Here, six semiconductors 12 are assembled on the upper conductive layer 11c. Alternatively, one or more semiconductors could be provided.

[0072] As illustrated, the power electronic module 10 further includes main interconnecting joints 13 through which the semiconductor components 12 are assembled to the power circuit 11c.

[0073] The main interconnecting joints 13 can be in the form of a paste, for example a solder or solder preform.

[0074] The main interconnecting joints 13 can be connected to the substrate 11, in particular to the upper conductive layer 1, by brazing.

[0075] The assembly of the main interconnecting joints 13 with the substrate 11 is known and will not be described further.

[0076] The power electronic module 10 may further include connectors (not shown) allowing the power electronic module 10 to be connected to external electrical elements (not shown).

[0077] As illustrated, and in no way limiting, the power electronic module 10 further includes connectors 14 and electrical connections 15, for example in the form of wiring wires, electrically connecting the connectors 14 and the semiconductors 12.

[0078] As illustrated in [Fig.1], and in no way limitingly, the power electronic module 10 comprises a housing 16, for example made of plastic such as polymer surrounding the semiconductor components 12 and attached to the substrate 11, in particular by bonding with an adhesive (not shown).

[0079] The housing 16 can be filled with an encapsulant, for example a gel or an epoxy resin, to provide mechanical and electrical protection of the components of power 12, 14 and wiring wires 15.

[0080] Semiconductors 12 include, for example, an electronic chip known as a MOSFET, an acronym for "metal-oxide-semiconductor field-effect transistor" in Anglo-Saxon terms, and may include a silicon carbide, a chemical compound with the formula SiC.

[0081] Alternatively, it could be envisaged that the semiconductors 12 comprise other materials.

[0082] Generally, each semiconductor 12 extends along a horizontal plane and comprises a lower face 12a, substrate side 11, and a metallized upper face 12b.

[0083] By "metallized top face", it is understood that the top face or surface 12b of the semiconductor 12 has a surface metallization.

[0084] Each semiconductor 12 comprises a drain (not visible in the figures) disposed on the lower face 12a and a gate 12c and a source 12d disposed on the metallized upper face 12b. Each semiconductor 12 has metallization of the drain, the gate 12c and the source 12d.

[0085] The semiconductor drain 12 is connected to the substrate 11 by a main interconnecting joint 13 or solder joint and thus has a good thermal connection with the substrate 11.

[0086] The semiconductor source 12 is connected to the substrate 11 by the wiring wires 15, for example by a welding process technique which allows a wire bonding, or "wire bonding" in Anglo-Saxon terms, ensuring an electrical connection between the semiconductor source 12 and the substrate 11, but does not allow, via this connection, to have a good thermal connection.

[0087] As illustrated, the power electronic module 10 further comprises a plurality of projections 20, each equipped with a thermal retardation capacity and attached to each semiconductor 12 by means of a secondary interconnection joint 17.

[0088] Each projection 20 having a thermal retardation capacity is called a thermal retardation projection.

[0089] In other words, the so-called thermal retardation protrusions 20 are assembled on the metallized upper surface 12b of the semiconductors 12 via the secondary interconnection joints 17.

[0090] The secondary interconnection joints 17 can be in the form of a paste, for example a solder.

[0091] The paste forming the main interconnecting joints 13 has a liquidus greater than the liquidus of the paste forming the secondary interconnecting joints 17 so that the semiconductors 12 do not move during the protrusion assembly step thermal retardation.

[0092] In a phase diagram, the curve that separates a single-phase liquid domain from a two-phase domain includes a liquid and a solid solution.

[0093] The thermal retardation projections 20 extend, here, in a direction perpendicular to the extension plane of the semiconductors 12.

[0094] As illustrated, the thermal retardant projections 20 each have a cylindrical shape. Alternatively, any other shape could be provided for said thermal retardant projections 20, for example, semi-spherical, hollow cylindrical, parallelepiped or in the form of a metal strip.

[0095] The thermal retarding projections 20 are made of metallic material, for example copper.

[0096] As illustrated, each semiconductor 12 comprises three secondary interconnection joints 17 and three thermal retardation protrusions 20, each integral with a secondary interconnection joint 17.

[0097] Alternatively, each semiconductor 12 could be provided to include at least one secondary interconnection joint 17 and at least one thermal retardation protrusion 20, each integral with a secondary interconnection joint 17.

[0098] It could also be envisaged that several thermal retardation projections 20 are assembled on a single secondary interconnection joint 17.

[0099] The thermal retardation projections 20 are distributed here on the metallized upper surface 12b of each semiconductor 12 around the source 12d.

[0100] Fig. 3 illustrates the steps of a process 100 for manufacturing the power electronic module 10 of Figures 1 and 2.

[0101] The process 100 for manufacturing the power electronic module 10 includes a first step 101, visible in [Fig.4], of preparing the substrate and the connectors 14, a second step 102, visible in [Fig.5], of depositing a main interconnection joint 13 or soldering on the substrate 11 for the assembly, in step 103, of the semiconductor 12.

[0102] During step 103, visible in [Fig.6], the semiconductors 12 are assembled to the substrate 11 by brazing or sintering techniques.

[0103] The process 100 further includes a step 104, visible in [Fig.7], of electrically connecting the semiconductors 12, and in particular the source 12d, by the wiring wires 15, for example by a welding process technique which makes a wire bonding connection, or "wire bonding" in Anglo-Saxon terms, ensuring an electrical connection between the source of the semiconductor 12 and the substrate 11.

[0104] Steps 101, 102, 103 and 104 are known and will not be described further.

[0105] As illustrated, the method 100 further comprises a step 105 of depositing one or more secondary interconnecting joints 17 or secondary brazes onto the surface upper 12b metallized of each semiconductor 12, as seen in [Fig.8].

[0106] The secondary interconnecting joints 17 allow the assembly, in step 106, of thermal retarding protrusions 20 on the semiconductors 12, as seen in [Fig. 2]. This assembly can be carried out by sintering or by remelting the interconnecting joint 17.

[0107] It is also conceivable that step 105 consists of depositing a metallic paste, for example by a technique known as "dispensing" in Anglo-Saxon terms, on the metallized upper surface 12b of the semiconductor 12, after wiring the electrical connections or wiring wires 15. The implementation of a rapid reflow may prove necessary to ensure the best thermal contact with the surface metallization of the semiconductor chip.

[0108] Without limiting the foregoing, the process 100 could also include subsequent steps (not shown), such as assembling the hood 16, injecting an encapsulant, etc...

[0109] The thermal retarding protrusion(s) 20 establish effective thermal contact with the metallized upper surface 12b of the corresponding semiconductor 12, which acts as a thermal retarder. The assembly of the semiconductor 12 with the thermal retarding protrusion(s) forces the semiconductor 12 to transition from a short-circuited state to an open-circuited state, ensuring a "clean" degradation within the power electronic module, i.e., one that does not damage other components of the power electronic module.

Claims

Demands

1. Power electronic module (10) comprising a substrate (11) comprising at least one power circuit (11c), said module (10) comprising at least one main interconnect joint (13) integral with the power circuit (11c) and at least one semiconductor (12) extending along an extension plane, and comprising a metallized upper surface (12b) and a lower surface (12a) assembled to the power circuit (11c) via the main interconnect joint (13), characterized in that it comprises at least one secondary interconnect joint (17) integral with the metallized upper surface (12b) of the semiconductor (12) and at least one protrusion (20) having a thermal retardation capacity and integral with said metallized upper surface (12b) via the secondary interconnect joint (17).

2. Power electronic module (10) according to claim 1, wherein the thermal retardation protrusion (20) has the shape of a cylinder or a metal strip.

3. Power electronic module (10) according to any one of the preceding claims, wherein the thermal retardation protrusion (20) is made of conductive material, preferably metallic.

4. Power electronic module (10) according to any one of the preceding claims, comprising a plurality of thermal retardation protrusions (20) distributed over the metallized upper surface (12b) of the semiconductor (12).

5. Power electronic module (10) according to any one of the preceding claims, wherein the semiconductor (12) comprises a drain disposed on the lower face (12a) and a grid (12c) and a source (12d) disposed on the upper face (12b) metallized, the semiconductor (12) further comprising a metallization of the drain, the grid and the source.

6. Power electronic module (10) according to claims 4 and 5, wherein the thermal retardation protrusions (20) are distributed around the source (12d) of the semiconductor (12).

7. A power electronic module (10) according to any one of the preceding claims, wherein the primary interconnecting joint (13) is in the form of a paste and the secondary interconnecting joint (17) is in the form of a paste, the paste forming the joint main (13) interconnection exhibits a liquidas greater than the liquidus of the paste forming secondary (17) interconnection joint.

8. Power electronic module (10) according to any one of the preceding claims, further comprising at least one connector (14) integral with the power circuit (11) and at least one wiring wire (15) electrically connecting the connector (14) and the semiconductor (12).

9. A method (100) for manufacturing a power electronic module (10) comprising a substrate (11) comprising at least one power circuit (11c), in which: - the substrate (11) is prepared; - at least one main interconnection joint (13) is deposited on the power circuit (11c) of the substrate (11); and - at least one semiconductor (12) is assembled to the power circuit (11c) of the substrate (11) via the main interconnection joint (13); characterized in that according to the method: - at least one secondary interconnection joint (17) is deposited on a metallized upper surface (12b) of the semiconductor (12); and - at least one thermal retardation protrusion (20) is assembled on said metallized upper surface (12b) via the secondary interconnection joint (17).

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