SINGLE-PHOTON AVALANCHE DIODE COMPRISING A CAPACITIVE PASSIVATION STRUCTURE

Abstract

One aspect of the invention relates to a single-photon avalanche diode (3) comprising: a semiconductor substrate (30) doped with a first type of conductivity and having a first face (30a) and a second face (30b) opposite to the first face; a semiconductor region (31) doped with a second type of conductivity opposite to the first type of conductivity, extending in the semiconductor substrate (30) from the first face (30a) towards the second face (30b); and a capacitive passivation structure (32) disposed inside a first trench (33) which extends into the semiconductor substrate (30) from the first face (30a) towards the second face (30b), the capacitive passivation structure (32) extending in contact with the semiconductor region (31) and being configured to form a first layer of electrical charge accumulation in the semiconductor region (31) at the interface with the first trench (33).Figure to be published with the abbreviation: Figure 3.

Description

Title of the invention: SINGLE-PHOTON AVALANCHE DIODE COMPRISING A CAPACITIVE PASSIVATION STRUCTURE TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of single-photon avalanche diodes, also called SPADs (for "single-photon avalanche diode"). TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] A single-photon avalanche diode (SPAD) is a photodiode comprising a PN junction reverse-biased at a voltage higher than its breakdown voltage. When no electric charge is present in the depletion region (also called the space charge region) of the PN junction, the photodiode is in a pseudostable, non-conducting state. When an electric charge generated by the absorption of a photon is injected into the depletion region, if the velocity of this charge within the depletion region is sufficiently high—that is, if the electric field in the depletion region is sufficiently intense—the photodiode enters avalanche mode. A single photon is thus capable of generating a measurable electrical signal in a very short time.

[0003] SPADs exhibit high detection sensitivity and a very short response time, making them excellent candidates for time-of-flight measurement in telemetry, facial recognition, and LiDAR (Light Detection and Ranging) applications. They can detect very low-intensity radiation and are also used for single-photon detection and photon counting.

[0004] The PN junction is typically formed between a substrate doped with a first type of conductivity and a localized region (within the substrate) doped with a second type of opposing conductivity. A problem that arises in SPADs with a horizontal PN junction (i.e., parallel to the front and back faces of the substrate) is the collection of photogenerated charges deep within the substrate, at a distance from the photodiode's avalanche zone (i.e., the part of the depletion region where the electric field is sufficiently intense for an avalanche to be triggered by a single charge). Indeed, beyond a certain distance from the PN junction, the electric field resulting from the reverse biasing of the PN junction becomes zero or is significantly attenuated, and no longer allows the photogenerated charges to be drawn towards the avalanche zone.Only random diffusion in the substrate is then likely to conduct the photogenerated charges towards the zone. avalanche effect, with a significant probability that the photogenerated charges will never reach the avalanche zone or will reach it with a considerable delay. This problem arises particularly when attempting to collect photogenerated charges under the influence of long-wavelength radiation, for example, radiation with wavelengths between 750 and 1200 nm in silicon.

[0005] Fig. 1 is a schematic cross-sectional view of a SPAD-type photodiode 1 described in international application WO2018 / 050996A1.

[0006] The photodiode 1 comprises a P-type doped silicon substrate 10 and an N-type doped silicon localized region 11 extending through the substrate 10 in a substantially vertical direction, i.e., substantially perpendicular to the upper face 10a of the substrate 10. The localized region 11 is, for example, tube-shaped with a substantially vertical central axis. The substrate 10 and the localized region 11 form the anode and cathode of the photodiode 1, respectively. An avalanche zone of the photodiode 1 is located at the PN junction formed between the substrate 10 and the lateral surfaces of the localized region 11. This avalanche zone extends into the substrate 10 in a substantially vertical direction. This configuration allows for the efficient collection of photogenerated charges deep within the substrate 10.

[0007] Photodiode 1 further comprises: • a low-doped layer of type P 12 (P doping), with a doping level lower than that of substrate 10, covering the lower face 10b of substrate 10; • a P-type doped support layer 13, with a doping level higher than that of the lightly doped P-layer 12, covering the lightly doped P-layer 12; and • a low-doped region of type N 14 (N ), with a doping level lower than that of the localized region 11, laterally surrounding the upper part 1 of the localized region 11.

[0008] The lightly doped layer P 12 and the lightly doped region N 14 decrease the electric field at the upper and lower parts of the PN junction (by their lower doping level) and consequently reduce the risk of unintended avalanche triggering due to charges generated by silicon surface defects.

[0009] The localized region 11 is formed by etching a trench 15 from the upper face 10a of the substrate 10, this trench 15 passing through the weakly doped N region 14, the substrate 10 and stopping in the weakly doped P layer 12, then filling the trench 15 with N-type doped polycrystalline silicon.

[0010] However, the surfaces delimiting trench 15 have many defects caused by the etching, which generate a dark current in the presence of an electric field.

[0011] Furthermore, US patent 11387379B2 describes an avalanche photodetector for the detection of single photons whose detection principle does not rely on a PN junction. This photodetector is intended not to suffer from the drawbacks of PN junction SPADs, such as the strong dark current caused by silicon defects.

[0012] Fig. 2 is a schematic cross-sectional view of the avalanche photodetector 2 described in this patent. The photodetector 2 comprises a P-type doped semiconductor substrate 20 and a peripheral structure 21 called CDTI (for "Capacitive Deep Trench Isolation"), extending through the semiconductor substrate 20 and surrounding an active region of the semiconductor substrate 20 intended for photon absorption. The peripheral CDTI structure 21 forms a vertical grid structure. It is formed by etching a trench 22 in the substrate 20, coating the lateral walls of the trench 22 with a layer of insulating material 210 (such as a thermal oxide), and then filling the remainder of the trench 22 with a conductive material 211 (such as polycrystalline silicon).

[0013] The peripheral CDTI structure 21 allows the formation of an electron accumulation layer in the P-doped semiconductor substrate 20, at the interface with the insulating material layer 210. In other words, it allows the formation of an inversion layer of the doping type, as in the channel region of a MOS transistor. This inversion layer generates an electric field E that attracts an electron (photogenerated by the absorption of an hv photon) towards the interface between the insulating material layer 210 and the semiconductor substrate 20. This electron collides with the atoms of the semiconductor substrate 20, which releases other electrons and causes the avalanche effect.

[0014] The electron accumulation layer, or inversion layer of the doping type, is equivalent to a thin, heavily N-doped layer. The electric field E near the interface is therefore high and abrupt, so much so that it causes the appearance of a parasitic tunneling current from band to band. This parasitic tunneling current considerably increases the dark current of the photodetector. Summary of the invention

[0015] There is therefore a need to provide a device for the detection of a single photon which exhibits a weak dark current.

[0016] According to a first aspect of the invention, this need is met by providing a single-photon avalanche diode comprising: • a doped semiconductor substrate of a first type of conductivity and having a first face and a second face opposite to the first face; • a doped semiconductor region with a second type of conductivity opposite to the first type of conductivity, extending into the semiconductor substrate from the first face towards the second face; and • a capacitive passivation structure disposed inside a first trench extending into the semiconductor substrate from the first face towards the second face, the capacitive passivation structure extending into contact with the semiconductor region and being configured to form a first layer of electrical charge accumulation in the semiconductor region at the interface with the first trench.

[0017] The first layer of electrical charge accumulation formed in the semiconductor region allows the surface defects created by etching the first trench to be passivated and eliminates any electric field at the interface with the first trench. Thus, these defects do not generate dark currents.

[0018] Preferably, the capacitive passivation structure comprises a first dielectric layer and a first electrically charged layer separated from the semiconductor region by the first dielectric layer.

[0019] Alternatively, the capacitive passivation structure comprises a first dielectric layer and an electrode separated from the semiconductor region by the first dielectric layer.

[0020] In first and second embodiments, the diode further comprises a peripheral isolation structure delimiting an active region of the semiconductor substrate, the peripheral isolation structure extending into the semiconductor substrate from the first face towards the second face.

[0021] Advantageously, the peripheral insulation structure is disposed inside a second trench and configured to form a second layer of electrical charge accumulation in the semiconductor substrate at the interface with the second trench.

[0022] The peripheral insulation structure preferably comprises a second dielectric layer and a second electrically charged layer separated from the active region of the semiconductor substrate by the second dielectric layer.

[0023] It may further comprise a layer of opaque material separated from the active region of the semiconductor substrate by the second electrically charged layer and the second dielectric layer.

[0024] In a third embodiment, the capacitive passivation structure surrounds the semiconductor region which itself surrounds an active region of the semiconductor substrate.

[0025] According to a development of this third embodiment, the capacitive effect passivation structure comprises a layer of opaque material.

[0026] In addition to the characteristics mentioned in the preceding paragraphs, the diode according to the first aspect of the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • the semiconductor region surrounds the passivation structure by capacitive effect; • the diode further includes a contact area for the semiconductor region; • the contact area is located on the capacitive passivation structure in the first trench; • the contact area extends into the semiconductor region; • the diode further includes a contact pad electrically connected to the semiconductor region by the contact zone; • The diode further comprises a first electric field reduction layer disposed on the first face of the semiconductor substrate; and • the diode further includes a second electric field reduction layer disposed on the second face of the semiconductor substrate.

[0027] A second aspect of the invention relates to a method for manufacturing a single-photon avalanche diode, comprising the following steps: • etch a first trench in a doped semiconductor substrate of a first type of conductivity and having a first face and a second face opposite to the first face, the first trench extending from the first face towards the second face; • to form a doped semiconductor region with a second type of conductivity opposite to the first type of conductivity, the semiconductor region being partially delimited by the first trench and extending into the semiconductor substrate from the first face towards the second face; and • form a capacitive passivation structure in the first trench, the capacitive passivation structure being configured to form a first layer of electrical charge accumulation in the semiconductor region at the interface with the first trench.

[0028] In one embodiment, the formation of the semiconductor region comprises the following substeps: • to form by epitaxy a doped semiconductor layer on a lateral surface of the first trench, the doped semiconductor layer comprising doping impurities; and • perform diffusion annealing to laterally diffuse doping impurities from the doped semiconductor layer into the semiconductor substrate.

[0029] In one embodiment, the semiconductor region is formed by gas-phase diffusion doping from a lateral surface of the first trench. BRIEF DESCRIPTION OF THE FIGURES

[0030] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which: • Fig. 1, previously described, schematically represents a single-photon avalanche diode according to the prior art; • the [Fig.2], previously described, schematically represents an avalanche photodetector according to the prior art; • [Fig.3] is a schematic cross-sectional view of a single-photon avalanche diode according to a first embodiment of the invention; • [Fig.4] schematically represents the behavior of the diode in [Fig.3] under reverse bias; • [Fig.5] is a schematic cross-sectional view of a single-photon avalanche diode according to a second embodiment of the invention; • [Fig.6] is a schematic cross-sectional view of a single-photon avalanche diode according to a third embodiment of the invention; • [Fig.7] is a schematic and partial top view of a photodetector comprising a plurality of single-photon avalanche diodes; • Figures 8A to 81 represent steps in a manufacturing process of the single-photon avalanche diode according to [Fig.3].

[0031] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0032] In the following description, the terms "front", "rear", "upper", "lower", "above", "below", "horizontal", "vertical", "lateral", etc. used to describe the position or orientation of certain elements refer to to the orientation of figures 3 to 6 and 8A-8I. Furthermore, unless otherwise specified, the expressions "approximately", "about" and "on the order of" mean to within 5%, or, when they concern absolute or relative angles or angular orientations, to within 5 degrees.

[0033] Figures 3, 5 and 6 represent in schematic cross-sectional view different embodiments of a single-photon avalanche diode 3. The single-photon avalanche diode 3 may be referred to interchangeably as "diode 3", "SPAD 3" or "photodiode 3".

[0034] Common to all these embodiments, diode 3 comprises: • a semiconductor substrate 30 doped with a first type of conductivity, having a first face 30a and a second face 30b opposite to the first face 30a; • a semiconductor region 31 doped with a second type of conductivity opposite to the first type of conductivity, extending in the semiconductor substrate 30 from the first face 30a towards the second face 30b; • a capacitive passivation structure 32 extending in the semiconductor substrate 30 from the first face 30a towards the second face 30b, in contact with the semiconductor region 31.

[0035] The semiconductor substrate 30 (hereinafter referred to simply as "substrate 30") and the semiconductor region 31 are preferably formed of the same semiconductor material, for example silicon.

[0036] The first and second faces 30a-30 of the substrate 30 extend along substantially parallel planes. The first face 30a corresponds (in the orientation of the figures) to the front or upper face of the substrate 30, while the second face 30b corresponds to its rear or lower face. The thickness of the substrate 30 can be between 1 µm and 25 µm, preferably between 5 µm and 20 µm.

[0037] The semiconductor region 31 preferably extends in a direction substantially perpendicular to the first face 30a. It advantageously crosses the substrate 30 (in other words, it extends over the entire thickness of the substrate 30).

[0038] The semiconductor region 31 is a so-called "localized" region, since it occupies only a portion of the volume of the substrate 30. It has a lateral surface 31c, at least part of which is in contact with the substrate 30, thus forming a PN junction that extends deep into the substrate. The PN junction preferably extends in a direction substantially perpendicular to the first face 30a.

[0039] When the substrate 30 is P-doped and the semiconductor region 31 is N-doped, the substrate 30 and the semiconductor region 31 form the anode and cathode of diode 3, respectively. Conversely, when the substrate 30 is N-doped N and the semiconductor region 31 is P-type doped, the substrate 30 and the semiconductor region 31 form respectively the cathode and the anode of the diode 3.

[0040] Diode 3 includes a depletion region, also called a space charge region, which extends laterally on either side of the PN junction. The avalanche of diode 3 occurs in a so-called active part of this depletion region.

[0041] The capacitive passivation structure 32 (hereinafter referred to simply as the “passivation structure 62”) is arranged inside a first trench 33, which partially delimits the semiconductor region 31 and extends into the substrate 30 from the first face 30a towards the second face 30b. As described later with reference to Figures 8C and 8D, the first trench 33 serves to form the semiconductor region 31.

[0042] The passivation structure 32 extends in contact with the semiconductor region 31, preferably in a direction substantially perpendicular to the first face 30a of the substrate. It advantageously traverses the substrate 30 (in other words, it extends over the entire thickness of the substrate 30).

[0043] As described below in relation to [Fig.4], the capacitive passivation structure 32 is configured to form a first layer of electrical charge accumulation in the semiconductor region 31 at the interface with the first trench 33.

[0044] In the illustrated embodiments, the diode 3 further comprises a first electric field reduction layer 34 disposed on the first face 30a of the substrate 30 (i.e., the front face) and / or a second electric field reduction layer 35 disposed on the second face 30b of the substrate 30 (the rear face). The first and second electric field reduction layers 34-35 are each formed of a doped semiconductor material, of type N or P, which has a concentration of doping impurities (respectively of donor or acceptor type) lower than the concentration of doping impurities of the substrate 30. This semiconductor material is preferably silicon.

[0045] Preferably, the first electric field reduction layer 34 (front face) has the same type of conductivity as the substrate 30 (i.e. the first type of conductivity) and the second electric field reduction layer 35 (rear face) has the opposite type of conductivity (i.e. the second type of conductivity).

[0046] Each of the first and second electric field reduction layers 34-35 can have a thickness between 50 nm and 1 pm, for example equal to 1 pm.

[0047] The semiconductor region 31 can extend from the upper face of the first electric field reduction layer 34, through this first layer 34 and the substrate 30, and terminate on the upper face of the second electric field reduction layer 35 or in this second layer 35.

[0048] Similarly, the first trench 33 can extend from the upper face of the first electric field reduction layer 34, cross this first layer 34 and the substrate 30, and stop on the upper face of the second electric field reduction layer 35 or in the second layer 35.

[0049] The diode 3 further comprises at least one first contact pad 361 electrically connected to the substrate 30 and at least one second contact pad 362 electrically connected to the semiconductor region 31. These contact pads 361-362 allow electrical potentials to be applied to the substrate 30 and to the conductive region 31, and thus to bias the PN junction of the diode 3. They are for example made of metal (this is referred to as contact metallization).

[0050] The diode 3 may include several first contact pads 361 distributed so as to uniformize the electrical potential applied to the substrate 30 and the collection of charge carriers, as illustrated in the cross-sectional views of Figures 3 to 5. It may, on the contrary, include only one second contact pad 362 (the semiconductor region 31 being much less extensive than the substrate 30).

[0051] Each first contact pad 361 is preferably disposed on and in contact with the upper face of the first electric field reduction layer 34.

[0052] For each first contact pad 361, a first contact area of ​​the substrate 371, preferably made of a doped semiconductor material with the same type of conductivity as the substrate 30 but with a higher concentration of doping impurities, can extend from the upper face of the first electric field reduction layer 34 towards the substrate 30, in order to minimize the contact resistance (between the first contact pad 361 and the substrate 30). The first contact pad 361 is then electrically connected to the substrate 30 by the first contact area 371. It is advantageously positioned on and in contact with this first contact area 371.

[0053] The second contact pad 362 is preferably located at the same level as the first contact pad(s) 361, that is, at the level of the upper face of the first electric field reduction layer 34 (which here coincides with the upper face of the semiconductor region 31). A second contact area 372 of the semiconductor region, preferably made of a doped semiconductor material with the same type of conductivity as the semiconductor region 31 but with a higher concentration of doping impurities, is advantageously provided to reduce the contact resistance (between the second contact pad 362 and the semiconductor region 31). The second contact pad 362 is then electrically connected to the semiconductor region 31 by the second contact area 372. It is advantageously disposed on and in contact with this second contact area 372.

[0054] The position of this second contact zone 372 (and therefore of the second contact pad 362) differs depending on the embodiment of the diode 3. In the embodiment of [Fig. 3], the second contact zone 372 is located in the first groove 33 on the passivation structure 32. The second contact zone 372 and the passivation structure 32 are thus aligned. In other words, the second contact zone 372 does not extend laterally beyond the passivation structure 32. It is then in contact with the semiconductor region 31 only by its lateral surface. In the embodiments of Figures 5 and 6, the second contact zone 372 extends into the semiconductor region 31. It is then in contact with the semiconductor region 31 by its lateral surface, but also by its lower surface.

[0055] The first and second contact areas 371-372 are preferably made of silicon (doped).

[0056] In the absence of the first electric field reduction layer 34, the first and second contact pads 361-362 are arranged at the front face 30a of the substrate 30 (rather than at the top face of the first electric field reduction layer 34).

[0057] During operation, the cathode of diode 3 is biased at a positive potential V+ and the anode of the photodiode is biased at a negative potential V- (via contact pads 361-362), such that the cathode-anode voltage of the diode is greater than the avalanche voltage (in absolute value). When diode 3 is thus reverse-biased, an electric field appears at the PN junction.

[0058] The operation of diode 3 is described below in relation to [Fig. 4]. This figure shows the diode of [Fig. 3] under reverse bias, but the operation described is common to all embodiments.

[0059] In [Fig. 4], the dashed lines represent equipotential lines in the structure when diode 3 is reverse-biased. In this example, substrate 30 is P-doped and constitutes the anode, while semiconductor region 31 is N-doped and constitutes the cathode. The closer the equipotential lines are to each other, the stronger the electric field.

[0060] As can be seen in the figure, because the doping level (i.e. the concentration of doping impurities) of the first and second electric field reduction layers 34-35 is lower than the doping level of the substrate 30, the equipotential lines are less close together at the upper (at the interface between the first layer 34 and the upper part of the semiconductor region 31) and lower (at the interface between the second layer 35 and the lower part of the semiconductor region 31) parts of the PN junction than at the central part (at the interface between the substrate 30 and the central part of the semiconductor region 31) of the PN junction. As a result, the electric field generated at the upper and lower parts of the PN junction is less intense than the electric field generated at the central part of the PN junction.

[0061] The concentrations of doping impurities in the substrate 30, the semiconductor region 31 and the first and second electric field reduction layers 34-35, as well as the bias voltage of the diode, are preferably chosen so that the electric field at the central part of the PN junction is sufficiently intense so that the avalanche can be triggered by a single photogenerated charge, for example greater than 300 kV / cm over a distance of 100 nm to 500 nm in a direction orthogonal to the PN junction, and so that the electric field at the upper and lower parts of the PN junction is sufficiently weak so that the avalanche cannot be triggered by a single photogenerated charge, for example less than 300 kV / cm.For example, the breakdown voltage (or avalanche voltage) of the diode is between 10 V and 50 V (absolute value), and the reverse bias voltage of the photodiode is greater than its breakdown voltage by a value between 0.5 and 10 V (absolute values). The concentration of doping impurities in the substrate 30 is, for example, between 5 x 10⁻³ cm⁻¹ and 7 x 10⁻³ cm⁻¹. The concentration of doping impurities in the semiconductor region 31 is, for example, between 10 cm⁻¹ and 10 cm⁻¹. The concentration of doping impurities in the first and second electric field reduction layers 34-35 is, for example, less than 5 x 10¹⁶ cm⁻³.

[0062] The first and second electric field reduction layers 34-35 reduce the risk of unintended avalanche triggering at the ends of the PN junction, this risk being linked to edge effects such as the presence of defects on the surface of the semiconductor material. These layers are, however, optional; other solutions can be used to control the risk of unintended avalanche triggering related to edge effects, for example by modifying the shape of the upper and lower ends of the semiconductor region 31, or by reducing the doping level of the semiconductor region 31 at its upper and lower ends.

[0063] The passivation structure 32, for its part, makes it possible to passivate the defects caused by the etching of the first trench 33, by forming a first layer of electrical charge accumulation in the semiconductor region 31, at the interface with the first trench 33. These electrical charges have a polarity corresponding to the type of conductivity of the semiconductor region 31, namely the second type of conductivity. It is therefore a true accumulation layer, and not an inversion layer as in the avalanche photodetector of the prior art. In In the example illustrated by [Fig.4], the semiconductor region 31 is N-doped and the accumulated charges are therefore electrons.

[0064] The electrical charges originate from the surface contact. The accumulation layer allows good electrical continuity between the contact and the rest of the semiconductor region 31 to ensure static but also dynamic equilibrium during avalanche phases.

[0065] The defects are rendered inactive and the electric field at the level of the first trench 33 is reduced. The dark current of the diode 3 is therefore reduced compared to a diode without a capacitive passivation structure, such as that of [Fig. 1].

[0066] The first trench 33 has a bottom and a peripheral lateral surface. The bottom of the first trench 33 is formed here by the second electric field reduction layer 35. The peripheral lateral surface of the first trench 33 is formed, at least in part, by the semiconductor region 31.

[0067] However, in the embodiments of Figures 3, 5 and 6, the semiconductor region 31 and the first trench 33 are arranged so that the peripheral lateral surface of the first trench 33 is entirely constituted by the semiconductor region 31.

[0068] The peripheral lateral surface of the first trench 33 is thus passivated, at least in part, by the first charge accumulation layer. In addition to reducing the dark current, this passivation allows the PN junction to be brought closer to the first trench 33 (without risk of activating the defects) and therefore, more generally, to reduce the lateral dimensions of the diode 3. This reduction in the size of the diode 3 proves particularly advantageous for the purpose of forming a photodetector comprising a diode array.

[0069] The passivation structure 32 can occupy the entire first trench 33, as in the embodiments of Figures 5 and 6, or only part of the first trench 33, as in the embodiment of [Fig.3] (where the second contact zone 372 occupies the upper part of the first trench 33).

[0070] The passivation structure 32 can adopt different configurations.

[0071] In the embodiment of [Fig.3], the passivation structure 32 comprises a first dielectric layer 321 and a first electrically charged layer 322 separated from the semiconducting region 31 by the first dielectric layer 321.

[0072] The first dielectric layer 321 covers the peripheral lateral surface of the first trench 33 and, advantageously, the bottom of the first trench 33. It is preferably formed of an oxide, for example silicon dioxide (SiO2).

[0073] The first charged layer 322 contains electric charges of opposite polarity to those desired in the semiconductor region 31. It is preferably formed of a dielectric material, for example silicon nitride (Si3N4) in the case of a positively charged layer, alumina (Al2O3) or tantalum pentoxide (Ta2O5) in the case of a negatively charged layer. The surface charge density of the first charged layer 322 at the interface with the first dielectric layer 321 is preferably greater than 1012 cm².

[0074] The first charged layer 322 advantageously occupies the remaining part of the first trench 33. It thus constitutes the core of the passivation structure 32, while the first dielectric layer 321 constitutes the envelope of the passivation structure 32.

[0075] An advantage of this embodiment is that the passivation structure 32 does not require electrical contact on the front face of the substrate 30, which allows the second contact pad 362 and the second contact zone 372 to be formed instead (see [Fig. 3]). The diode 3 can then have a symmetrical configuration with respect to the passivation structure 32. Forming the second contact zone 372 in the first trench 33 limits the contact area on the effective surface of the diode 3, which tends to avoid electric field peaks and therefore unwanted avalanche triggering on the surface.

[0076] In the embodiment of [Fig. 5], the passivation structure 32 comprises the first dielectric layer 321 described above and an electrode 322' separated from the semiconductor region 31 by the first dielectric layer 321, in the manner of a MOS (metal-oxide-semiconductor) gate structure. The electrode 322' is an electrically conductive layer, for example, made of doped polycrystalline silicon or metal. Analogously to the embodiment of [Fig. 3], the first dielectric layer 321 and the electrode 322' can constitute the outer shell and the core of the passivation structure 32, respectively.

[0077] During operation of the diode 3, a voltage is applied between the electrode 322' and the semiconductor region 31 (in addition to the PN junction bias voltage) in order to form the first charge accumulation layer. To this end, the diode 3 includes a third contact pad 363 electrically connected to the electrode 322' of the passivation structure 32. This third contact pad 363 is preferably located on and in contact with the upper face of the electrode 322'. It is advantageously situated at the same level as the first and second contact pads 361-362.

[0078] Common to the embodiments of Figures 3 and 5, the semiconductor region 31 is ring-shaped (or tube-shaped) and the passivation structure 32 occupies the interior space of this ring. In other words, the semiconductor region 31 surrounds the passivation structure 32. The inner lateral surface of the semiconductor region The conductive region 31, in contact with the passivation structure 32, is therefore peripheral. The ring formed by the semiconducting region 31 preferably has a rectangular cross-section (in the plane of the figures) and a central axis substantially perpendicular to the first face 30a.

[0079] Furthermore, the semiconductor region 31 and the passivation structure 32 are themselves surrounded by a so-called active region 30' of the substrate 30. The lateral surface 31c of the semiconductor region 31, which is external and in contact with the active region 30' of the substrate 30, is therefore peripheral. The active region 30' of the substrate 30 is designed for the absorption of photons.

[0080] The semiconductor region 31 and the passivation structure 32 are advantageously arranged in the center of the active region 30' of the substrate 30.

[0081] Furthermore, the diode 3 advantageously comprises a peripheral isolation structure 38 delimiting the active region 30' of the substrate 30. The peripheral isolation structure 38 extends into the substrate 30 from the first face 30a towards the second face 30b, preferably in a direction substantially perpendicular to the first face 30a. It advantageously traverses the substrate 30.

[0082] The peripheral insulation structure 38 can also extend through the first electric field reduction layer 34 and / or the second electric field reduction layer 35, as illustrated in the figures.

[0083] The peripheral insulation structure 38 is advantageously arranged inside a second trench 39 and configured to form, by capacitive effect, a second layer of electrical charge accumulation in the substrate 30, at the interface with this second trench 39. Thus, the defects generated by etching the second trench 39, for the purpose of electrical and / or optical insulation of the diode 3, are passivated. In the example illustrated in [Fig. 4], the substrate 30 is P-doped, so the accumulated charges are holes.

[0084] Such a peripheral insulation structure 38 can be called a capacitive deep trench insulation structure or CDTI structure (for "capacitive deep trench insulation" in English).

[0085] In a manner analogous to the passivation structure 32, the peripheral insulation structure 38 may comprise: • a second dielectric layer 381 (preferably made of an oxide such as SiO2); and • a second electrically charged layer 382 (preferably in a dielectric such as Si3N4, Al2O3 or Ta2O5) or a second electrode 382' (in metal or doped polysilicon) separated from the active region 30' of the substrate 30 by the second dielectric layer 381.

[0086] The second trench 39 has an annular shape (to surround the active region 30' and the semiconducting region 31). The second dielectric layer 381 covers a peripheral lateral surface of the second trench 39, formed by the active region 30' of the substrate 30. The second electrically charged layer or the second electrode occupies all or part of the remainder of the second trench 39.

[0087] The peripheral insulation structure 38 may further comprise a layer of opaque material 383 separated from the active region 30' by the second electrically charged layer 382 or the second electrode 382' and the second dielectric layer 381. This layer of opaque material 383, preferably metallic, renders the peripheral insulation structure 38 opaque, thereby preventing photons emitted in the avalanche zone of diode 3 from propagating to one or more neighboring diodes 3 and triggering an avalanche. Thus, the peripheral insulation structure 38 is configured to reduce optical crosstalk, in addition to limiting electrical charge leakage (electrical insulation). An opaque material layer is defined as a layer whose transmission factor is less than 20% for wavelengths between 400 nm and 1100 nm.

[0088] Alternatively, the peripheral isolation structure 38 can be a deep trench isolation structure, or DTI structure (for "deep trench isolation" in English), in other words a structure devoid of the functions of passivation of the sides of the diode 3 by capacitive effect and of limitation of optical crosstalk.

[0089] Figure 6 shows an embodiment of the diode 3 in which the capacitive passivation structure 32 (arranged inside the first trench 33) and the semiconductor region 31 both have an annular (or tubular) shape. The passivation structure 32 surrounds the semiconductor region 31, which itself surrounds the active region 30' of the substrate 30. In other words, the passivation structure 32 is not located at the center of the diode 3, but at its periphery. The passivation structure 32 is therefore referred to as peripheral.

[0090] The peripheral passivation structure 32 may comprise, analogously to the embodiment of [Fig. 3], the first dielectric layer 321 and the first electrically charged layer 322 (separated from the semiconductor region 31 by the first dielectric layer 321). Advantageously, it further comprises a layer of opaque material 323 separated from the semiconductor region 31 by the first electrically charged layer 322 and the first dielectric layer 321, to reduce optical crosstalk with one or more neighboring diodes.

[0091] The peripheral passivation structure 32 can alternatively comprise the first dielectric layer 321 and the first electrode 322', as in the embodiment of [Fig. 5]. Optical crosstalk between neighboring diodes is then reduced by choosing an opaque (conductive) material (such as a metal) to form the first electrode 322'.

[0092] In both cases, the peripheral passivation structure 32 then fulfills the electrical insulation function of the peripheral insulation structure 38 described in relation to Figures 3 and 5 and, advantageously, the optical crosstalk limitation function (in the presence of an opaque material layer).

[0093] This embodiment has the advantage of only having to form one (annular) trench, instead of two.

[0094] The diode 3 may here only have a single first contact pad 361 electrically connected to the substrate 30, preferably via a first contact area 371. This first contact pad 361 is advantageously located in the center of the upper face of the diode 3 (upper face of the first electric field reduction layer 34 or upper face of the active portion of the substrate 30).

[0095] Several diodes 3 according to any of the embodiments described above can be combined in a photodetector in the form of an array. Each diode 3 then forms a pixel of the array, called a SPAD pixel. The different diodes 3 share the same substrate 30. Each diode 3 comprises an active region 30' of the substrate 30, a semiconductor region 31 in contact with this active region 30' (thus forming the PN junction), and a capacitive passivation structure 32. The active region 30' of the substrate 30 is delimited either by the peripheral isolation structure 38 of Figures 3 and 5, or by the peripheral passivation structure 32 of [Fig. 6]. Two neighboring pixels (in a row or column of the array) can share a portion of the opaque material layer 323, 383, which serves as an optical insulator.

[0096] Figure 7 shows, in top view, an example of a photodetector comprising a matrix of diodes 3 or SPAD pixels, here of which there are four. The diodes 3 are in this example in the configuration described in relation to Figure 3. The active region 30' preferably has a square shape in top view and measures, for example, between 2 pm and 6 pm on each side. Each diode 3 comprises four first semiconductor areas 731 (and four first contact pads) located in the four corners of the active region 30', in order to uniformize the electric field and charge collection.

[0097] In addition to the diode matrix 3, the photodetector may include a circuit for biasing the diodes 3 (at a voltage higher than their avalanche voltage), a reading circuit configured to detect the avalanche of one or more diodes 3 (and in particular a voltage pulse generated at the output of the diode), as well as a quenching circuit whose function is to interrupt The avalanche of the diode(s) once it is triggered. These auxiliary circuits have not been shown in the figures and will not be detailed, as the diode embodiments described above are compatible with the auxiliary circuits equipping known SPAD photodetectors.

[0098] For diodes 3 according to [Fig. 3] or [Fig. 5], the read circuit and the extinguishing circuit are advantageously electrically connected to the second contact pad 362 (or to the second contact area 372) of each diode 3, and therefore to the semiconductor region 31, since the semiconductor region 31 constitutes the electrode with the lowest capacitance, due to its smaller surface area compared to the other electrode or doping areas of the diode. For diodes 3 according to [Fig. 6], the read circuit and the extinguishing circuit are advantageously electrically connected to the first contact pad 361 (or to the first contact area 371) of each diode 3.

[0099] The auxiliary circuits of the photodetector can be assembled in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit. This integrated circuit is advantageously bonded to the diode matrix 3, preferably on the front side of the substrate 30 (for illumination of the diodes on the rear side).

[0100] A manufacturing process for diode 3 will now be described. Figures 8A to 81 schematically represent, in cross-sectional view, steps SI to S9 of a preferred embodiment of the manufacturing process for obtaining diode 3 of [Fig.3].

[0101] Figure 8A represents an SI step of etching the first trench 33 in the substrate 30, through an etching mask 80. The first trench 33 has, for example, a diameter between 250 nm and 1 pm and a depth between 5 pm and 25 pm. The etching mask 80 is preferably a hard mask, for example made of oxide.

[0102] The first trench 33 is preferably etched from the top face of a stack comprising the first electric field reduction layer 34, the substrate 30, and the second electric field reduction layer 35 (not shown). The stack may also include a support layer / substrate (not shown), from which the other layers 34, 30, 35 are formed, for example by epitaxy. The first trench 33 passes through the first electric field reduction layer 34 and the substrate 30 and is interrupted on or within the second electric field reduction layer 35.

[0103] Steps S2 and S3 of Figures 8B and 8C relate to the formation of the semiconducting region 31, from the first trench 33.

[0104] In step S2 of [Fig. 8B], a doped semiconductor layer 81 (of the second type of conductivity) is formed by epitaxy on at least part of the peripheral lateral surface of the first trench 33, and preferably on the entire peripheral lateral surface of the first trench 33. Advantageously, the etching mask 80 is retained at this step to prevent the growth of the doped conductive layer 81 on the upper face of the stack (this is referred to as selective epitaxy). The doped semiconductor layer 81 has, for example, a thickness between 50 nm and 200 nm. Its concentration of doping impurities is advantageously less than 5 x 10¹⁹ cm³ to avoid obtaining too strong an electric field in the PN junction.

[0105] Then, in step S3 of [Fig.8C], a diffusion anneal is performed to diffuse the doping impurities of the doped semiconductor layer 81 laterally into the substrate 30, thus obtaining the semiconductor region 31. Preferably, the doping impurities are diffused over a distance d between 100 nm and 1 pm, this distance being measured from the peripheral lateral surface of the first trench 33.

[0106] Thus, when the doped semiconductor layer 81 covers the entire peripheral lateral surface of the first trench 33, the semiconductor region 31 is ring-shaped around the first trench 33 (this ring having a cross-section of width l=d between 100 nm and 1 pm).

[0107] Diffusion annealing is preferably carried out at a temperature between 800 °C and 1100 °C. Its duration can be between 10 s and 90 min.

[0108] Diffusion annealing has the effect of smoothing the doping of the semiconductor region 31 to soften the electric field (thus avoiding the band-to-band tunnel effect) and of moving the depletion zone of the PN junction away from the etching zone of the first trench 33.

[0109] In an embodiment of steps S2 and S3, the semiconductor region 31 is formed by gas-phase diffusion doping from the lateral surface of the first trench 33.

[0110] Figure 8D represents an optional step S4 of the manufacturing process, consisting of forming, at the interface between the semiconductor region 31 and the first trench 33, an additional doped semiconductor layer 82 (called the interface layer), in order to reinforce the passivation of defects caused by the etching of the first trench 33 (said passivation being obtained by the first charge accumulation layer formed by the passivation structure 32). The additional doped conductive layer 82 has, for example, a thickness of between 25 nm and 200 nm. Its concentration of doping impurities is advantageously greater than or equal to 51018cm3.

[0111] Steps S5 and S6 of Figures 8E and 8F relate to the formation of the capacitive effect passivation structure 32.

[0112] In step S5 of [Fig.8E], the first dielectric layer 321 is formed on at least said part of the peripheral lateral surface of the first trench 33, and preferably on the entire peripheral lateral surface of the first trench 33. The first dielectric layer 321 is preferably formed by thermal oxidation of the material of the semiconducting region 31. Its thickness is, for example, between 1 nm and 5 nm.

[0113] Next, in S6 (cf. [Fig.8F]), the remaining part (the core) of the first trench 33 is filled with an electrically charged material to form the first charged layer 322. The technique used may be atomic layer deposition (or ALD), which is a conformal deposition technique.

[0114] After removal of the etching mask 80, the passivation structure 32 is complete and can be used as is. The process then subsequently includes a step of forming the second contact zone 372 in the semiconductor region 31.

[0115] However, it is possible to go further in the integration to minimize the surface area occupied by the diode, by forming the second contact area 372 in the first trench 33.

[0116] Steps S7 to S9 of figures 8G to 81 are thus related to the formation of the second contact zone 372 at the top of the first trench 33.

[0117] After step S6 of filling the first trench 33 with the electrically charged material, the process includes a step S7 represented by [Fig. 8G] and consisting of etching an upper portion of the first charged layer 322 (this is referred to as partial recessing). The etched portion of the first charged layer 322 can have a thickness between 50 nm and 200 nm. The etching of the first charged layer 322 is preferably selective with respect to the first dielectric layer 321.

[0118] Then, in S8 (cf. [Fig.8H]), the first dielectric layer 321 is etched in the upper part of the first trench 33, until (a part of) the lateral surface of the semiconducting region 31 is exposed. The etching of the first dielectric layer 321 is preferably selective with respect to the semiconducting region 31. Advantageously, the hard mask 80 is removed simultaneously (the first dielectric layer 321 and the hard mask 80 can in particular both be in an oxide, such as SiO2).

[0119] Finally, in S9 (see [Fig. 81]), a doped semiconductor material (such as doped polycrystalline silicon) is deposited in the upper part of the first trench 33 (emptied of the electrically charged material), so as to plug the first trench 33 and form the second contact zone 372. The doped semiconductor material can be deposited so as to form a flat surface with the top face of the stack (or the top face of the substrate, in the absence of the first electric field reduction layer 34). Alternatively, the deposit can form an excess thickness on the top face of the stack, in which case a planarization operation (e.g., chemical polishing) is carried out to obtain a flat surface with the top face of the stack.

[0120] The diode 3 of [Fig. 5] can be fabricated by replacing the electrically charged material with an electrically conductive material (e.g., metal, doped polysilicon) to form the electrode 322' in step S6 of [Fig. 8F] and omitting the subsequent steps S7-S9. As an alternative, the process will include a step for forming the second contact zone 372 in the semiconductor region 31, for example, by implanting doping impurities.

[0121] The semiconductor region 31 and the capacitive passivation structure 32 (obtained according to any of the methods described above) together form a structure referred to as a diffused capacitive deep trench or CDTC (for "diffused capacitive deep trench" in English).

Claims

Demands

1. Single-photon avalanche diode (3) comprising: - a semiconductor substrate (30) doped with a first type of conductivity and having a first face (30a) and a second face (30b) opposite the first face; - a peripheral insulation structure (38) delimiting an active region (30') of the semiconductor substrate (30), the peripheral insulation structure (38) extending in the semiconductor substrate (30) from the first face (30a) towards the second face (30b); - a semiconductor region (31) doped with a second type of conductivity opposite to the first type of conductivity, extending in the active region of the semiconductor substrate (30) from the first face (30a) towards the second face (30b);and - a capacitive passivation structure (32) disposed inside a first trench (33) which extends into the semiconductor region (31), the capacitive passivation structure (32) extending in contact with the semiconductor region (31) and being configured to form a first layer of electrical charge accumulation in the semiconductor region (31) at the interface with the first trench (33).

2. Diode (3) according to claim 1, wherein the capacitive passivation structure (32) comprises a first dielectric layer (321) and a first electrically charged layer (322) separated from the semiconductor region (31) by the first dielectric layer (321).

3. Diode (3) according to claim 1, wherein the capacitive passivation structure (32) comprises a first dielectric layer (321) and an electrode (322') separated from the semiconducting region (31) by the first dielectric layer (321).

4. Diode (3) according to claim 1, wherein the peripheral insulation structure (38) is disposed inside a second trench (39) and configured to form a second layer of electrical charge accumulation in the semiconductor substrate (30) at the interface with the second trench (39).

5. Diode (3) according to claim 4, wherein the peripheral insulation structure (38) comprises a second dielectric layer (381) and a second electrically charged layer (382) separated from the active region (30') of the semiconductor substrate (30) by the second dielectric layer (381).

6. Diode (3) according to claim 5, wherein the peripheral insulation structure (38) further comprises a layer of opaque material (383) separated from the active region (30') of the semiconductor substrate (30) by the second electrically charged layer (382) and the second dielectric layer (381).

7. Diode (3) according to any one of claims 1 to 6, wherein the semiconductor region (31) surrounds the capacitive passivation structure (32).

8. Diode (3) according to any one of claims 1 to 7, further comprising a contact area (372) of the semiconductor region (31), the contact area (372) being disposed on the capacitive passivation structure (32) in the first trench (33).

9. Method of manufacturing a single-photon avalanche diode (3), comprising the following steps: - etching a first trench (33) in a semiconductor substrate (30) doped with a first type of conductivity and having a first face (30a) and a second face (30b) opposite to the first face, the first trench extending from the first face towards the second face; - after etching the first trench (33), forming a semiconductor region (31) doped with a second type of conductivity opposite to the first type of conductivity, the semiconductor region (31) being formed from the first trench, delimited in part by the first trench (33) and extending in the semiconductor substrate (30) from the first face (30a) towards the second face (30b);- form a capacitive passivation structure (32) in the first trench (33), the capacitive passivation structure (32) being configured to form a; first layer of accumulation of electrical charges in the semiconducting region (31) at the interface with the first trench (33); the single-photon avalanche diode (3) further comprising a peripheral isolation structure (38) delimiting an active region (30') of the semiconductor substrate (30), the peripheral isolation structure (38) extending into the semiconductor substrate (30) from the first face (30a) towards the second face (30b).

10. A method according to claim 9, wherein the formation of the semiconductor region (31) comprises the following substeps: - to form by epitaxy a doped semiconductor layer (81) on a lateral surface of the first trench (33), the doped semiconductor layer (81) comprising doping impurities; and - perform a diffusion anneal to make the doping impurities of the doped semiconductor layer (81) diffuse laterally into the semiconductor substrate (30).

11. Method according to claim 9, wherein the semiconductor region (31) is formed by gas-phase diffusion doping from a lateral surface of the first trench (33).

Images