Method for manufacturing a memory device

Abstract

Title: Method for manufacturing a memory device. The invention relates to a memory device (1) comprising a plurality of memory points (1000a, 1000b). The device comprises a plurality of first electrodes (120a, 120b) and a plurality of second electrodes (220a, 220b), each second electrode (220a, 220b) being at least partially adjacent to a first electrode (120a, 120b). The device is characterized in that it comprises an active layer (150) extending continuously between the plurality of first electrodes and the plurality of second electrodes. Furthermore, each first electrode (120a, 120b), a second electrode (220a, 220b) located at least partially opposite said first electrode (120a, 120b), and a portion of the active layer (150) extending between said first electrode (120a, 120b) and said second electrode (220a, 220b) together form a memory point (1000a, 1000b). See Figure 2K for abbreviations.

Description

Title of the invention: Method for manufacturing a memory device technical field

[0001] The present invention relates to non-volatile resistive memories integrated into an interconnect network, for example of a CMOS (Complementary Metal Oxide Semiconductor) type technology. It can be applied to different types of resistive memories and in particular to oxide-based resistive memories (OxRAM), ferroelectric-based resistive memories (FeRAM), conductive bridge resistive memories (CBRAM). STATE OF THE ART

[0002] As illustrated in [Fig.1], the memory points 1000' of non-volatile resistive memories are classically made up of three stacked elements: a lower conductive electrode 120', an active layer 150' whose properties allow a change of state in order to store information, and a top conductive electrode 220'.

[0003] In the case of a resistive memory of the OxRAM type, the active layer is based on a dielectric. The application of an electric field across the terminals of the lower and upper electrodes makes it possible to break or form a conductive filament within the dielectric layer and thus to switch from a state of high resistivity to a state of low resistivity of the dielectric layer, these two states corresponding respectively to the information "0" (or state "OFF") and to the information "1" (or state "ON") of the memory.

[0004] The integration of such a memory point into an interconnection network is commonly based on a mesa-type structure in which the memory point is formed according to a pattern produced by lithography. The connections to the electrodes are commonly made by vias 110', 210' connected to metal lines constituting the interconnection network. Furthermore, the mesa structure thus produced is then encapsulated by a stack of dielectric layers and then planarized in order to be electrically insulated and to allow for higher levels of interconnection. This interconnection network preferably forms part of the layers designated as BEOL, an acronym for the English term "Back End Of Line."

[0005] In order to increase the density of memory points in each of the memory planes, the aim is to reduce the dimensions of the memory points and / or decrease their spacing. One of the major obstacles in this regard is the dimension The minimum achievable resolution for creating a mesa-type structure is currently determined by the size of the lithography pattern. However, the most advanced lithography techniques, using extreme ultraviolet (EUV) immersion lithography and DRIE (Dry Reactive Ion Etching) plasma etching, offer a resolution of approximately 60 nm at best for defining mesa-type structures, i.e., isolated points. The resulting memory point densities are insufficient, and there is a need to overcome this dimensional limitation to create higher-performance memory devices and / or devices with smaller overall dimensions.

[0006] An objective of the present invention is therefore to provide a solution for improving the density of memory points within memory devices. SUMMARY

[0007] To achieve this objective, a first object of the invention relates to a memory device comprising a plurality of memory points, the device comprising a plurality of first electrodes and a plurality of second electrodes, each second electrode being at least partially opposite a first electrode, characterized in that it further comprises an active layer extending continuously between the plurality of first electrodes and the plurality of second electrodes, and in that: • each first electrode, • a second electrode located at least partially opposite said first electrode, and • a portion of the active layer extending between said first electrode and said second electrode together form a memory point.

[0008] A second object of the invention relates to a method for manufacturing a memory device comprising a plurality of memory points, the method comprising the following steps: • To form a plurality of first electrodes, • Form an active layer on each of the first electrodes, the active layer being continuous, Forming a plurality of second electrodes on the active layer, each second electrode being at least partially opposite a first electrode, each first electrode, a second electrode being at least partially opposite said first electrode, and a portion of the active layer extending between said first electrode and said second electrode together forming a memory point.

[0009] Since the active layer is common to the plurality of memory points, the memory points thus formed do not require lithography and etching steps to form the active layer, technological steps whose resolution is currently limited to 60 nm. Existing techniques, on the other hand, make it possible to form electrodes with lithography and etching steps having a resolution below 40 nm. Thus, the process according to the invention can make it possible to significantly increase, typically doubling, the density of memory points within a memory device.

[0010] Furthermore, eliminating the need for engraving to form the memory dot pattern reduces edge defects caused by this manufacturing step. These defects, which are poorly controlled in the prior art, can lead to a deterioration in the performance of the memory device. The process according to the invention therefore makes it possible to produce a memory device with improved performance compared to the prior art.

[0011] The fact that the active layer is continuous and common to several memory locations eliminates the need for lithography and etching steps that could damage the active layer and ultimately lead to reduced memory device performance. During the development of the present invention, it was observed that this shared active layer does not hinder the proper functioning of each individual memory location.

[0012] According to a preferred embodiment of the device according to the invention, the latter comprises a stack comprising, stacked in a so-called stacking direction, in this order: • A first support layer having a top face, the first support layer comprising a plurality of first holes each extending from its top face, each first hole housing: i. A first metallic via, ii. A first electrode of the plurality of first electrodes, each first electrode surmounting a distinct first metallic via, • The active layer, above the top surface of the first support layer.

[0013] According to a preferred embodiment of the process according to the invention, the step of forming the plurality of first electrodes comprises the following steps: • Provide a first support layer, having a top face and a bottom face opposite each other, the first support layer comprising a plurality of first holes, each extending from its upper face and opening onto its lower face, • Form a first electrode in each first hole of the plurality of first holes, the active layer being formed on the upper face of the first support layer, the process further comprising a step of forming in each first hole a first metallic via, the first electrode being in contact with the first metallic via.

[0014] The memory points thus formed require only the formation of holes in the first and second support layers. Existing techniques make it possible to form holes such as those formed in this advantageous embodiment of the process according to the invention with a resolution below 40 nm.

[0015] The first holes and the second holes also preferably each have a continuous profile along the stacking direction.

[0016] The advantages presented with reference to the method according to the second aspect of the invention apply mutatis mutandis to the device according to the first aspect of the invention. BRIEF DESCRIPTION OF THE FIGURES

[0017] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0018] [Fig.1] Fig.1 represents memory points according to the prior art within an interconnection network.

[0019] [Fig.2A] Figures 2A to 2M illustrate one embodiment of the process according to the invention.

[0020] [Fig.2B]

[0021] [Fig.2C]

[0022] [Fig.2D]

[0023] [Fig.2E]

[0024] [Fig.2F]

[0025] [Fig.2G]

[0026] [Fig.2H]

[0027] [Fig.2I]

[0028] [Fig.2J]

[0029] [Fig.2K]

[0030] [Fig.2L]

[0031] [Fig.2M]

[0032] [Fig.3] Figure [Fig.3] illustrates an embodiment in which two memory points share an electrode and a via.

[0033] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the relative dimensions and thicknesses are not representative of reality. DETAILED DESCRIPTION

[0034] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0035] According to a preferred embodiment, the stack further comprises, on the active layer, a second support layer comprising a plurality of second holes passing through it and each opening onto the active layer, each second hole housing: • A second metallic viaduct, • A second electrode from the plurality of second electrodes, said second electrode being disposed between the second metallic via and the active layer, and being at least partly opposite a first electrode from among the plurality of first electrodes.

[0036] According to a preferred embodiment, the first holes each have a continuous profile along the stacking direction projected onto any plane including the stacking direction. According to a preferred embodiment, the second holes each have a continuous profile along the stacking direction projected onto any plane including the stacking direction.

[0037] According to one example, each second electrode is in direct contact with the active layer.

[0038] According to one embodiment, at least one first electrode among the plurality of first electrodes is located at least partly opposite at least two second electrodes.

[0039] According to an alternative embodiment, each of the first electrodes is located opposite a single second electrode.

[0040] According to one example, the first metallic via and the first electrode contained in the same first hole are made of different materials. According to another example, the second metallic via and the second electrode contained in the same first hole are made of different materials.

[0041] According to one example, the first metallic via is based on one of the following materials: W, WN, Ru, Co, Ni, Cu, a combination of layers comprising these materials, or an alloy of these materials. According to another example, the second metallic via is based on one of the following materials: W, WN, Ru, Co, Ni, Cu, a combination of layers comprising these materials, or an alloy of these materials.

[0042] According to one example, the first electrode is based on one of the following materials: TiN, Ti, TaN, W, WN, Ru, C, Si, Co, Ni, a combination of layers comprising these materials, or an alloy of these materials. According to another example, the second electrode is based on one of the following materials: TiN, Ti, TaN, W, WN, Ru, C, Si, Co, Ni, a combination of layers comprising these materials, or an alloy of these materials.

[0043] According to one example, the device further includes a protective layer between the active layer and the second support layer.

[0044] According to one example, the active layer is based on a dielectric, for example one of the following materials: • SiOx with x equal to 1 or 2, such that SiO2, • HfOx with x equal to 1 or 2, such that HfO2, • A12O3, • TiO2, • Ta2O5, • ZrO2, • an alloy of these elements.

[0045] According to one example, the active layer is based on a ferroelectric material, for example one of the following, HfxZri XO2 with 0 <x<l, du HfO2 dopé Si, de l’AlScN et un titano-zirconate de plomb (PZT). Dans le cas d’une couche active à base de HfO2 dopé Si, le Si est de préférence présent dans une concentration inférieure ou égale à 10% atomique, de préférence sensiblement égale à 1% atomique.

[0046] According to one example, the active layer comprises a solid electrolyte, for example based on one of: silver-doped germanium sulfide and copper-doped germanium sulfide.

[0047] According to an advantageous example, each first electrode is flush with the upper face of the first support layer.

[0048] According to one embodiment, the device further comprises a plurality of first secondary electrodes and a plurality of second secondary electrodes, each second secondary electrode being at least partially located opposite a first secondary electrode, the device further comprising an active layer secondary extending continuously between the plurality of first secondary electrodes and the plurality of second secondary electrodes, and: • each first secondary electrode, • a second secondary electrode located at least partially opposite said first secondary electrode, and • a portion of secondary active layer extending between said first secondary electrode and said second secondary electrode together form a secondary memory point.

[0049] Two elements are understood to be isolated from each other if they are not in direct contact and are separated from each other by a medium or material having an electrical resistivity greater than 10⁶ Qm

[0050] According to an advantageous embodiment of the process according to the invention, it further comprises the following steps: • To form a second support layer on the active layer, the second support layer comprising a plurality of second holes traversing the second support layer and each opening onto the active layer, each second hole being at least partially opposite a different first electrode, • Form in each second hole of the plurality of second holes a second electrode of the plurality of second electrodes and a second metallic via, the second electrode being in contact with the second metallic via.

[0051] According to an advantageous embodiment, the first support layer comprises at least one first contact hole, the second support layer comprises at least one second contact hole, the first contact hole and the second contact hole being at least partially opposite each other, the method further comprising the following steps: • Form a first metallic contact via in the first hole, • Form a second metallic contact in the second hole, the first via metallic contact and the second via metallic contact being in electrical conduction.

[0052] Two elements are understood to be in electrical conduction when they are in direct contact or in contact via conductive layers typically having a resistivity of less than 150 pQ.cm. The first via metallic contact and the second via metallic contact are preferably in direct contact. According to one embodiment, the first via metallic contact and the second via metallic contact are in contact via at least one metallic layer, typically a first contact electrode and / or a second contact electrode.

[0053] According to one example, the first metallic via and the first electrode located in the same first hole are formed during the same deposition step.

[0054] According to an advantageous example, the formation of the second support layer comprises a step of depositing the support layer and a step of forming the plurality of first holes in the support layer, the process further comprising, after the formation of the second support layer on the active layer, and before the formation in each second hole of the second metallic via and the second electrode, a step of processing the active layer through the second holes, the active layer processing step preferably taking place at one of the following times: • Before the formation of the second support layer, • After the deposition of the second support layer and before the formation of the plurality of first holes, • After the formation of the plurality of first holes.

[0055] According to one example, the process further comprises, after the formation of the active layer, and before the formation of the second support layer, the formation of a protective layer on an upper face of the active layer.

[0056] According to one example, the process further comprises, after the formation of the second support layer on the active layer, a removal of portions of the apparent protective layer through the second holes.

[0057] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0058] A layer may also be composed of several sub-layers of the same material or of different materials.

[0059] A substrate, layer, or device "based on" a material M is understood to mean a substrate, layer, or device comprising only that material M or that material M and possibly other materials, for example, alloying elements, impurities, or dopant elements. Thus, a material based on a III-N material may comprise a III-N material with added dopants.

[0060] Selective etching with respect to or etching exhibiting selectivity with respect to means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. The selectivity is the ratio between the etching speed of material A and the etching speed of material B. The selectivity between A and B is denoted SA:B.

[0061] A frame of reference, preferably orthonormal, comprising the axes X, Y, Z is shown in figures 2A to 2K. The Z direction may be designated as the “stacking direction”.

[0062] In this patent application, the terms thickness for a layer and height for a structure or device will preferably be used. Height is measured perpendicular to the horizontal XY plane. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along Z when it extends mainly along the horizontal XY plane, and a projecting element, for example an insulation trench, has a height along Z. The relative terms "on," "under," and "below" preferably refer to positions measured along the Z direction.

[0063] The terms "approximately", "about", "in the order of" mean "within 10%, preferably within 5%".

[0064] An embodiment of the method according to the invention will now be described with reference to Figures 2A to 2K. For clarity, these figures illustrate the obtaining of only two memory points. Naturally, these steps can allow for the simultaneous obtaining of numerous memory points from the same first support layer, the same active layer, and the same second support layer.

[0065] Figure 2A illustrates the provision of a stack comprising, in particular, a first support layer 10. This first support layer 10 can rest, as illustrated, on any suitable support 30 for the intended applications. It is typically a line comprising metallic connecting elements 35a, 35b, of the "end-of-line" or "BEOL" type. This support 30 can be described as the lower metallic line or the lower interconnection line. The support 30 may also include other metallic layers. Furthermore, the support 30 may include transistors.

[0066] The first support layer 10 has a lower face 12 opposite this support 30, as well as a top face 11 opposite the lower face 12. As illustrated in [Fig.2B], holes called first holes 15a, 15b are then formed in the first support layer 10 from its top face 11.

[0067] Preferably, the first holes 15a, 15b pass through the first support layer 10 through its entire thickness ei0 in the Z direction. Advantageously, each first hole 15a, 15b opens onto a metallic interconnection 35a, 35b of the lower metallic line 30. It is also conceivable that, initially, the first holes 15a, 15b do not open onto the lower face 12 of the first support layer 10. It will be possible, after the formation of the memory points 1000a, 1000b, to polish or grind (for example by chemical-mechanical polishing - CMP) this lower face 12 in order to bring the first metallic vias 110a, 110b, whose formation will be described later, to the surface. The assembly with the lower metallic line 30 then takes place after this polishing step.

[0068] The first holes 15a, 15b can, for example, be formed by lithography and etching. Preferably, this is an anisotropic etching such as reactive ion etching or plasma etching.

[0069] The profile of the first holes 15a, 15b is preferably continuous. In particular, the profile of the first holes 15a, 15b is continuous along a direction perpendicular to the upper face 11 of the first support layer 10 (here the stacking direction Z). A continuous profile is understood to be one that does not exhibit an abrupt change in cross-section in the horizontal XY plane along the stacking direction Z. Such a change can, for example, be called a step-off. Such a step-off is obtained, for example, when a first layer is etched according to a certain pattern, and then a second layer is deposited on the first layer according to another pattern. In other words, each first hole 15a, 15b defines a continuous surface, this surface corresponding to the boundary formed by the first support layer 10 of said first hole 15a, 15b.In particular, by projecting the profile onto any plane perpendicular to the horizontal XY plane, this profile is continuous along the stacking direction Z. Thus, by tracing the first hole 15a, 15b from the upper face 11 to the lower face 12, a curve, preferably a straight line, is defined. This curve has no angles. This straight line can be vertical or, preferably, oblique in a plane containing Z, as illustrated in the figures. Advantageously, the surface defined by each first hole 15a, 15b in the first support layer 10 exhibits rotational symmetry about an axis parallel to the stacking direction Z.

[0070] The profile of the first holes 15a, 15b may or may not be constant along the stacking direction Z. A hole with a constant profile is one whose cross-section in the horizontal XY plane is constant along the entire height of the hole along Z. Conversely, a hole with a non-constant profile is one whose cross-section in the horizontal XY plane varies along the height of the hole.

[0071] The first holes 15a, 15b each have, in the horizontal XY plane, a maximum dimension Li5. In the typical case of holes having a circular shape when projected onto the horizontal XY plane, their maximum dimension corresponds to their diameter. If a hole does not have a constant cross-section along the stacking direction Z, then Li5 is considered to correspond to the maximum diameter (or other characteristic dimension) of that hole along the Z direction. Preferably, Li5 is less than 200 nm, preferably less than 100 nm, and even more advantageously, less than 50 nm. Li5 can notably be approximately equal to 40 nm.

[0072] According to an advantageous embodiment, at least one first contact hole 15* is also formed in the first support layer 10 from its upper face 11. The first contact hole 15* and the first holes 15a, 15b are preferably formed simultaneously, during the same etching step. Advantageously, the first contact hole 15* leads to a metallic interconnection 35* of the lower metallic line 30.

[0073] The first support layer 10 is thus obtained comprising a plurality of first holes 15a, 15b, and preferably at least one first contact hole 15*, which, according to an advantageous embodiment of the process according to the invention, is provided during the first step of the process.

[0074] As illustrated by the transition from [Fig.2B] to [Fig.2E], a second step of the process consists of filling each first hole 15a, 15b with a first metallic via 110a, 110b and a first electrode 120a, 120b.

[0075] The characteristics described below for a first metallic via 110a, 110b and a first electrode 120a, 120b apply to all first metallic vias 110a, 110b and first electrodes 120a, 120b.

[0076] The first metallic via 110a, 110b is preferably in contact with a metallic interconnection 35a, 35b of the lower metallic line 30. The first electrode 120a, 120b and the first metallic via 110a, 110b are in contact.

[0077] The first electrode 120a, 120b can be multilayered.

[0078] The first electrode 120a, 120b is preferably made of a material inert to the active layer 150, i.e., not participating in the mechanism of filament formation and rupture in the active layer. In a particular case, it may promote the creation of a conductive filament within the active layer 150, which will be described later. It may be made of the same material as the first metallic via 110a, 110b, or of a different material.

[0079] According to a first example illustrated by the sequence of steps shown in Figures 2B, 2C, 2D and 2E, the first holes 15a, 15b are first completely filled by the first metallic via 110a, 110b ([Fig. 2C]), then a portion of this first metallic via 110a, 110b is removed, typically by etching, from its upper face 111a, 111b ([Fig. 2D]). The space thus left empty by this removal in the first hole 15a, 15b is then at least partially, preferably completely, filled by the first electrode 120a, 120b ([Fig. 2E]).

[0080] According to a second example illustrated by the sequence of steps shown in Figures 2B, 2D and 2E, the first holes 15a, 15b are initially partially filled by the first metallic via 110a, 110b ([Fig.2D]), then the first electrode 120a, 120b is deposited on the first metallic via 110a, 110b ([Fig.2E]).

[0081] In both cases, the assembly consisting of the first metallic via 110a, 110b and the first electrode 120a, 120b located in the same first hole 15a, 15b constitutes a first conducting assembly 100a, 100b. Just like the first holes 15a, 15b, the first conducting assemblies 100a, 100b have a continuous profile.

[0082] As illustrated in Figures 2C to 2E, a first metallic contact via 110* and a first contact electrode 120* are formed in the first contact hole 15*, preferably during the same deposition and etching steps as the first metallic vias 110a, 110b and the first electrodes 120a, 120b, respectively. It is understood, however, that the first contact hole 15* may accommodate only a first metallic contact via 110* or only a first contact electrode 120*. The first metallic contact via 110*, the first contact electrode 120*, or both, as the case may be, constitutes a first conductive contact assembly 100*. The first conductive contact assembly 100* is preferably in contact with a metallic interconnection 35* of the lower metallic line 30.

[0083] The deposition of the first electrodes 120a, 120b, the first metallic vias 110a, 110b, the first metallic contact via 110* and the first contact electrode 120* can for example be done by physical vapor deposition (PVD, “Physical Vapor Deposition”) or by chemical vapor deposition (CVD, “Chemical Vapor Deposition”).

[0084] It is understood that after the formation of the first metallic vias 110a, 110b, the first contact metallic vias 110*, the first electrodes 120a, 120b, and the first contact electrodes 120* in the first holes 15a, 15b, and in the first contact holes 15*, the first support layer 10 always defines these holes 15a, 15b, 15*, even if they are filled. Thus, in the remainder of this description, a hole formed in the support layer 10 can therefore refer to an empty hole or a filled hole.

[0085] As illustrated in [Fig. 2F], in a third step of the process, an active layer 150 is formed on the upper face 11 of the first support layer 10 and on, and preferably in contact with, each of the first electrodes 120a, 120b. The active layer 150 thus extends over a plurality of first conducting assemblies 100a, 100b. The active layer 150 is continuous, thus there is continuity of material between the portions of the active layer 150 overlying the different first conducting assemblies 100a, 100b.

[0086] The active layer 150 can be multilayered. It is preferably single-layered.

[0087] Furthermore, at this stage of the process, the active layer 150 preferably also covers the first conductive contact assembly 100*. Indeed, depositing the layer active 150 on the entire surface of the stack (so-called "full plate" deposition) simplifies the process.

[0088] The active layer 150 is based on a material that can selectively switch from a first state having a first resistivity to a second state having a second resistivity, different from the first. Preferably, the first resistivity is greater than 2 times, preferably 10 times, and preferably 100 times, the second resistivity.

[0089] At this stage, it is possible to perform a treatment step on the active layer 150. This can be a surface treatment or a treatment throughout the entire thickness of the active layer 150. The treatment could, for example, be ion implantation aimed at modifying the properties of the layer to promote the formation or rupture of the conductive filament. A heat treatment can also be carried out at this stage to relax the stresses in the active layer 150 and thus limit structural defects that may be present after deposition, or to modify the structure of the active layer 150 to promote the formation or rupture of the conductive filament. In particular, this heat treatment can allow the active layer 150 to transition from an amorphous state to a crystalline state, which may be preferentially desired in the case of FeRAM-type memory. This treatment can be performed in a wafer-scale oven.

[0090] Advantageously, a protective layer 160 is formed on the active layer 150. This protective layer 160 can, for example, be based on SiN, SiCN, carbon, or any other material offering good selectivity to etching both with respect to the second support layer 20 described above and to the active layer 150 so that it will be possible to etch the second holes 25a and 25b by stopping on this layer 160 and without damaging the active layer 150, and then to remove the portions of the layer 160 exposed in the bottoms of the second holes 25a and 25b by a process allowing little or no degradation of the first electrodes 120a, 120b.

[0091] Figure 2G illustrates the deposition of a second support layer 20 on the active layer 150. This second support layer 20 indirectly covers at least the plurality of holes 15a, 15b, now filled by the plurality of first conductive assemblies 100a, 100b. It also advantageously covers the first contact conductive assembly 100*. If a protective layer 160 has previously been deposited on the active layer 150, the second support layer 20 also covers it, preferably in contact with it.

[0092] After the formation of the second support layer 20, a treatment step can be carried out. This may, in particular, be a heat treatment as described above. When this heat treatment is carried out at this stage of the process, the second support layer 20 helps to protect the active layer 150 during the treatment.

[0093] As illustrated in [Fig.2H], a plurality of second holes 25a, 25b is then formed in the second support layer 20, from its upper face 21. The second holes 25a, 25b each pass through the second support layer 20 over its entire thickness e20 in the Z direction. Each second hole 25a, 25b thus opens onto the active layer 150 and is located opposite a distinct first hole 15a, 15b.

[0094] If a protective layer 160 is present between the active layer 150 and the second support layer 20, the second holes 25a, 25b also pass through the protective layer 160 through its entire thickness in the Z direction. The formation of the second holes 25a, 25b can then take place in two steps: a first etching in the second support layer 20 and a second etching in the protective layer 160. The protective layer 160 then protects the active layer 150 during the etching of the second holes 25a, 25b in the second support layer 20. It is itself advantageously removed locally by means of a process that causes very little or no damage to the active layer 150, for example, chemical etching or RIE (Reactive Ion Etching) selectively to the active layer.The presence of the protective layer 160 and the formation of the second holes 25a, 25b in two successive and distinct removal steps thus limit the degradation of the active layer 150. This optimizes the performance of the memory points obtained at the end of the process.

[0095] As with the first holes 15a, 15b, the profile of the second holes 25a, 25b is continuous and may or may not be constant along the stacking direction Z.

[0096] The second holes 25a, 25b each have a maximum dimension L25 in the horizontal XY plane. In the typical case of holes having a circular shape when projected onto the horizontal XY plane, their maximum dimension corresponds to their diameter. If a hole does not have a constant cross-section along the stacking direction Z, then Li5 is considered to correspond to the maximum diameter (or other characteristic dimension) of that hole along the Z direction. Preferably, L25 is less than 200 nm, preferably less than 100 nm, and even more advantageously less than 50 nm. L25 may, in particular, be substantially equal to 40 nm. It should be noted that the second holes 25a, 25b may have a maximum dimension L25 different from the maximum dimension Li5 of the first holes.

[0097] At this stage, it is possible to carry out a treatment step of the active layer 150 through the second holes 25a, 25b. More precisely, the treatment is effective at the level of the portions of the active layer 150 visible through the second holes 25a, 25b. This can involve a surface treatment or a treatment throughout the entire thickness of the active layer 150. The treatment could, for example, be ion implantation aimed at modifying the layer's properties to promote the formation or rupture of the conductive filament. A heat treatment can also be performed at this stage to relax stresses in the active layer 150 and thus limit structural defects that may be present after deposition or after etching of holes 25a, 25b, or even modify the structure of the active layer 150 to promote the formation or rupture of the conductive filament. In particular, this heat treatment can transform the active layer 150 from an amorphous to a crystalline state, which is often preferred in the case of FeRAM memory.This treatment can be carried out in a wafer-scale oven or by using a laser locally at the second holes 25a, 25b.

[0098] At this stage, it is also possible to deposit a second active layer 170 over the entire exposed surface of the stack, namely on the upper face 21 and the inner sides 23a, 23b of the support layer 20 and on the portions of the active layer 150 visible through the second holes 25a, 25b. This second active layer 170 can advantageously improve the performance of the memory point in conjunction with the first active layer 150. This layer 170 is deposited continuously over the entire wafer without the need for etching (except for a portion that will be etched during the formation of the second contact hole 25* described below).

[0099] According to an advantageous embodiment, at least one second contact hole 25* is also formed in the second support layer 20 from its upper face 11, and, if they have been previously deposited, in the protective layer 160 and in the second active layer 170. Similarly, if the active layer 150 has been previously deposited up to the first conductive assembly 100*, the second contact hole 25* also passes through the active layer 150.

[0100] The second contact hole 25* is formed independently of the second holes 25a, 25b in order to etch the active layer 150 and optionally the protective layer 160 only in this second contact hole 25* the areas of the active layer 150 or the protective layer 160 apparent through the second holes 25a, 25b being then protected.

[0101] According to another advantageous embodiment, the second contact hole 25* can be formed before the second holes 25a, 25b. This avoids the risk of damaging the active layer 150 during the formation of the second contact hole 25*.

[0102] According to another advantageous embodiment, the second contact hole 25* can be partially formed during the formation of the second holes 25a, 25b. In this case, the second holes 25a, 25b and the second contact hole 25* are engraved simultaneously. in the support layer 20 (and in the protection layer 160 if present) up to the active layer 150, then a new protection is put in place above the second holes 25a, 25b to etch the active layer 150 only in the second contact hole 25*.

[0103] The second contact hole 25* and the first contact hole 15* are opposite each other and allow the passage of current between the lower and upper levels of the circuit.

[0104] This gives us the second support layer 20 comprising a plurality of second holes 25a, 25b, and preferably at least one second contact hole 25*, which is formed during the fourth step of the process according to the invention.

[0105] As illustrated by Figures 21 and 2J, a fifth step of the process consists of filling each second hole 25a, 25b with a second metallic via 210a, 210b and a second electrode 220a, 220b.

[0106] The characteristics described below for a second metallic via 210a, 210b and a second electrode 220a, 220b apply to all second metallic vias 210a, 210b and second electrodes 220a, 220b.

[0107] The second electrode 220a, 220b can be deposited directly onto the active layer 150, and optionally also against the inner flank 23a, 23b of the second support layer 20, defining the hole 20a, 20b in which it is deposited. If a second active layer 170 has been deposited on the active layer 150 and on the inner flank 23a, 23b of the second support layer 20, the second electrode 220a, 220b will be deposited on the second active layer 170. In all cases, the second electrode 220a, 220b then defines a cavity in which the second metallic via 210a, 210b can be deposited.

[0108] Whatever shape is chosen for the second electrode 220a, 220b, the second electrode 220a, 220b and the second metallic via 210a, 210b are in contact.

[0109] The second electrode 220a, 220b can be multilayer. It is preferably monolayer.

[0110] The second electrode 220a, 220b is preferably based on a material that promotes the creation of a conductive filament within the active layer 150. It can be based on the same material as the second metallic via 210a, 210b, or on a distinct material.

[0111] The assembly consisting of the second metallic via 210a, 210b and the second electrode 220a, 220b located in the same second hole 25a, 25b constitutes a second conducting assembly 200a, 200b. Just like the second holes 25a, 25b, the second conducting assemblies 200a, 200b have a continuous profile.

[0112] As illustrated in [Fig. 2J], a second metallic via contact 210* and optionally a second contact electrode 220* (not shown) may be formed in the second contact hole 25*, preferably during the same deposition and etching steps as the second metal vias 210a, 210b and the second electrodes 220a, 220b, respectively. The second metal contact via 210*, optionally with the second contact electrode 120*, constitutes a second contact conductor assembly 200*.

[0113] The deposition of the second electrodes 220a, 220b, the second metallic vias 210a, 210b, the second metallic contact via 210* and the second contact electrode 220* can, for example, be carried out by physical vapor deposition (PVD, “Physical Vapor Deposition”) or by chemical vapor deposition (CVD, “Chemical Vapor Deposition”).

[0114] As illustrated in [Fig. 2K], a layer or line 40 can be formed on the second support layer 20 and on the second conductor assemblies 200a, 200b. This is typically a line comprising metallic connecting elements 45a, 45b, of the "end of line" or "BEOL" type. This line 40 can be described as the upper metallic line or the upper interconnection line.

[0115] Each second metallic via 210a, 210b is preferably in contact with a metallic interconnection 45a, 45b of the upper metallic line 40. Furthermore, the second conductor contact assembly 200* is preferably in contact with a metallic interconnection 45* of the upper metallic line 40.

[0116] Each assembly consisting of a first electrode 120a, 120b and a second electrode 220a, 220b facing each other, as well as the portion of active layer 150 separating them, forms a memory point 1000a, 1000b.

[0117] Furthermore, each assembly consisting of a first conductor contact assembly 100* and a second conductor contact assembly 200* facing each other forms a contact point 1000* or via contact 1000*. This via contact 1000* is entirely electrically conductive. It thus allows the passage of current from one level of the interconnection network to the level directly above or below.

[0118] According to an embodiment illustrated in [Fig. 3], it is possible that several memory points 1000a, 1000b have a common conductive assembly, whether it is the first conductive assembly 100a or the second conductive assembly 100b. In other words, the same first metallic via 110a and the same first metallic electrode 120a, or the same second metallic via 210a and the same second metallic electrode 220a can be part of several memory points 1000a, 1000b.

[0119] In the example illustrated in [Fig. 3], two memory points 1000a, 1000b have the same first conductor assembly 100a. This extends below two separate conductor assemblies 200a, 200b. To obtain such an arrangement, only the dimensions and positioning of the first holes 15a, 15b need to be modified. compared to an embodiment in which all memory points consist of first conducting sets 100a, 100b and second conducting sets 200a, 200b distinct.

[0120] The structure illustrated in [Fig.3] corresponds to a so-called 1T2R structure. It is understood that it is possible to form any structure of the type ITnR, n being an integer greater than 2, n corresponding to the number of second conducting sets located opposite the same first conducting set.

[0121] Case 1T1R corresponds to the embodiment illustrated in [Fig.2M].

[0122] In the case of an ITnR structure, every second via 200a, 200b is preferably connected to an independent upper line (typically designated "bit line") allowing a particular bias to be applied to each memory point 1000a, 1000b during the reading or writing of one of the n memory points thus formed.

[0123] It is understood that the terms "lower" and "upper" are not to be construed in a restrictive sense, particularly with regard to the order of implementation of the process. It is entirely conceivable that the first support layer 10 may initially be deposited on an interconnection line which will act as the upper metallic line, and that the second support layer 20 may be covered by an interconnection line which will act as the lower metallic line within a BEOL-type interconnection network.

[0124] It appears, in light of the various embodiments described, that by forming vias and electrodes within the first and second holes, the invention makes it possible to increase the density of memory points within a device. In particular, it is possible, thanks to the invention, to obtain higher densities of memory points than by forming them using mesa-type structures.

[0125] In addition to the higher memory point densities obtained with the invention, another drawback of mesa-structured memory points is overcome. Indeed, when creating mesa-type structures, to achieve an acceptable memory point density, structures with a height greater than their diameter (referred to as a high aspect ratio, typically greater than 1:1) and also greater than the spacing between structures are used. This raises the problem of encapsulating these memory point matrices with an insulating layer without leaving gaps. These gaps can create integration problems, for example during planarization, or even affect the reliability of the device. By integrating the vias and electrodes into the gaps formed within the continuous layers 10, 20, the encapsulation and planarization steps of the memory points are eliminated, and there is no longer a risk of unwanted gaps forming between the memory points..

[0126] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

1. Demands Memory device (1) comprising a plurality of memory points (1000a, 1000b), the device (1) comprising a plurality of first electrodes (120a, 120b) and a plurality of second electrodes (220a, 220b), each second electrode (220a, 220b) being at least partially adjacent to a first electrode (120a, 120b), characterized in that it further comprises an active layer (150) extending continuously between the plurality of first electrodes (120a, 120b) and the plurality of second electrodes (220a, 220b), and in that: • each first electrode (120a, 120b), • a second electrode (220a, 220b) located at least partially opposite said first electrode (120a, 120b), and • a portion of active layer (150) extending between said first electrode (120a, 120b) and said second electrode (220a, 220b) together form a memory point (1000a, 1000b), and in that it further comprises a stacking comprising, stacked along a so-called stacking direction (Z), in this order: • a first support layer (10) having a top face (11), the first support layer (10) comprising a plurality of first holes (15a, 15b) each extending from its top face (11), each first hole (15a, 15b) housing: i. A first metallic via (110a, 110b), ii. A first electrode (120a, 120b) of the plurality of first electrodes (120a, 120b), each first electrode (120a, 120b) surmounting a distinct first metallic via (110a, 110b), • the active layer (150), overlying the upper face (11) of the first support layer (10), • on the active layer (150), a second support layer (20) comprising a plurality of second holes (25a, 25b) passing through it and each opening onto the active layer (150), each second hole (25a, 25b) housing: i. a second metallic via (210a, 210b), ii. a second electrode (220a, 220b) of the plurality of second electrodes (120a, 120b), said second electrode (220a, 220b) being disposed between the second metallic via (210a, 210b) and the active layer (150), and being at least partly opposite a first electrode (120a, 120b) among the plurality of first electrodes (120a, 120b).

2. Memory device (1) according to the preceding claim wherein the first holes (15a, 15b) each have a continuous profile along the stacking direction (Z) in projection into any plane comprising the stacking direction (Z).

3. Memory device (1) according to any one of the preceding claims wherein each second electrode (220a, 220b) is in direct contact with the active layer (150).

4. Memory device (1) according to any one of the preceding claims wherein at least one first electrode (120a, 120b) among the plurality of first electrodes (120a, 120b) is at least partly opposite at least two second electrodes (220a, 220b).

5. Memory device (1) according to any one of claims 1 to 3, wherein each of the first electrodes (120a, 120b) is located opposite a single second electrode (220a, 220b).

6. Memory device (1) according to any one of the preceding claims wherein the first metallic via (110a, 110b) and the first electrode (120a, 120b) contained in the same first hole (15a, 15b) are based on distinct materials.

7. Memory device (1) according to any one of the preceding claims further comprising a protective layer (160) between the active layer (150) and the second support layer (20).

8. Memory device (1) according to any one of the preceding claims wherein each first electrode (120a, 120b) is flush with the upper face (11) of the first support layer (10).

9. Memory device (1) according to any one of the preceding claims further comprising a plurality of first secondary electrodes and a plurality of second secondary electrodes, each second secondary electrode being at least partially opposite a first secondary electrode, the device further comprising a secondary active layer extending continuously between the plurality of first secondary electrodes and the plurality of second secondary electrodes, and wherein: • each first secondary electrode, • a second secondary electrode being at least partially opposite said first secondary electrode, and • a portion of secondary active layer extending between said first secondary electrode and said second secondary electrode together form a secondary memory point.

10. A method for manufacturing a memory device (1) comprising a plurality of memory points (1000a, 1000b), the method comprising the following steps: • Forming a plurality of first electrodes (120a, 120b), • Forming an active layer (150) on each of the first electrodes (120a, 120b), the active layer (150) being continuous, • Forming a plurality of second electrodes (220a, 220b) on the active layer (150), each second electrode (220a, 220b) being at least partially adjacent to a first electrode (120a, 120b), each first electrode (120a, 120b), a second electrode (220a, 220b) being at least partially adjacent to said first electrode (120a, 120b), and a portion of the active layer (150) extending between said first electrode (120a, 120b) and said second electrode (220a, 220b) together forming a memory point (1000a, 1000b), the step of forming the plurality of first electrodes (120a,120b) comprising the following steps:,

11. • Provide a first support layer (10), having an upper face (11) and a lower face (12) opposite each other, the first support layer (10) comprising a plurality of first holes (15a, 15b) each extending from its upper face (11) and opening onto its lower face (12), • Form a first electrode (120a, 120b) in each first hole (15a, 15b) of the plurality of first holes (15a, 15b), the active layer (150) being formed on the upper face (11) of the first support layer (10), the process further comprising a step of forming in each first hole (15a, 15b) a first metallic via (110a, 110b), the first electrode (120a, 120b) being in contact with the first metallic via (110a, 110b), the process further includes the following steps: • To form a second support layer (20) on the active layer (150), the second support layer (20) comprising a plurality of second holes (25a, 25b) traversing the second support layer (20) and each opening onto the active layer (150), each second hole (25a, 25b) being at least partly opposite a different first electrode (220a, 220b), • Form in each second hole (25a, 25b) of the plurality of second holes (25a, 25b) a second electrode (220a, 220b) of the plurality of second electrodes (220a, 200b) and a second metallic via (210a, 210b), the second electrode (220a, 220b) being in contact with the second metallic via (210a, 210b). A method according to the preceding claim, wherein the formation of the second support layer (20) comprises a step of depositing the support layer (20) and a step of forming the plurality of first holes (15a, 15b) within the support layer (20), the method further comprising, prior to the formation in each second hole (25a, 25b) of the second metallic via (210a, 210b) and the second electrode (220a, 220b), a step of processing the active layer (150), the active layer (150) processing step preferably taking place at one of the following times: • Before the formation of the second support layer (20), • After the deposition of the second support layer (20) and before the formation of the plurality of first holes (15a, 15b), • After the formation of the plurality of first holes (15a, 15b).

Images