METHOD FOR MANUFACTURING A DEVICE COMPRISING A PLURALITY OF PIXELS

Abstract

One aspect of the invention relates to a method for manufacturing a device comprising a plurality of pixels, the method comprising a step of forming a first group of pixels (40) on the substrate (11) comprising the following substeps: Deposition, on lower electrodes (41) of the pixels deposited on the substrate, of a first stack (421) of organic layers and a first conductive layer (16) on the first stack (421) of organic layers; Etching at least a portion of the first conductive layer to form cavities (30) having a depth strictly less than the thickness of the first conductive layer, the cavities being located at the level of spaces extending between lower electrodes of the pixels of the first group,Anisotropic etching of the first conductive layer and the first stack of organic layers so as to extend the cavities through the first conductive layer and the first stack of organic layers, residual portions (431) of the first conductive layer remaining between the cavities. Figure to be published with the abstract: Figure 7,

Description

Title of the invention: METHOD FOR MANUFACTURING A DEVICE COMPRISING A PLURALITY OF PIXELS TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of optoelectronic devices and components and more particularly that of organic semiconductor devices.

[0002] The present invention relates to a method for manufacturing a device comprising a plurality of OLED (for "Organic Light-Emitting Diodes" in English) or OPD (for "Organic Photo-Diodes" in English) pixels.

[0003] The present invention has an advantageous application for the production of display screens for electronic devices, and in particular for the production of high-resolution color display screens. The term "high resolution" refers to pixels with a size of less than 15 µm. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0004] Generally speaking, an important parameter for matrix display devices is to have emissive surfaces (i.e. pixels) that are as bright and small as possible.

[0005] In the field of OLED display devices with improved resolution, matrix OLED displays are known which have pixels of a size less than 15 pm, typically between 5 pm and 12 pm.

[0006] When this type of matrix display is in color, each pixel is subdivided into sub-pixels of different colors (typically three, with red, green, and blue as their colors) which cooperate so that the pixel emits the desired color. Each sub-pixel is an elementary light source and has a size less than 10 µm, for example, 3 µm or 6 µm.

[0007] Each sub-pixel is generally formed of several superimposed elements, including a lower electrode (the anode) deposited on a common substrate, several organic layers (at least one of which is emissive) forming an OLED stack on each lower electrode, and an upper electrode (the cathode).

[0008] To improve the luminous flux of OLED pixels, OLED display devices with multi-stacked OLED pixels are known, also called "multistack" pixels according to commonly used Anglo-Saxon terminology. In such devices, the OLED stack comprises several OLED diodes superimposed and separated from each other by a conductive interconnecting layer (also called CGL for "Charge Generation Layer"). generally also of organic nature. The use of several superimposed OLED diodes, instead of just one, increases the pixel luminance since the luminous fluxes of the OLED diodes add up.

[0009] Due to the complexity of structuring the organic layers with the desired resolution (typically a resolution corresponding to pixels with lateral dimensions less than 15 pm), it is generally preferable to separate only the lower electrodes from each other to form a multistack OLED pixel array. The other elements (OLED stack, interconnecting conductive layer, top electrode) are thus left as layers common to all pixels.

[0010] This arrangement, however, leads to the appearance of crosstalk phenomena between neighboring pixels, which degrade the performance of the display device (essentially, they lead to a denaturation of colors and a blurring of the image displayed by the OLED display device).

[0011] These crosstalk effects are due to capacitive effects between neighboring pixels, or to parasitic currents flowing between neighboring pixels through the common conductive layers of the OLED stacks and the interconnect layer. They are exacerbated in the case of multistack structures due to the presence of the conductive interconnect layer(s), which facilitates the flow of currents. They are also exacerbated when the pixel size decreases.

[0012] To reduce crosstalk phenomena, one approach is to discretize all the material layers (including organic layers) forming the pixels.

[0013] Documents FR3079909A1 and US2023 / 0041252Al thus describe separation structures between pixels which allow for the smooth discretization of organic layers.

[0014] The expression "gently" here means without implementing masking and removal steps which generally require environments (humidity, temperature above 90°C, solvents, ultraviolet, etc.) that are detrimental to organic materials.

[0015] Document FR3079909 A1 describes a first OLED display device in which the lower electrodes of each subpixel are separated from each other by an insulating wall rising vertically from the substrate. Each wall acts as a separator between two neighboring subpixels.

[0016] This same document FR3079909 describes a second device in which the insulating walls are replaced by trenches in which an insulating layer is deposited.

[0017] The insulating walls and trenches are formed before the organic layers are deposited by thermal evaporation and play the same role. Like the The evaporation deposition technique is predominantly directional; the organic layers are preferentially deposited on the horizontal surfaces of the device, and not on the lateral surfaces of the insulating walls or trenches. Each organic layer is thus broken (or discretized) at the level of the insulating walls or trenches.

[0018] However, in practice, the directivity of the OLED stack deposition is never absolute. Organic particles can therefore also be deposited on the side walls of insulating walls or trenches. These particles are undesirable because they degrade the (electrical, optical) insulation between sub-pixels and contribute to creating the crosstalk phenomena described above.

[0019] Document US2023 / 0041252A1 offers a solution to this problem by describing subpixel separators that are arranged on a substrate and have a mushroom-shaped structure (or "hang-over" structure, according to the English terminology used in this document). More specifically, this mushroom-shaped structure comprises a lower portion with slanted sides, forming the stem of the mushroom. It also comprises an upper portion, wider than the lower portion, which masks a region of the substrate. This upper portion forms the cap of the mushroom.

[0020] The sub-pixels are formed once the mushroom-shaped structures are in place. The OLED stack is then deposited onto these structures and broken at the upper parts. The OLED stack is broken with satisfactory reliability since no organic particles can be deposited on the region of the substrate masked by the upper part or on the lateral walls of the mushroom-shaped structure (the lower part is not accessible from above because it is hidden by the upper part). Thus, the degree of directivity of the OLED stack deposition is of little importance.

[0021] These mushroom-shaped structures are, however, particularly complex to manufacture and not very compact (vertically, they have a height of approximately 1 µm or more). Furthermore, manufacturing the common cathode requires the use of deposition equipment specifically designed for the device. This involves depositing a metallic layer under the upper part of the mushroom-shaped structures at a very specific angle determined by the inclination of the lower sections. Therefore, deploying such a manufacturing process is neither easy nor economically advantageous.

[0022] There is therefore still a need for a manufacturing process for OLED display devices with high resolution and improved efficiency that is less expensive and simpler to implement. Summary of the invention

[0023] The invention offers a solution to the problems mentioned above, by allowing the discretization of all the material layers forming each pixel without using separation structures.

[0024] The term "pixel" refers to a sub-pixel, that is to say the smallest element composing a pixel of the organic semiconductor device.

[0025] A first aspect of the invention thus relates to a method for manufacturing a device comprising a plurality of pixels arranged on a substrate, each pixel comprising a lower electrode, an upper electrode, and an active element disposed between the lower and upper electrodes, said method comprising the following steps: • Provision of a structure comprising the substrate and the lower electrodes of the pixels, the lower electrodes being spaced apart and arranged on a first surface of the substrate, called the active surface, • Formation of a first group of pixels on the substrate, by completing the following sub-steps: • Deposition, on the active surface of the substrate, of an initial stack of organic layers configured to generate or absorb initial radiation, • Deposition of a first conductive layer on the first stack of organic layers, • Etching at least part of the first conductive layer to form cavities having a depth strictly less than the thickness of the first conductive layer, the cavities being located at the level of spaces extending between the lower electrodes of the pixels of the first group, • Anisotropic etching of the first conductive layer and anisotropic etching of the first stack of organic layers so as to extend the cavities through the first conductive layer and the first stack of organic layers, residual portions of the first conductive layer remaining between the cavities, from which the pixels of the first group are separated from each other by the cavities.

[0026] Radiation is understood here as light radiation which includes at least one wavelength in the visible and infrared spectrum, that is to say in the range of wavelengths extending between 400 nm and 2500 nm.

[0027] Thus, the use, as an etching mask for the stack of organic layers, of a conductive layer (here called the first conductive layer) intended to be partially retained in the device (the residual portions of this The layer (which is part of the pixels), meaning that some of it remains after the manufacturing process, eliminates the need for a mask removal (or "stripping") step. A mask removal step like those used in the manufacturing of inorganic semiconductor devices is incompatible with OLED (Organic Light-Emitting Diode) or OPD (Organic Photodiode) technology.

[0028] Indeed, this mask removal step requires the application of particularly aggressive, and therefore destructive, environments to the substrate, which are detrimental to the organic layers. These environments may involve solvents (in the case of a resin mask), exposure to a plasma (in the case of a hard mask), and / or the use of high temperatures, exceeding 100°C.

[0029] The manufacturing process according to the invention therefore does not involve any step of removing an etching mask that would be in contact with the organic materials constituting the active element of each pixel (because this step is no longer necessary). Thus, the organic materials are preserved. Furthermore, the process is simpler to implement than prior art processes, which are based on separation structures between pixels, and is suitable for forming pixels up to 1 pm in size (i.e., to achieve the desired high resolution).

[0030] Furthermore, thanks to the anisotropic etching of the first conductive layer and the first stack of organic layers, pixels that are physically separated from each other along their entire height are obtained. This prevents electrical crosstalk since currents can no longer flow between the pixels. It also reduces optical crosstalk between pixels. Indeed, the cavities separating the pixels create a refractive index break between the pixels and their external environment, which leads to the confinement of light flux within the pixel area.

[0031] Thus, thanks to the invention, a high-resolution and better-performing organic semiconductor device is manufactured in a simple way.

[0032] In addition to the characteristics mentioned in the preceding paragraph, the manufacturing process according to the first aspect of the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • The anisotropic etching substep is carried out under an oxygen-free atmosphere. • The supplied structure includes an electrically insulating layer disposed on the active surface of the substrate and laterally enclosing the lower electrode of each pixel, the electrically insulating layer serving as a stop layer during the anisotropic etching of the first stack of organic layers. The step of forming the first group of pixels on the substrate also includes: • between the deposition of the first stack of organic layers and the deposition of the first conductive layer, the deposition of a second conductive layer made of a metal, • between the anisotropic etching of the first conductive layer and the anisotropic etching of the first stack of organic layers, an anisotropic etching of the second conductive layer. The first stacking of organic layers is configured to generate the first radiation, and the step of forming the first group of pixels on the substrate further includes: • Between the deposition of the first stack of organic layers and the deposition of the second conductive layer, the following operations occur: • Deposition of a conductive interconnecting layer on the first stack of organic layers, the conductive interconnecting layer being adapted to connect the first stack of organic layers to a second stack of organic layers, • Deposition of the second stack of organic layers onto the conductive interconnecting layer, • Between the anisotropic etching of the second conductive layer and the anisotropic etching of the first stack of organic layers, an anisotropic etching of the interconnecting conductive layer and an anisotropic etching of the second stack of organic layers, from which results the pixels separated from each other and having a tandem structure. The conductive interconnect layer is formed from a metallic or organic conductive material. The first conductive layer is made of a metal and has an initial thickness determined so that the thickness of the residual portions of the first conductive layer is less than 20 nm, preferably between 10 nm and 20 nm. The first conductive layer is formed of a conductive and transparent material such as a transparent conductive oxide (TCO). The manufacturing process may include, after the step of forming the pixels on the substrate, a step of depositing a passivation layer on the peripheries of the pixels and on the surface of the substrate. The passivation layer is deposited in a conforming manner. The manufacturing process may include, after the passivation layer deposition step, a common electrode formation step comprising the following sub-steps: • Opening the passivation layer to create access to the top electrode of each pixel, • Formation of a third continuous conductive layer on the pixels and on the substrate between the pixels and on an electrical contact track disposed on a second surface of the peripheral substrate to the active surface, from which results the common electrode connecting the upper electrode of each pixel to the electrical contact track. The third conductive layer can be transparent. Alternatively, the third conductive layer is reflective and the substrate is transparent. When the conductive layer is reflective, the third conductive layer has a thickness greater than 50 nm. The manufacturing process may include, after the passivation layer deposition step, a step of forming a second group of pixels on another part of the lower electrodes, comprising the following sub-steps: • Opening the passivation layer to create access to each lower electrode of the pixels in the second group, • Deposition, on the active surface of the substrate, of a third stack of organic layers configured to generate radiation distinct from the first radiation, • Deposition of a fourth conductive layer on the third stack of organic layers, • Etching at least part of the fourth conductive layer to form cavities having a depth less than or equal to the thickness of the fourth conductive layer, the cavities being located at the gaps extending between the lower electrodes of the pixels of the second group, • Anisotropic etching of the fourth conductive layer and anisotropic etching of the third stack of organic layers so as to extend the cavities through the fourth conductive layer and the third stack of organic layers, with residual portions of the fourth conductive layer remaining between the cavities, from which it results, in addition to the pixels of the first group, the pixels of the second group separated from each other by the cavities.

[0033] A second aspect of the invention relates to a method for manufacturing a device comprising a plurality of pixels arranged on a substrate, each pixel comprising a lower electrode, an upper electrode, and an active element disposed between the lower and upper electrodes, said method comprising the following steps: • Provision of a structure comprising the substrate and the lower electrodes of the pixels, the lower electrodes being spaced apart and arranged on a first surface of the substrate, called the active surface, • Formation of a first group of pixels on the substrate, by completing the following sub-steps: • Deposition, on the active surface of the substrate, of an initial stack of organic layers configured to generate or absorb initial radiation, • Deposition of a second conductive layer made of a metal on the first stack of organic layers, • Deposition of a first conductive layer on the first stack of organic layers, • Etching at least part of the first conductive layer to form cavities having a depth less than or equal to the thickness of the first conductive layer, the cavities being located at the gaps extending between the lower electrodes of the pixels of the first group, • Anisotropic etching of the first conductive layer and anisotropic etching of the first stack of organic layers so as to extend the cavities through the first conductive layer, the second conductive layer and the first stack of organic layers, residual portions of the first conductive layer remaining between the cavities, from which results the pixels of the first group separated from each other by the cavities.

[0034] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0035] The figures are presented for illustrative purposes only and are in no way limiting of the invention. • Figure [1] schematically represents a cross-sectional view of an example pixel of an electroluminescent display device, • Figures 2 to 14 represent a first implementation of a manufacturing process for an electroluminescent display device according to the invention, • Figures 15 to 19 represent a second implementation of the manufacturing process for an electroluminescent display device according to the invention, • Figure [Fig. 20] represents a third embodiment of the manufacturing process for an electroluminescent display device according to the invention, • The [Fig.21] represent a fourth embodiment of the manufacturing process for an electroluminescent display device according to the invention. DETAILED DESCRIPTION

[0036] The present invention aims to improve the manufacturing processes for devices comprising an organic pixel array (i.e., pixels made partly of organic materials). The present invention relates in particular to a manufacturing process that improves the pixel separation phase. More specifically, the present invention aims to physically separate pixels from each other in a simpler manner than prior art solutions based on separation elements between pixels.

[0037] The present invention finds, for example, an advantageous application in the manufacture of devices comprising an OLED (Organic Light Emitting Diode) pixel matrix with improved resolution, also called OLED electroluminescent display devices or OLED micro-displays. The present invention makes it possible to obtain display devices that are convenient to manufacture and of higher quality, since crosstalk between OLED pixels is reduced.

[0038] Naturally, the present invention can also be applied to the manufacture of other OLED-type display devices, such as OLED screens for television applications or any other OLED pixel-based light source. The present invention can further be applied to the manufacture of devices comprising an OPD (Organic Photodiode) pixel array.

[0039] Figures 2 to 11 illustrate a first method of implementing a manufacturing process according to the invention, used preferably to produce an electroluminescent display device.

[0040] Figure 7 shows, schematically, a first embodiment of an OLED electroluminescent display device 1 (also noted as a "display device"). 1 » thereafter) obtained at the end of an E2 step of forming a first group of pixels on a substrate, according to the first method of implementation of the manufacturing process.

[0041] As shown in [Fig.7], the first embodiment of the display device 1 comprises a plurality of pixels 40 arranged on a substrate 11.

[0042] The substrate 11 has an upper surface lia (also referred to hereafter as the "surface of the substrate 11") which extends in a plane {X,Y}. This plane defines the plane of the substrate. Directions and dimensions will hereafter be designated with respect to this plane {X,Y} of the substrate. Thus, the term "lateral" designates a direction contained in the plane of the substrate 11 or in a plane parallel to the plane of the substrate 10, while the term "vertical" designates a direction along a Z-axis perpendicular to the plane {X,Y} of the substrate. The terms "height," "thickness," and "depth" refer to dimensions measured perpendicular to the plane {X,Y} of the substrate, i.e., along the Z-axis. The term "length" refers to a dimension measured in a plane parallel to the plane of the substrate 11.

[0043] The substrate 11 is advantageously a specialized circuit or ASIC (for "Application Specified Integrated Circuit") of the CMOS (for "Complementary Metal Oxide Semiconductor") type, formed from a silicon wafer. This type of circuit is indeed well suited for addressing pixels 40 with lateral dimensions less than 15 pm. Note that such a substrate 11 is opaque and that the display device 1 is then of the top-emitting type (or "TOP emission" according to commonly used terminology). In the following description, the terms "transparent" and "opaque" refer to an element which, for at least one wavelength in the 400-800 nm spectral band, has an optical transmission coefficient greater than 60% and less than or equal to 60%, respectively.

[0044] Alternatively, the substrate 11 may comprise thin-film transistors or TFTs (Thin Film Transistors) made of amorphous silicon, polycrystalline silicon, and / or deposited on a glass plate. The substrate 11 may thus be transparent. The display device 1 may then be of the bottom-emitting type.

[0045] The substrate 11 includes an addressing circuit and a plurality of contact pads 113 of the pixels (for readability, the addressing circuit is not shown in [Fig.7], nor in the other figures, and the contact pads 113 are shown only in Figures 2 and 9).

[0046] The addressing circuit is configured to address pixels 40.

[0047] The contact pads 113 are made of a conductive material. They are spaced apart and flush with the surface 1 of the substrate 11. The contact pads 113 allowing an electrical connection to be made between each pixel 40 and the addressing circuit.

[0048] For an enhanced resolution display device, the pixels 40 preferably have lateral dimensions less than 15 pm, preferably between 15 pm and 3 pm, for example, equal to 4 pm. In top view, they advantageously have a square shape. The size of the pixels will hereafter be referred to as the side of the square.

[0049] As shown in the boxed portion of [Fig.7], each pixel 40 comprises a lower electrode 41 disposed on the substrate 11, an upper electrode 43 and an active element 42 disposed between the lower electrode 41 and the upper electrode 43.

[0050] The lower electrode 41 of the pixel is preferably made of one or more metals, advantageously chosen from the following metals: silver (Ag), chromium (Cr), aluminium (Al), titanium (Ti).

[0051] The lower electrode 41 is preferably reflective for a top-emitting device. In this case, its thickness is greater than 15 nm. The reflective lower electrode 41 is preferably used when the substrate 11 is opaque.

[0052] Alternatively, the lower electrode 41 is transparent for a bottom-emitting device. In this case, its thickness is less than 15 nm. The transparent lower electrode 41 is preferably used when the substrate 11 is transparent.

[0053] The lower electrodes 41 of the pixels are preferably formed by structuring a conductive layer or several stacked conductive layers made of different conductive materials.

[0054] With reference to [Fig. 7], the lower electrode 41 has a lower face 41a connected to the surface 1a of the substrate and an opposite upper face 41b connected by a peripheral lateral surface. The lower electrode 41 also has a height e4i.

[0055] The lower electrode 41 finally presents, in a plane parallel to the {X,Y} plane of the substrate, a surface, or section, which can take different forms (square, circular, rectangular, etc.).

[0056] In [Fig.7], the cross-section of the lower electrode 41 is square in shape. The peripheral lateral surface 41d is then made up of four facets corresponding to the four lateral faces (also called peripheral edges hereafter) 41c of the lower electrode 4L. In the cross-sectional view of [Fig.7], two of these lateral walls 41c are visible.

[0057] The cross-section of the lower electrode 41 corresponds to the emission surface of the pixel 40. For high-resolution display devices, this emission surface is advantageously less than 15x15 pm2, preferably between 3x3 pm2 and 12x12 pm2, and for example equal to 4x4 pm2.

[0058] The lower electrode 41 is electrically connected to one of the contact pads of the substrate 11.

[0059] The active element 42 of the pixel is arranged on the upper face 41a of the lower electrode 4L II has a height e42.

[0060] In the example shown in [Fig.7], the active element 42 has a tandem structure, that is to say, it comprises successively, from the lower electrode 41 and in the vertical direction, the following sub-elements: a first electroluminescent sub-element formed of a first OLED stack 421, a charge generation conductive layer CGL (for "Charge Generation Layer" in English), and a second electroluminescent element formed of a second OLED stack 422.

[0061] This tandem structure is described in more detail below in relation to [Fig.1].

[0062] The first and second OLED stacks 421, 422 both include organic layers, at least one of which is emissive (noted EM42i and EM422 in [Fig.1]).

[0063] Preferably, each OLED stack 421, 422 comprises successively the following organic layers: • a layer of HIL holes injection • an HTL hole transport layer • an electron blocking layer (EBL), • an EM42i, EM422 emissive layer • a layer of HBL hole hedgerows • an electron transport layer (ETL), and • an electron injection layer (EIL).

[0064] The injection, transport and blocking layers are conductive.

[0065] The term "emitting organic layer" EM42b EM422 refers to an organic layer which has the property of generating radiation when a voltage is applied between the lower and upper electrodes of the pixel.

[0066] Radiation is understood here as light radiation which includes at least one wavelength in the visible and infrared spectrum, that is to say in the range of wavelengths extending between 400 nm and 2500 nm.

[0067] Hereafter, "white light radiation" will be defined as radiation whose spectrum extends between 400 nm and 800 nm, while colored radiation will designate a light radiation whose spectrum is centered around the wavelength corresponding to the color. Thus: • Radiation in the blue region exhibits a spectrum of wavelengths centered on blue, for example, a spectrum located mainly between 430 nm and 490 nanometers • Radiation in the green region has a spectrum centered on green, for example, a spectrum located mainly between 490 nm and 590 nm, • and radiation in the red has a spectrum centered on red, for example a spectrum located mainly between 590 nm and 700 nm.

[0068] The EM42i emissive layer of the first OLED stack 421 and the EM422 emissive layer of the second OLED stack can be configured to generate radiation of different colors, so that the active element 42 emits white light radiation.

[0069] The charge-generating CGL layer separating the two OLED stacks can be an organic conductive layer whose conductivity has been modulated by a doping technique. Alternatively, the charge-generating CGL layer separating the two OLED stacks 421, 422 can be an undoped organic semiconductor layer.

[0070] Alternatively, the CGL layer can be a metallic conductive layer. Using a metal rather than a semiconducting organic layer improves the injection of charge carriers into the OLED diodes arranged on either side of this CGL layer. This optimizes the use of the two electroluminescent sub-elements 421 and 422 (each electroluminescent sub-element 421, 422 carries a higher current density). In other words, by increasing the conductivity of the charge-transfer GGL layer, double the luminance compared to using a single electroluminescent element with the same current density. Pixel 40 is thus brighter and has an extended operational lifespan.

[0071] The upper electrode 43 of the pixel is a conductive element which covers the active element 42 (on its upper face) and terminates (at the top) the pixel 40. It has a thickness noted e43 on the [Fig.7].

[0072] The pixel 40 then has a height h40 which is equal to the sum of the thickness e4 of the lower electrode 41, the thickness e42 of the active element 42 and the thickness e43 of the upper electrode 43 (see [Fig. 7]). This height h40 of the pixel is preferably between 100 nm and 200 nm, for example equal to 150 nm.

[0073] In this first embodiment, the upper electrode 43 comprises two superimposed conducting portions 431, 432, the second portion 432 being arranged on the active element 42 and the first portion 431 being disposed on the second portion 432. The thickness e43 of the upper electrode 43 is then equal to the sum of the thickness e43i of the first portion 431 and the thickness e432 of the second portion 432.

[0074] The second portion 432 of the upper electrode 43 allows to create an optical microcavity effect in the pixel 40 (the microcavity being delimited between the lower electrode 41 and the first portion 431 of the upper electrode).

[0075] Depending on the configuration chosen for the active element 42 of the pixel 40 (including its height h42 or the optical index of the organic layers forming this active element 42), this microcavity effect makes it possible to select a radiation of a given color from the hip light radiation obtained at the output of the active element 42.

[0076] The configuration of the active element 42 can thus be chosen so that the pixel 40 produces light radiation in blue, in green or in red.

[0077] The upper electrode 43 is transparent when the substrate 11 is opaque.

[0078] The upper electrode 43 is preferentially reflective when the substrate 11 is transparent.

[0079] Now that each pixel 40 has been described, the arrangement of the pixels with respect to each other is described in more detail.

[0080] The pixels 40 occupy an area of ​​the substrate 11 called the active area SA ct (see [Fig.7]). This active area SA ct of the substrate 11 extends, for example, between 10 mm2 and 5 cm2 for OLED micro-displays.

[0081] On this active surface SA Ct, the pixels 40 are preferably arranged in rows and columns. In other words, they are arranged with a first repetition step along a first direction lying in the plane of the substrate (for example, the X direction) and with a second repetition step along a second direction (for example, Y) intersecting the first direction. Thus, the pixels 40 form a matrix of electroluminescent elements.

[0082] Advantageously, the 40 pixels all have an identical shape (within manufacturing tolerances).

[0083] As shown in [Fig.7], the pixels 40 are physically separated from each other, along their entire height h40. In other words, a trench 30 free of organic and conductive layers is arranged between two neighboring pixels 40 (or separates, or rather spaces, two neighboring pixels 40).

[0084] This trench 30 extends over a length, defined as the distance d40 between a lateral wall of a lower electrode 41 and the opposite lateral wall of the neighboring lower electrode 41, which is preferably less than or equal to 1 pm, preferably between 500 nm and 1 pm, for example equal to 800 nm.

[0085] Since no layer (organic, conductive) is common to all pixels, no current can flow between pixels 40. This prevents the occurrence of electrical crosstalk between neighboring pixels 40. This makes it possible to obtain a display device 1 that is both brighter (thanks to the tandem structure of the active elements 42) and has a better display resolution (thanks to the gaps 30 between the pixels 40).

[0086] Another advantage of physically separating the pixels 40 is to limit optical crosstalk between them. The presence, between the pixels 40, of an area free of organic and conductive layers allows for a break in the optical index at the outer boundaries of each pixel 40. This break in the optical index is conducive to confining the radiation emitted by each pixel within the area of ​​pixel 40. Reducing optical crosstalk contributes to improving the display resolution of the display device 1.

[0087] Note that, in the display device shown in [Fig. 7], all pixels 40 have a height h40 and identical lateral dimensions (within manufacturing tolerances) and their elements 41, 42, 43 are all of the same nature (i.e., made of the same materials). The display device is therefore monochrome (all pixels 40 produce the same radiation).

[0088] Fig. 19 represents a second embodiment of the display device 1.

[0089] This second embodiment differs from the first embodiment (illustrated in Fig. 7) only in that the pixels 40 do not all produce the same light radiation.

[0090] According to this second embodiment, the display device 1 comprises three groups of pixels 40ijB, 402v, and 403jR configured to produce three radiations of distinct colors, for example, red R, green V, and blue B. The pixels of the three groups are advantageously arranged alternately: a green pixel 402v positioned between a blue pixel 40iB and a red pixel 403jR. The overall radiation emitted by these three pixels 40ijB, 402jV, and 403r, which corresponds to the combination of these three radiations, can be adjusted according to the light intensities of the three pixels. The display device is then a color display device.

[0091] Fig. 20 shows a third embodiment of the display device 1.

[0092] This third embodiment differs from the first embodiment illustrated in [Fig. 19] in that the active element 42 of each pixel comprises a single electroluminescent sub-element (or first OLED stack 421). This makes it possible to obtain a display device admittedly less bright than the first and second embodiments, but simpler to make.

[0093] It is noted that the presence of the trenches 30 between the pixels 40 allows, as for the first and second embodiments, to reduce, or even eliminate, the phenomena of electrical and optical crosstalk between the pixels 40. These phenomena also exist (although to a lesser extent compared to tandem pixel devices) in simple OLED display devices.

[0094] The third embodiment is further distinguished from the first and second embodiments in that the upper electrode 43 of the pixels 40 is preferably formed of a single conductive portion 431 (instead of two conductive portions 431, 432). This single conductive portion 431 is then made of a metal (silver, aluminum, titanium, etc.). It may also have a thin thickness e431, less than 15 nm, so as to be transparent. This configuration is preferred when the substrate 11 is opaque.

[0095] The use of a single conductive portion 431 instead of two makes it possible to reduce the number of manufacturing steps and thus simplify the manufacture of the display device 1.

[0096] Note that this third embodiment allows for the creation of a monochrome display device. Indeed, the active elements 42 of the pixels 40 can all be configured identically, like the pixels 40 of the first embodiment illustrated in [Fig.7].

[0097] According to one variant, the active element of each pixel 40 of the device shown in [Fig. 20] can, alternatively, be formed of a stack of organic layers configured to absorb (and not generate) visible or infrared radiation. In this case, the pixels are OPD pixels (for "organic photodiode").

[0098] Figure [Fig. 21] shows a fourth embodiment of the display device 1.

[0099] According to this fourth embodiment, the device 1 comprises, as the Third embodiment: simple OLED structure pixels.

[0100] Thus, the active elements 42ijB 422>v 423jR of the pixels are formed only from a stacking of organic layers 421b 4212, 4213.

[0101] Like the third embodiment, the fourth embodiment of device 1 comprises three groups of pixels 40ijB, 402>v and 403jR.

[0102] Preferably, the color of the radiation produced by each pixel group is obtained directly by configuring the OLED stacking 421, 4212, 4213 of the pixels 40. In other words, the active element 42ijB of each pixel 40ijB of the first group is formed from a first stacking configured to produce radiation in the blue, while the active element 422v of each pixel 402v of the second group is formed from a second stack configured to produce radiation in the green, and that the active element 423>R of each pixel 403, R of the third group is formed from a third stack configured to produce radiation in the red.

[0103] Obtaining the color radiation directly at the level of the active elements 42 of the pixels makes it possible to do without a color filter and to obtain brighter color pixels.

[0104] The manufacturing process of the display device 1 according to the first embodiment will now be described in relation to Figures 2 to 7.

[0105] As shown in [Fig.2], the process 1 begins with a step El consisting of providing a structure 10 comprising the substrate 11 and the lower electrodes 41 of the pixels, these being spaced apart from each other (and therefore electrically isolated from each other).

[0106] The surface of the substrate 11 which is occupied by the lower electrodes 41 corresponds to an active surface SA ct of the substrate 11.

[0107] These lower electrodes 41 can be formed by well-known operations of deposition, lithography, etching and mask removal (or “stripping” in English).

[0108] The structure 10 may also include an electrically insulating layer 12 which extends over the active surface SA ct of the substrate 11 and laterally encases each lower electrode 41 (i.e. which covers the lateral peripheral surface of each lower electrode 41).

[0109] In addition to providing effective electrical insulation between the lower electrodes 41, the insulating layer 12 also serves, as will be described later, as an etching stop layer.

[0110] The insulating layer 12 can be formed from silicon dioxide (SiO2).

[0111] The structure 10 further comprises an electrical track 13 disposed on a surface of the substrate 11 (also referred to as the "peripheral surface SPER1" hereafter) located at the periphery of the active surface SA CT- This electrical track 13 is electrically connected to the contact pads 113 of the substrate 11 via conductive links 111. In [Fig.2], the contact pads 113 which are shown allow, as will be explained later, the establishment of an electrical connection between the upper electrode 43 of each pixel 40 and the electrical track 13.

[0112] The multiplicity of these contact pads allows a better distribution of current through the upper electrodes of the pixels, compared to a single point of contact resumption.

[0113] Figures 3 to 7 illustrate an E2 step of the formation of a first group of pixels 40 on the substrate 11.

[0114] The number of pixels in the first group can correspond, as illustrated in [Fig.7], to the number of lower electrodes 41 arranged on the substrate 11. Thus, all the pixels 40 of the display device 1 are formed during step E2.

[0115] Step E2 includes a substep E21 of material layer deposition and two etching substeps E22 and E23.

[0116] With reference to [Fig.3], step E2 begins with substep E21 which consists of successively depositing, on the active surface SA ct of the substrate 11, the materials forming the active element 42 (cf. Fig. 7) and the upper electrode 43 of the pixels 40.

[0117] More specifically, substep E21 comprises the following operations: • Deposition E211 of the first stack 421 of organic layers on the active surface SA ct of the substrate 11 (in this case on the insulating layer 12), • Deposition E212 of the CGL layer on the first stack of 421 organic layers, • E213 deposit of the second 422 stack of organic layers on the CGL layer, • Deposition E214 of a second conductive layer 17 on the second stack 422 of organic layers, and • Deposition E215 of a first conductive layer 16 on the second conductive layer 17.

[0118] It is specified that the deposits E211 to E215 are preferably made using a stencil which exposes the active surface SA Ct of the substrate 11 and protects the peripheral surface SPERi of the substrate 11.

[0119] Furthermore, the material deposits are preferably carried out by a directional process (in a direction perpendicular to the plane {X,Y} of the substrate 11), preferably by a physical vapor phase deposition process such as evaporation.

[0120] The first conductive layer 16 is intended to form the first conductive portions 431 of the upper electrodes 43 of the pixels 40 (see [Fig. 7]). The initial thickness ei6 (see [Fig. 4]) of this first conductive layer 16 is to be adjusted according to the desired thickness e43 (see [Fig. 7]) for the upper electrode 43 of each pixel 40. The initial thickness ei6 of the first conductive layer 16 is thus, for example, between 30 nm and 100 nm.

[0121] The first conductive layer 16 can be formed of a metal such as aluminium (Al), silver (Ag), or chromium (Cr) for a bottom-emitting display device 1

[0122] Alternatively, the first conductive layer 16 may be formed of a conductive and transparent material selected (but not limited to) from the following materials: Poly(3,4-ethylenedioxythiophene) (or PEDOT), indium tin oxide (or ITO for "Indium Tin Oxide" in English), tin dioxide (SnO2), zinc oxide (ZnO) or aluminum-doped zinc oxide (or AZO).

[0123] The second conductive layer 17 is intended to form the second conductive portions 432 of the upper electrodes 43 of the pixels 40.

[0124] The second conductive layer 17 is preferably formed of a metal, for example silver (Ag).

[0125] To obtain transparent second conductive portions 432, the second conductive layer 17 has a thickness of less than 20 nm, for example between 10 nm and 20 nm.

[0126] At the end of substep E21, all the materials intended to form the pixels 40 were deposited on the active surface SAct of the substrate 11. The resulting layers 421, CGL, 422, 17, and 16 form a stack marked Ep on [Fig.3].

[0127] Figures 4 to 6 illustrate operations carried out during substep E22.

[0128] With reference to [Fig. 5] or with reference to [Fig. 6], this substep E22 consists of to etch at least part of the first conductive layer 16 to form cavities 30 having a depth e30 less than or equal to the thickness ei 6 of the first conductive layer 16. These cavities 30 are located at the level of the spaces 40B extending between lower electrodes 41 of the pixels 40. These spaces 40B correspond to the spaces provided between the pixels 40.

[0129] The E22 etching substep is described in detail below.

[0130] With reference to [Fig.4], substep E22 begins with an operation E221 of forming an etching mask 20, for example in photosensitive resin, on the first conductive layer 16. Photolithographic processes known to those skilled in the art are implemented for this purpose.

[0131] In [Fig. 4], the spacing 20B between two adjacent portions 20A of the etching mask 20 corresponds here to the spacing 40B between two adjacent lower electrodes 4L. Furthermore, each portion of the etching mask 20 corresponds to a zone 40A of one of the lower electrodes 4L.

[0132] Next, as illustrated in [Fig.5], a first etching operation E222 of the first conductive layer 16 is carried out through the etching mask 20 to form the cavities 30.

[0133] This first E222 etching operation may be partial, as shown in [Fig.5]: indeed, the cavities 30 do not cross the first conductive layer 16. There therefore remains a residual layer of the first conductive layer 16 on the second conductive layer 17.

[0134] Each cavity 30 preferably has a depth e30 between 10 nm and 300 nm. The thickness ei6' of the first conductive layer disposed under the cavities 30 (also noted as "first residual conductive layer") is for example 100 nm.

[0135] Alternatively, the first E222 etching operation can be configured to reach the second conductive layer 17. In this configuration, not shown in the figures, the cavities 30 pass through the first conductive layer 16 and their bottom is made up of the upper surface of the second conductive layer 17.

[0136] The first E222 etching operation is preferably a dry etching type etching, such as reactive ionic etching (or RIE), induced-coupled plasma etching (or ICP), or ion beam etching (or IBE).

[0137] As shown in [Fig.5], when the E222 etching operation is partial, the first etching operation E222 makes it possible to obtain a first conductive layer 16 thicker at the lower electrodes 41 of the pixels 40 than at the regions 40B between the lower electrodes 41 of the pixels 40.

[0138] Finally, an E223 removal of the engraving mask 20 is implemented. This gives the structure illustrated in [Fig.6].

[0139] The fact that the cavities 30 obtained (after the first etching operation E222) in the first conductive layer 16 are not through-holes (in the configuration shown in [Fig.5]) produces a double effect: on the one hand, the residual first conductive layer protects the organic layers of the Ep stack during the removal E223 of the etching mask 20 and, on the other hand, it allows portions 431 of this first conductive layer 16 to be left on either side of the cavities 30 after the substep E23 described below.

[0140] In the configuration where the second conductive layer 17 is present and the etching E222 continues up to this second conductive layer 17, it is the second conductive layer 17 that protects the underlying organic layers (of the Ep stack) during the removal E223 of the etching mask. Furthermore, portions of the first conductive layer 16 remain on either side of the cavities 30.

[0141] In the next substep E23, the following operations are carried out to extend the cavities 30 to the substrate (in this case, to the insulating layer 12): • Anisotropic E231 etching of the first conductive layer 16 such that the cavities pass through the still-present first conductive layer 16, • anisotropic E232 etching of the second conductive layer 17 such that the cavities 30 pass through the second conductive layer 17, • Anisotropic E233 etching of the second stack of 422 organic layers such that the cavities 30 pass through this second stack of organic layers, • Anisotropic E234 etching of the CGL layer so that the cavities pass through the CGL layer, and • anisotropic E235 etching of the first 421 stack of organic layers so that the cavities 30 pass through the first 421 stack of organic layers.

[0142] By anisotropic etching, we mean an etching carried out along a preferential etching direction perpendicular to the plane {X,Y} of the substrate 11. Anisotropic etching allows the topology (i.e. the profile of the cavities 30) of the first conductive layer 16 to be preserved as obtained after the etching substep E22.

[0143] Anisotropic etching is preferably carried out using a ballistic physical etching process. This prevents etching on both sides of the cavities. Ballistic etching allows the cavities 30 to be extended while reducing the risk of damaging the organic layers of the stacks 421, 422 between the cavities 30.

[0144] Preferably, anisotropic etching is carried out under an oxygen-free atmosphere. The absence of oxygen helps to best preserve the performance of the organic layers, since these are particularly sensitive to this element.

[0145] For example, anisotropic engravings are carried out under vacuum according to a ballistic physical engraving process, preferably by exposure to an argon plasma.

[0146] As shown in [Fig.7], the pixels 40 are formed at the end of substep E23 and are separated from each other by the cavities 30.

[0147] Thus, initially, the anisotropic etching of the first conductive layer 16 makes it possible to reduce the thickness of the first conductive layer 16 uniformly (i.e. in the same way over the entire surface of the first conductive layer 16).

[0148] As the anisotropic etching of the first conductive layer 16 is carried out until the cavities 30 open onto the second conductive layer 17, the remaining first conductive layer 16 consists of conductive portions 431 spaced apart from each other (cf. [Fig.7]).

[0149] The remaining portions 431 of the first conductive layer 16 are illustrated in Figure 7. These conductive portions 431 remain on either side of the cavities 30, where the thickness of the first conductive layer (after the etching substep E22 and before the etching substep E23) was thickest. Each portion 431 of the first conductive layer 16 corresponds to, or constitutes, one of the first conductive portions 431 of the upper electrodes 43 of the pixels 40.

[0150] Thus, the depth e30 of the cavities 30 is less than 20 nm, preferably between 10 nm and 20 nm to obtain transparent first conductive portions 431. This configuration is chosen when the substrate 11 is opaque and the The second conductive layer 17 is transparent. This allows for a top-emitting device.

[0151] Alternatively, the depth e30 of the cavities 30 is strictly greater than 15 nm to obtain first reflective conductive portions 431. This configuration is preferably chosen when the substrate 11 is transparent. This makes it possible to obtain a top-emitting device.

[0152] In a second step, the underlying layers 17, 422, CGL, 422 to the first conductive layer 16 are etched anisotropically through the remaining first conductive layer 16 which serves as an etching mask. Thus, the first conductive portions 431 are not removed.

[0153] Anisotropic etchings E232, E233, E234 and E235 can be carried out with the same etching chemistry or with different etching chemistries, implemented in the same etching chamber or in different chambers of the same equipment.

[0154] Preferably, the layers underlying 17, 422, CGL, 422 to the first conductive layer 16 are further etched selectively with respect to the first conductive layer 16.

[0155] It is noted that the pixel formation step E3 is analogous to the steps used for the fabrication of inorganic semiconductor devices, but that it does not involve any mask removal operation (since this operation is not necessary).

[0156] This makes it possible to physically separate the OLED pixels without damaging the organic layers. Indeed, it avoids applying solvents (in the case of a resin mask), plasmas (in the case of a hard mask) and / or high temperatures, above 100°C, to the substrate and therefore into the environment of the organic layers, which are particularly aggressive, and therefore destructive, to the organic layers.

[0157] Furthermore, because the manufacturing process includes technological steps commonly used for the fabrication of inorganic semiconductor devices, it is simpler than prior art processes based on separation structures between pixels. The process also makes it possible to form pixels as small as 1 pm, or even less (i.e., to achieve the desired high resolution).

[0158] Now that the 40 pixels have been formed, the manufacturing process can advantageously proceed with steps E3, E4 and E5.

[0159] Step E3, illustrated in [Fig. 8], consists of conformally depositing a passivation layer 50 onto the substrate 11 and around the edges of the pixels 40. A conformal deposition technique is preferably implemented. For example, a technique of Atomic thin layer deposition (or ALD for "Atomic Layer Deposition" in English) is implemented.

[0160] The passivation layer 50 is made of a material that acts as an oxygen barrier. For example, it is made of alumina or SiO₂. The passivation layer 50 thus protects the active elements 43 from the external environment. In particular, it prevents the organic layers of these active elements from coming into contact with oxygen (they are particularly sensitive to this element).

[0161] The encapsulation layer 50 is also electrically insulating. This therefore enhances the electrical insulation of the pixels.

[0162] Step E4, illustrated in Figures 9 and 10, consists of forming a common electrode 60 electrically connecting the upper electrode of each pixel to the electrical track 13 arranged on the peripheral surface of the substrate 11.

[0163] This common electrode 60 allows current to be supplied to the upper electrodes of the pixels 40.

[0164] Step E4 includes for this purpose a substep E41, illustrated in [Fig.9], which consists of opening the passivation layer 50 on the upper face of the pixels 40. By thus exposing part of the passivation layer 50 on the pixels, an access 43a to the upper electrode 43 of each pixel 40 is created.

[0165] Masking operations using an etching mask (for example, a photosensitive resin), followed by etching and removal of the etching mask are carried out, for example, during this step E41. As the passivation layer 50 remains on the sides of the pixels 40, it protects the organic layers of the stacks 421, 422 from the external environment.

[0166] Since the height h40 of the pixels 40 is preferably between 100 nm and 200 nm, and the distance d40 between the pixels 40 is preferably between 500 nm and 1 pm, the ratio between the height h40 of the pixels and their spacing d40 is preferably between 0.1 and 0.4. This ratio is favorable to an efficient spreading of the photosensitive resin between the pixels 40.

[0167] Preferably, openings 113a are also created at this substep through the insulating layer 12 between the pixels 40, so as to free access to the contact points 113 of the substrate 11 (cf. [Fig.2]).

[0168] With reference to [Fig. 10], a substep E42 is then implemented to form a third conductive layer 60 of continuous thickness which extends around the edges of the pixels 40, over the first passivation layer 50 between the pixels 40 and up to the electrical contact track 13.

[0169] As openings 43a have been created in the passivation layer 50 at the upper electrodes 43 of the pixels 40 (see [Fig. 9]), the third conductive layer is also deposited in contact with these upper electrodes 43. The electrode common 60 is thus formed at least in part by the third conductive layer 60.

[0170] When openings 113a are also created through the insulating layer 12, the third conductive layer 60, and therefore the common electrode 60, connects each contact pad 113 of the substrate 11. Thus, the current distribution through each pixel 40 is carried out from a contact pad 113 located close to the pixel 40. This proximity of distribution makes it possible to reduce the contact resistance and to uniformize the current distribution through the pixels 40 of the display device 1.

[0171] The third conductive layer 60 is preferably formed by a directional deposition process (along a direction perpendicular to the {X,Y} plane of the substrate 11), preferably by a physical vapor deposition process such as evaporation. It should be noted that, since the height h40 of the pixels is small compared to the distance between the pixels (for example, there is a factor of 0.1 between this height and this distance), such a directional deposition process makes it possible to deposit conductive material also on the lateral peripheral surface of the pixels 40 (in addition to the horizontal surfaces). This eliminates the need for a more complex and costly conformal deposition process.

[0172] This third conductive layer 60 can be formed of a metal, for example silver, aluminium, or chromium.

[0173] It can then have a thickness of less than 15 nm to be transparent. Such a thickness is preferred when the substrate 11 is opaque and the lower electrodes are reflective. This makes it possible to obtain a top-emitting display device.

[0174] Alternatively, it can have a significant thickness, for example greater than 300 nm, to be reflective, in the case where the substrate 11 is transparent and where the lower and / or upper electrodes are also transparent. This makes it possible to obtain a bottom-emitting display device.

[0175] Alternatively, the third conductive layer 60 can be formed of a transparent conductive oxide or TCO.

[0176] With reference to [Fig. 11], step E5 consists of forming a second conformal passivation layer 70 on the third conductive layer 60. The second passivation layer 70 can be formed of the same material as the first passivation layer 50. It allows the display device to be encapsulated and thus protected and electrically isolated.

[0177] Figures 12 to 18 illustrate a second embodiment of the manufacturing process for manufacturing the electroluminescent display device 1 illustrated in [Fig. 19] (i.e. the second embodiment of the electroluminescent display device 1).

[0178] Primarily, this second implementation differs from the first implementation in that the 40 pixels are formed group by group. In other words, they are not all formed during step E2.

[0179] According to this second embodiment, the manufacturing process begins with a step identical to step El, illustrated in [Fig.2], of the first embodiment.

[0180] The manufacturing process continues with a step E2', illustrated in Figures 12 and 13. This step E2' differs from step E2 illustrated in Figures 3 to 5 in that a first group of pixels 40ijB (see [Fig. 13]) is formed on only a portion (typically one-third) of the lower electrodes 41 (it should be noted that, according to the first embodiment, there are as many pixels 40 as there are lower electrodes 41). Typically, of three adjacent lower electrodes, only one lower electrode is used to form the pixels 401,B of the first group (the other lower electrodes are labeled 40NR in [Fig. 13]).

[0181] The 40i>B pixels of this first group are then configured to produce a first color radiation, for example a blue color radiation.

[0182] Step E2' begins with a step identical to step E21 illustrated in [Fig.3], consisting of: • Deposit the first stack 421 of organic layers onto the active surface SA ct of the substrate 11 (in this case on the insulating layer 12), • Place the CGL layer on top of the first 421 stack of organic layers, • Place the second stack of 422 organic layers on top of the CGL layer, • Deposit the second conductive layer 17 onto the second stack of organic layers 422, and • Place the first conductive layer 16 on the second conductive layer 17.

[0183] The first and second stacks 421, 422 and the second conductive layer 17 are here configured to produce the first color radiation (in the chosen example, blue color, marked "B" in the figures.).

[0184] With reference to [Fig. 12], step E2' continues with a substep E22' of partial etching of the first conductive layer 16. As previously stated, substep E22' can alternatively be an etching configured to reach the second conductive layer 17.

[0185] This substep E22' comprises, like substep E22 illustrated in Figures 4 to 6, an operation to form an etching mask, followed by an etching operation partial removal of the first conductive layer 16 through the etching mask, followed by an etching mask removal operation.

[0186] The operation of forming the engraving mask according to this second embodiment is illustrated in [Fig. 12].

[0187] As shown in [Fig.12], the portions 20A' of the etching mask 20 no longer correspond to each lower electrode 41 (as illustrated in [Fig.4]) but to one lower electrode out of three, noted 41 i>B in [Fig. 12].

[0188] Step E2' continues by implementing substeps E22' and E23' which are respectively identical to substeps E22 and E23 previously described.

[0189] Fig. 13 shows the structure obtained at the end of this alternative step E2'. It includes 40ijB pixels (here in blue) formed on the substrate 11 and spaced two by two adjacent lower electrodes (not covered with materials, marked 41NR on Fig. 13).

[0190] The manufacturing process according to the second manufacturing method can optionally be continued with a step E3', illustrated in [Fig. 14]. This step E3' is analogous to step E3 illustrated in [Fig. 8]. It consists of depositing a passivation layer 50 around the edges of pixels 40ijB and between pixels 40ijB.

[0191] Next, the second group of pixels is formed during a step E6, illustrated in Figures 15 to 18.

[0192] The pixels in the second group are configured to produce a second radiation of a different color than the first radiation. For example, the second radiation is green. The pixels in the second group are labeled 402>v in Figures 17 and 18.

[0193] When step E3' of depositing the passivation layer 50 is implemented, step E6 begins with a substep E61, illustrated in [Fig.15]. Otherwise, step E6 begins with substep E62.

[0194] Substep E61 consists of opening the passivation layer 50 at the lower electrodes 412v of the pixels in the second group, to form access points 80 to these lower electrodes 412v-

[0195] Substep E62 is analogous to substep E21 illustrated in [Fig. 3]. Thus, with reference to [Fig. 16], we carry out: • a deposit, on the active surface SAct of the substrate, of a third stack of 4212 organic layers, • a deposit, on the third stack of organic layers, of a second layer CGL2 deposited during step E2', • a deposit, on the second layer CGL2, of a fourth stack of 4222 organic layers, • a deposit, on the fourth stack of 4222 organic layers, of a fifth conductive layer 172, and • a deposit of a fourth conductive layer 162 on the fifth conductive layer 172.

[0196] The second CGL2 layer is similar to the CGL layer, in that it fulfills the same role, namely interconnecting two stacks of organic layers, here the third and fourth stacks 4212, 4222 of organic layers. Furthermore, the second CGL2 layer is preferably formed of the same material as the CGL layer deposited in substep E21.

[0197] The third and fourth stacks of organic layers 4212, 4222 are configured to produce the second color radiation (in the chosen example, this second radiation is green, denoted "V" in the figures). These 4212, 4222 stacks of organic layers are intended to form the active elements 422>v of the pixels in the second group.

[0198] The fourth conductive layer 162 is similar to the first conductive layer 16, in that it is intended to form the first 4312 portions of the upper electrodes 432>v, of the pixels 402>v of the second group (cf. [Fig. 17]).

[0199] The fifth conductive layer 172 is similar to the second conductive layer 17 in that it is intended to form the second conductive portions 4322 of the upper electrodes 43 of the pixels 402>v of the second group.

[0200] Substep E63, like substep E22 of the first embodiment or substep E22' of this second embodiment, aims to partially etch the upper conductive layer (which is here the fourth conductive layer 162) to form non-through cavities. In this substep E63, the cavities extend between the pixels 40ijB of the first group and on either side of the lower electrodes of the pixels of the second group (denoted 412>v in [Fig. 16]).

[0201] For this, the same procedure is followed as for substep E22. Thus, an operation E631 for forming an etching mask on the fourth conductive layer 162 is implemented. This operation E631 is illustrated in [Fig. 16]. The portions 20A'' of the etching mask are positioned here at the lower electrodes 412>v of the pixels in the second group.

[0202] Next, a partial etching operation (not shown in the figures) of the fourth conductive layer 162 is performed through the etching mask 20 to form cavities having a depth strictly less than the thickness of the fourth conductive layer 162. The etching settings (chemistry, duration, etc.) are then similar to those used in operation E222. Alternatively, the etching operation is not partial but configured to reach the fifth conductive layer 172. The cavities 30 then have the fifth conductive layer 172 as their base.

[0203] Finally, the etching mask is removed using a process similar to the process implemented during operation E223.

[0204] In a substep E64 illustrated in [Fig. 17], the cavities formed in the preceding substep E63 are extended. The cavities are thus extended through the fourth conductive layer 162, then through the fifth conductive layer 172, the fourth stack of organic layers 4222, the second layer CGL2, and the third stack of organic layers 4212. The resulting cavities, labeled 302 in [Fig. 17], open onto the insulating layer 12. This results in the 402>v pixels of the second group and the 40ijB pixels of the first group being separated from each other.

[0205] Specifically, during this substep E64, the following anisotropic etching operations are performed: • Anisotropic etching of the fourth conductive layer 162 until reaching the fifth conductive layer 172, • anisotropic etching of the fifth conductive layer 172 until reaching the fourth stack of organic layers 4222„ • Anisotropic etching of the fourth stack of 4222 organic layers until reaching the second layer CGL2, • anisotropic etching of the second layer CGL2 until reaching the third stack of organic layers 4212 and • anisotropic etching of the third stack of organic layers 4212 until reaching the insulator layer 12.

[0206] The anisotropic etching configurations of the layers underlying the fourth conductive layer 162 are similar to the etching configurations of the layers underlying the first conductive layer 16, in the sense that they are preferably ballistic-type etchings, and / or preferably selective etchings with respect to the fourth conductive layer 162.

[0207] In an optional substep E65, analogous to step E3, a third passivation layer 50' can be conformally formed around the edges of the pixels and between the pixels. At the end of substep E65, the structure illustrated in [Fig. 18] is obtained. This structure comprises, in addition to the 40ijB pixels of the first group, the 402jV pixels of the second group, separated from each other by the cavities 302. These 40ijB, 401, and v pixels are covered by the passivation layer 50'.

[0208] Next, the third group of 403 R pixels is formed during a step E7, illustrated in [Fig.19],

[0209] The pixels in the third group are configured to produce a third radiation of a different color than the first and second radiations. For example, the third radiation is red. The pixels in the third group are labeled 403jR in [Fig. 19].

[0210] In this step E7, the procedure is the same as in step E6, as described below.

[0211] When step E6 includes the substep of depositing the 50' passivation layer, step E7 begins, like step E6, with a substep (not shown in the figures) of opening the 50' passivation layer so as to create access to each lower electrode 413jR of the pixels in the third group.

[0212] Step E7 continues with the operations described below. Note that when step E6 does not include the substep of depositing the 50' passivation layer, these operations are carried out at the beginning of step E7.

[0213] Step E7 then continues with the following operations: • Deposition, on the active surface SAct of the substrate, of a fifth stack of 4213 organic layers, • Deposition of a third CGL3 layer on the fifth 4213 organic layer, • Deposition of a sixth stack of 4223 organic layers on the third layer CGL3, • Deposition of a seventh conductive layer 173 on the sixth stack 4223, • Deposition of a sixth conductive layer 163 on the third stack of organic layers.

[0214] The third layer CGL3 is similar to the CGL layer and the second layer CGL2, in that it fulfills the same role, namely interconnecting stacks of organic layers (here the fifth and sixth stacks 4213, 4223 of organic layers). Furthermore, the third layer CGL3 is preferentially formed of the same material as the CGL layer deposited in substep E21.

[0215] The third and fourth stacks of organic layers 4213, 4223 are configured to produce the third color radiation (in the chosen example, this second radiation is red, denoted "R" in the figures). These stacks 4213, 4223 of organic layers are intended to form the active elements 423 r of the pixels in the third group.

[0216] The sixth conductive layer 163 is similar to the first conductive layer 16, in that it is intended to form the first 4313 portions of the upper electrodes 433 R of the pixels 403, R of the third group (cf. [Fig. 19]).

[0217] The seventh conductive layer 173 is similar to the second conductive layer 17 in that it is intended to form the second conductive portions 4323 of the upper electrodes 43 of the pixels 403, R of the third group.

[0218] Once the deposits of the materials intended to form the pixels of the third group have been deposited, step E7 continues, like step E6, with a substep of partial etching of the sixth conductive layer 163 to obtain non-through cavities between the pixels 40i, B, 412, v already formed and at the gaps between the lower electrodes 413>R of the pixels of the third group. Alternatively, the etching operation is not partial but configured to reach the seventh conductive layer 173. The cavities 30 then have the seventh conductive layer 173 as their bottom.

[0219] For this, we proceed in the same way as for substep E22.

[0220] The etching configurations (chemistry, duration, etc.) are then similar to those used during operation E222.

[0221] Once the non-through cavities are obtained, a sub-step illustrated in [Fig. 19] is implemented, as in step E6. This sub-step consists of extending the non-through cavities through the sixth conductive layer 163, then through the seventh conductive layer 173, the sixth stack of organic layers 4223, the third layer CGL3 and the fifth stack of organic layers 4213. The resulting cavities, labeled 303 in [Fig. 19], open onto the insulating layer 12. This results in the pixels 403, R of the second group, the pixels of the second group 402>v and the pixels 40ijB of the first group separated from each other.

[0222] As in substep E64, anisotropic etchings are made through the sixth conductive layer 163, and then through the layers underlying the sixth conductive layer 163. The anisotropic etching configurations are similar to the etching configurations described in relation to substep E64, or in relation to substep E23.

[0223] Finally, a fourth passivation layer 50” (see [Fig. 19]) is conformally formed around the edges of the pixels and between the formed pixels. At the end of step E7, the structure illustrated in [Fig. 19] is obtained. This structure comprises, in addition to the 40ijB pixels of the first group and the 402>v pixels of the second group, the 403>R pixels of the third group, separated from each other by the cavities 303.

[0224] Preferably, steps E4 and E5 are implemented on the display device illustrated in [Fig. 19].

[0225] According to a third embodiment, the manufacturing process makes it possible to form the display device 1 according to the third embodiment (illustrated in [Fig.20]).

[0226] The manufacturing process according to the third embodiment differs from the first embodiment (described in relation to Figures 2 to 7) in that, during substep E21, which consists of depositing the materials intended to form the pixels, operations E212, E213, and E214 are not performed. In other words, the manufacturing process does not include, during a pixel formation step E2', the following operations: • Deposition of the CGL layer onto the first stack of 421 organic layers, • Deposition of the second stack of 422 organic layers onto the CGL layer, • Deposition of the second conductive layer 17 on the second stack 422 of organic layers.

[0227] Since the CGL layer and the second stack of 422 organic layers are not deposited, the manufacturing process according to this third embodiment does not further include the following operations: • Anisotropic E232 etching of the second conductive layer 17, • Anisotropic E233 etching of the second 422-layer stack organic • Anisotropic E234 etching of the CGL layer.

[0228] It should be noted that the charge-carrying layers CGL, the second stack of 422 organic layers, and the second conductive layer 17 are therefore not essential.

[0229] Furthermore, the manufacturing process according to the third embodiment differs from the first embodiment (described in relation to Figures 2 to 7) in that the step E222 of etching at least a part of the first conductive layer 16 is configured so that the cavities 30 have a depth e30 strictly less than (and not less than or equal to) the thickness ei 6 of the first conductive layer 16. Indeed, in the absence of the second conductive layer 17, the residual thickness of the first conductive layer 16 protects the first stack of organic layers during the removal of the etching mask.

[0230] According to one embodiment, the second conductive layer 17 can be deposited on the first stack 421 of organic layers before the deposition of the first conductive layer 16. In this case, an anisotropic etching operation of the second conductive layer 17 deposited on the first stack 421 of organic layers is carried out between the anisotropic etching of the first conductive layer 16 and the anisotropic etching of the first stack of organic layers 421. Furthermore, the etching of at least a portion of the first conductive layer 16 is configured so that the cavities 30 have a depth less than or equal to the thickness of the first conductive layer 16.

[0231] According to a fourth embodiment, the manufacturing process makes it possible to form the 1 colour display device according to the fourth embodiment (illustrated in [Fig.21]).

[0232] This fourth embodiment differs from the third embodiment in that all the pixels are not formed in a single step E2', but in three steps, with organic layers configured to produce radiation of different colors (here, in the chosen example, of respective colors blue, green and red).

[0233] For this, we proceed in much the same way as for the second method of implementation, described in relation to figures 12 to 19.

[0234] Specifically, the fourth embodiment differs from the second embodiment only in the stages of deposition and anisotropic etching of the materials intended to form, or forming, the pixels.

[0235] Thus, compared to the second embodiment, the manufacturing process according to the fourth embodiment does not include, during a step E2” of pixel formation of the first group, the following operations: • Deposition of the CGL layer onto the first stack of 421 organic layers, • Deposition of the second stack of 422 organic layers onto the CGL layer, • Deposition of the second conductive layer 17 onto the second stack of organic layers 422, • Anisotropic etching of the second conductive layer 17, • Anisotropic etching of the second 422 stack of organic layers, • Anisotropic etching of the CGL layer.

[0236] Furthermore, the manufacturing process according to the fourth embodiment does not does not include, during step E6' of pixel formation of the second group, the following operations: • Deposition of the second CGL2 layer onto the third stack of 4212 organic layers, • Deposition of the fourth stack of 4222 organic layers onto the second layer CGL2, • Deposition of the fifth conductive layer 172 onto the fourth stack 4222 of organic layers, • Anisotropic etching of the fifth conductive layer 172, • Anisotropic etching of the fourth 4222 stack of organic layers, • Anisotropic etching of the second layer CGL2.

[0237] Finally, the manufacturing process according to the fourth embodiment does not include, during a step E7' of pixel formation of the third group, the following operations: • Deposition of the third layer CGL3 onto the fifth stack of 4213 organic layers, • Deposition of the sixth stack of 4223 organic layers onto the third layer CGL3, • Deposition of the seventh conductive layer 173 onto the sixth stack of organic layers 4223, • Anisotropic etching of the seventh conductive layer 173, • Anisotropic etching of the sixth 4223 stack of organic layers, • Anisotropic etching of the third layer CGL3.

Claims

1. Demands Method of manufacturing a device (1) comprising a plurality of pixels (40) arranged on a substrate (11), each pixel (40) comprising a lower electrode (41), an upper electrode (43), and an active element (42) disposed between the lower (41) and upper (43) electrodes, said method comprising the following steps: Provision (El) of a structure (10) comprising the substrate (11) and the lower electrodes (41) of the pixels (40), the lower electrodes (41) being spaced apart from each other and arranged on a first surface (SA ct) of the substrate (11), called the active surface (SA ct), Formation (E2) of a first group of pixels (40) on the substrate (11), by performing the following sub-steps: • Deposition (E21, E211), on the active surface (SA ct ) of the substrate, of a first stack (421) of organic layers configured to generate or absorb first radiation, • Deposition (E21, E215) of a first conductive layer (16) on the first stack (421) of organic layers, • Etching (E22) of at least a part of the first conductive layer (16) to form cavities (30) having a depth strictly less than the thickness (ei 6) of the first conductive layer (16), the cavities (30) being located at the right of spaces (40B) extending between lower electrodes (41) of the pixels (40) of the first group, • Anisotropic etching (E23) of the first conductive layer (16) and anisotropic etching (E23) of the first stack (421) of organic layers so as to extend the cavities (30) through the first conductive layer (16) and the first stack (421) of organic layers, residual portions (431) of the first conductive layer (16) remaining between the cavities (30), from which it results the pixels (40) of the first group separated from each other by the cavities (30).

2. A manufacturing method according to claim 1, wherein the substep (E23) of anisotropic etching is carried out under an oxygen-free atmosphere.

3. A manufacturing method according to any one of claims 1 to 2, wherein the supplied structure (10) comprises an electrically insulating layer (12) disposed on the active surface (SA ct) of the substrate (11) and laterally encasing the lower electrode (41) of each pixel (40), the electrically insulating layer (12) serving as a stop layer during the anisotropic etching (E23) of the first stack (421) of organic layers.

4. A manufacturing method according to any one of claims 1 to 3, wherein the step (E2) of forming the first group of pixels (40) on the substrate (11) further comprises: - between the deposition (E211) of the first stack of organic layers and the deposition (E215) of the first conductive layer, the deposition (E214) of a second conductive layer (17) formed of a metal, - between the anisotropic etching (E23) of the first conductive layer (16) and the anisotropic etching (E23) of the first stack (421) of organic layers, an anisotropic etching (E23) of the second conductive layer (17).

5. A manufacturing method according to claim 4, wherein the first stack (421) of organic layers is configured to generate the first radiation and wherein the step (E2) of forming the first group of pixels on the substrate further comprises: - Between the deposition (E211) of the first stack of conductive layers and the deposition (E214) of the second conductive layer, the following operations: - Deposition (E212) of an interconnecting conductive layer (CGL) on the first stack (421) of organic layers, the interconnecting conductive layer (CGL) being adapted to connect the first stack (421) of organic layers to a second stack (422) of organic layers, - Deposition (E213) of the second stack (422) of organic layers on the conductive interconnect layer (CGL), - Between the anisotropic etching (E23) of the second conductive layer (17) and the anisotropic etching (E23) of the first stack (421) of organic layers, an anisotropic etching (E23) of the conductive interconnect layer (CGL) and an anisotropic etching of the second stack (422) of organic layers, from which results the pixels (40) separated from each other and having a multi-stack structure also called tandem structure.

6. A manufacturing method according to claim 5, wherein the interconnecting conductive layer (CGL) is formed of a metallic or organic conductive material.

7. A manufacturing method according to any one of claims 1 to 4, wherein the first conductive layer (16) is formed of a metal and has an initial thickness (ei 6) determined so that the thickness (e431) of the residual portions of the first conductive layer (16) is less than 20 nm, preferably between 10 nm and 20 nm.

8. A manufacturing method according to any one of claims 1 to 7, comprising, after the step (E2) of forming the pixels on the substrate, a step (E3) of depositing a passivation layer (50) on the peripheries of the pixels (40) and on the surface of the substrate (11).

9. A manufacturing method according to claim 8, wherein the deposition (E3) of the passivation layer (50) is carried out in a conforming manner.

10. A manufacturing method according to any one of claims 8 to 9, comprising, after the step (E3) of depositing the passivation layer, a step (E4) of forming a common electrode (60) comprising the following substeps: - Opening the passivation layer (50) so as to create access to the upper electrode (41) of each pixel (40), - Forming a continuous third conductive layer (60) on the pixels (40) and on the substrate between the pixels and on an electrical contact track (13) disposed on a second surface (SPERI) of the peripheral substrate at the

11.

12.

13.

14. active surface, from which results the common electrode (70) connecting the upper electrode (43) of each pixel (40) to the electrical contact track (13). Manufacturing method according to claim 10, wherein the third conductive layer (60) is transparent. Manufacturing method according to claim 10, wherein the third conductive layer (60) is reflective and the substrate (11) is transparent. Manufacturing method according to claim 12, wherein the third conductive layer (60) has a thickness greater than 50 nm. A manufacturing method according to any one of claims 8 to 13, comprising, after the step (E3) of depositing the passivation layer, a step (E6) of forming a second group of pixels on another part of the lower electrodes, comprising the following substeps: Opening the passivation layer to create access to each lower electrode of the pixels in the second group, Deposition, on the active surface of the substrate, of a third stack of organic layers configured to generate or receive a second radiation distinct from the first radiation, Deposition of a fourth conductive layer on the third stack of organic layers, Etching at least part of the fourth conductive layer to form cavities having a depth less than or equal to the thickness of the fourth conductive layer, the cavities being located at the right-hand side of spaces extending between the lower electrodes of the pixels of the second group, Anisotropic etching of the fourth conductive layer and anisotropic etching of the third stack of organic layers so as to extend the cavities through the fourth conductive layer and the third stack of organic layers, with residual portions of the fourth conductive layer remaining between the cavities, from which it results, in addition to the pixels of the first group, the pixels of the second group separated from each other by the cavities.

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