METHOD FOR PRODUCING A MICROELECTRONIC DEVICE ON AN FD-SOI SUBSTRATE, CORRESPONDING DEVICE AND INTEGRATED CIRCUIT INCORPORATING IT

Abstract

The production of a microelectronic device on an FD-SOI substrate comprises: the formation in the substrate (11) of a first wafer, first boxes made of insulating material adapted to form shallow isolation trenches (STI) (14); the formation, on a second wafer, of a strained silicon (sSi) film (23) covered with an oxide layer (24); the bonding of the second wafer to the first wafer, after vertical flipping, whereby the oxide layer becomes a buried oxide layer (BOX), covered by the sSi film which thus becomes a strained silicon film on insulator; the dismantling of the donor substrate while leaving the BOX layer and the sSi film; and the formation of second SSTI isolation trenches (34) by local oxidation of the silicon of the sSi film, which join the STIs via the BOX, to form complex isolation structures (STI-BOX-SSTI). Figure for the abstract: [Fig.11]

Description

Title of the invention: METHOD FOR PRODUCING A MICROELECTRONIC DEVICE ON AN FD-SOI SUBSTRATE, CORRESPONDING DEVICE AND INTEGRATED CIRCUIT INCORPORATING IT Technical field

[0001] The invention relates to the field of the microelectronic industry, or semiconductor industry, and concerns the manufacturing of a microelectronic structure on an SOI substrate (acronym for "Silicon-On-Insulator" in English, which means silicon on insulator). The invention also concerns the microelectronic structure obtained by such a manufacturing method.

[0002] It finds applications, in particular for the manufacture of integrated semiconductor devices, such as microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS), or microelectronic or optoelectronic devices, such as for example an image sensor (or imager) in CMOS technology (from the English “Complementary Metal-Oxide-Semiconductor”) or any other microelectronic device produced in this technology. State of the prior art

[0003] Since the 1950s, the microelectronics industry has been engaged in a race to miniaturize microelectronic devices, the basic element of which is the field effect transistor, and in particular the MOS transistor (from the English "Metal-Oxide-Semiconductor"), notably in CMOS technology, which is used as a switching element between two distinct electrical states corresponding to two opposite logical states (1 or 0 in binary logic). The miniaturization of MOS transistors has been accompanied by better control of their electrical properties, and in particular of the quantity of current which flows per unit of time through the conduction channel of these transistors, on which the speed of their switching depends.

[0004] However, the speed of the current is mainly determined by the material it flows through. Since microelectronic chip manufacturers are more or less limited to using silicon (Si) substrates, they have focused on increasing switching speed by reducing the size of transistors, for example MOS transistors, particularly in CMOS (Complementary Metal-Oxide-Semiconductor) technology.

[0005] In this context, silicon-on-insulator (SOI) substrates have become widely used nowadays for the manufacturing of transistor-based microelectronic devices. But after several decades of improvements in technological processes, the industry found it increasingly difficult to further reduce the size of transistors.

[0006] This is why the technique developed by Leti (laboratory of the French Alternative Energies and Atomic Energy Commission (CEA)) and its partners a good twenty years ago, and known as FD-SOI (from the English "Fully-Depleted Silicon-On-Insulator"), then consisted of proposing a new architecture of ultrathin MOS transistors, with a channel which can therefore be totally "deserted" (in English: "fully depleted", FD), that is to say without doping elements. The FD-SOI technique has made it possible to pursue the challenge of miniaturization, while combining high performance and low energy consumption, particularly in integrated circuits for analog applications in millimeter waves and radiofrequency (RF) waves up to 100 GHz, for example for 5G telephony. FD-SOI technology makes it possible to achieve even higher technology nodes less than or equal to 10 nm, or even 7 nm.

[0007] FD-SOI technology differs from conventional thicker SOI structures, such as classic MOS transistor technology whose channel is formed in a bulk silicon substrate, and FinFET (Fin Field-Effect Transistor) technology proposed by Intel® in which a fin field-effect transistor, which is a non-planar transistor (or "3D transistor"), is built on a bulk substrate where the gate is placed on two, three or four sides of the channel, forming a multi-gate structure. Compared to these technologies, FD-SOI technology makes it possible to increase the speed of current flow because the components are formed not in a bulk silicon block but in an ultra-thin silicon layer placed on a thin insulating oxide layer, itself placed on the silicon substrate, which no longer needs to be doped.Thus, transistors made on an SOI substrate, which are planar transistors and therefore simpler to make than FinFET transistors, are less sensitive to current leaks between the source and their drain on the one hand, and the silicon of the carrier substrate on the other hand, which increases the speed at which they switch without it being necessary to make them smaller.

[0008] But we also know that the speed of current flow also depends on the crystalline structure of the silicon. This is why SOI substrates are currently tending towards the use of strained silicon (Si), for the production of active zones of microelectronic devices such as the channel of transistors in CMOS technology. The use of strained silicon or sSI (from the English "strained Silicon"), currently constitutes one of the most important factors in the acceleration of CMOS technology on silicon. The improvement of the mobility of charge carriers electrical which is obtained by applying an appropriate constraint to the structure of the crystal lattice in fact makes it possible to increase the speed of these charge carriers in the channel of the MOS transistor, which results in a higher current for a fixed supply voltage and gate oxide thickness.

[0009] In practice, strained silicon (sSi) is a layer of silicon in which the silicon atoms are stretched (tension) or compressed (compression) beyond their normal interatomic distance. A tension-strained silicon layer can be achieved by placing a thin layer of silicon on a silicon-germanium (SiGe) substrate. When the atoms in the silicon layer align with the atoms in the underlying silicon-germanium layer (which are arranged slightly further apart, compared to those in a bulk silicon crystal), the bonds between the silicon atoms are stretched, resulting in a distorted lattice of silicon atoms. This improves the mobility of these charge carriers, resulting in better chip performance and lower power consumption.Electrons can thus move 70% faster, which allows sSi NMOS transistors to have a switching speed increased by 35%.

[0010] FD-SOI technology and the use of sSi can be combined, in order to combine the respective advantages of these two major technological advances. This consists of bonding a strained silicon (sSi) film over a very thin layer of buried oxide or BOX (from the English "Buried Oxide") formed on an undoped silicon support. The bonding of a strained silicon (sSi) film on such a substrate is described, for example, in the prior art documents EP 1923912 A1 and US 5691231 A.

[0011] The thinness of the oxide layer (BOX) under the strained silicon (sSi) film is a source of bonding problems when the thin film is continuous (i.e. devoid of patterns). This is due, in particular, to the fact that the hydrogen gas of the atmosphere under which the bonding operation is carried out must be absorbed by the BOX for the bonding to take place, and when the BOX is very thin then there is a risk of bonding defects. The solution disclosed in document EP 1923912 A1 for bonding a portion of a donor wafer comprising the active layer of the microelectronic device on a support wafer, provides a satisfactory response to the problems of bonding the sSi film on the BOX.

[0012] However, it is found that the subsequent production of etched patterns forming shallow trench isolation or STI (from the English "Shallow Trench Isolation") between components produced at respective adjacent positions in the active layer of the microelectronic device, in turn poses problems. Shallow trench isolation (STI), also known as the box isolation technique, prevents leakage of electric current between components adjacent components of a microelectronic device which are made on the same semiconductor substrate provided that said laterally adjacent components are isolated from each other by such an insulating trench. The STI technique has generally been used, for many years, in CMOS technologies of 250 nanometers and less.

[0013] However, when one seeks to create active zones isolated from one another and each comprising a respective portion of a strained silicon film (in sSi), one notes that the strain of the sSi tends to relax, that is to say to decrease at the edges of the active zones created, where said sSi film is cut. This occurs when the etching of the patterns intended to be filled with the insulator to form the STI isolation trenches is carried out, given that said etching physically breaks the sSi film. Presentation of the invention

[0014] The invention aims to remedy at least in part the drawbacks of the prior art, and more particularly to propose an alternative to the formation of shallow isolation trenches (STI) in accordance with current practice, which avoids relaxing the silicon stress in disjointed portions of a continuous strained silicon film due to the formation of said isolation trenches which separate said continuous film into said disjointed portions, in order to preserve its good electrical conduction properties.

[0015] For this, the object of the invention is a method of manufacturing a microelectronic device, said method comprising: • the provision of a first plate comprising a support substrate; • the formation, on the support substrate of the first plate, of first isolation trenches; • providing a second plate comprising a donor substrate; • the formation, on the donor substrate of the second plate, of a film of strained silicon, • bonding the second plate to the first plate, so that the strained silicon film is found on the first plate via at least one layer of insulating material formed, before bonding, on the first plate after the formation of the first trenches and / or on the second plate after the formation of the strained silicon film; • disassembly of the donor substrate while retaining the layer of insulating material and the strained silicon film on the first wafer; • the formation of second isolation trenches around and / or along portions of the strained silicon film.

[0016] Thus, embodiments of the invention are based on the combination: • bonding a donor wafer comprising a strained silicon film to be transferred onto a support wafer having patterns forming isolation trenches (STI); on the one hand, and, • additional oxidation of the strained silicon film which is carried out after the transfer of said film onto the support wafer, on the other hand, to create further shallow isolation (STI) trenches that join the insulator of the STI trenches already present deeper, without cutting the strained silicon film. Advantageously, the strained silicon film is not cut, in fact, because it is simply transformed locally into silicon dioxide. As a result, there is no relaxation of the silicon stress in the respective portions of the strained silicon film that are created by the formation of said isolation trenches.

[0017] Some preferred but non-limiting aspects of this method are as follows.

[0018] In embodiments, it can be provided that: • the first isolation trenches formed in the support substrate of the first wafer are so-called “shallow trenches”, or STI, the depth of which is greater than approximately 5 nm, or between approximately 5 nm and approximately 300 nm, preferably between approximately 50 nm and approximately 300 nm, and even more preferably between approximately 70 nm and approximately 300 nm; and / or • the second isolation trenches have a depth equal to or greater than the thickness of the strained silicon film, for example between approximately 10 nm and approximately 20 nm, for example of the order of 15 nm.

[0019] The insulating material of the first trenches, the insulating material of the second trenches and / or the insulating material of the insulating material layer, may be silicon dioxide (SiO2).

[0020] In embodiments, the formation of the first trenches in the donor substrate may be carried out by etching through a first mask previously produced by photolithography in a layer of hard material such as for example a nitride, which covers the support substrate provided by means of an associated layer of insulating material, residues of said first mask and of said associated layer of insulating material being removed from the support substrate after the formation of said first trenches.

[0021] In embodiments, the method further comprises the formation of third isolation trenches made through a second mask previously made by photolithography in a layer of hard material such as for example a nitride, which is deposited over an associated layer of insulating material itself deposited on the strained silicon layer after disassembly of the donor substrate, residues of said second mask and said associated insulating material layer being removed after the formation of said third trenches.

[0022] For example, the second isolation trenches join the first trenches through the layer of insulating material to form an isolation structure around and along the strained silicon film.

[0023] The second trenches can be made by local oxidation of the silicon of the strained silicon film, for example the local oxidation of the silicon of the strained silicon film is a thermal oxidation, for example a LOCOS type oxidation.

[0024] In embodiments, disassembly of the donor substrate may be achieved by grinding, selective removals, or fracture by implantation, for example by implementing the Smart-cut® process.

[0025] The donor substrate of the second wafer may comprise a silicon-germanium, Si-Ge, layer adapted to constrain the silicon of the constrained silicon film.

[0026] In embodiments, at least one opening may be further provided through the thickness of one of the second trenches and through the layer of insulating material to expose the underlying support substrate, in an area of ​​said support substrate in which there are no first trenches, and in which, in addition, the silicon (Si) of the support substrate is grown upwards by epitaxial growth in the opening, at least up to and including the level of the layer of insulating material.

[0027] In embodiments, at least some of the second isolation trenches may have the same horizontal dimensions as associated first trenches, and are respectively vertically aligned with said associated first trenches.

[0028] According to a second aspect of the invention, there is also provided a microelectronic structure obtained by implementing the manufacturing method according to the first aspect above, said structure comprising active zones disjointed on the surface of the same carrier substrate and isolated from each other by deep and less deep isolation trenches, each active zone having a respective portion of strained silicon film, and said portions of strained silicon film resting on the same insulating layer which is itself located above the carrier substrate.

[0029] The strained silicon can be, for example, of the totally deserted silicon on insulator type.

[0030] The insulating material of the first trenches, the insulating material of the second trenches and / or the insulating material of the insulating material layer, may be silicon dioxide (SiO2).

[0031] The second trenches may have non-vertical sides.

[0032] According to yet a third aspect, there is provided an integrated circuit comprising the microelectronic structure according to the second aspect above, and further comprising at least one MOS type field effect transistor produced in an active zone of said micro structure, the strained silicon film portion of which serves as a fully depleted silicon on insulator (FD-SOI) substrate in which the channel of the MOS transistor is produced. Brief description of the drawings

[0033] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the appended drawings in which: • Figures [Fig.lA] to [Fig.lC] are schematic views in vertical section, at respective stages of its preparation, of an example of a support wafer having shallow isolation trenches (STI) made, in accordance with embodiments of the invention, before bonding the donor wafer to said support wafer; • [Fig.2] is a schematic view in vertical section of an example of a donor wafer comprising a layer of strained silicon, intended to be transferred by bonding onto the support wafer of [Fig.1C]; • [Fig.3A] schematically illustrates the bonding, on the support wafer, of the donor wafer with its strained silicon layer, after vertical turning of said donor wafer; • [Fig.3B] is a schematic view showing, in vertical section, the new plate obtained after the bonding schematically illustrated by [Fig.3A]; • [Fig.4] is a schematic view, in vertical section, of the wafer of [Fig.3B] after removal from the substrate of the (formerly) donor wafer; • [Fig.5] shows a schematic, in vertical section, of the wafer of [Fig.4] after formation of an oxide insulation layer then a nitride passivation and protection layer; • [Fig.6] shows, in vertical section, the wafer of [Fig.5] after the formation, through the oxide and nitride layers, of wells exposing the strained silicon layer which has been transferred to the support wafer; • [Fig.7] is a schematic view, in vertical section, of the wafer after filling the boxes of [Fig.6] with insulating material to form insulation trenches by local oxidation of the strained silicon, which isolation trenches join the deeper trenches already made in the substrate of the support wafer before the transfer of the silicon film constrained by bonding of the donor wafer; • [Fig.8] shows the microstructure of [Fig.7] after removal of the hard mask in dielectric nitride; • [Fig.9] is a schematic view, in vertical section, of the wafer finally obtained after removal of the oxide residues, and planarization; • [Fig. 10] is a step diagram schematically illustrating example steps of implementations of the method according to the invention; and, • [Fig.l 1] is a schematic view, in vertical section, of an example of an electronic circuit obtained by the process, after the creation of openings allowing access to the silicon of the carrier substrate. Description of detailed embodiments

[0034] In the figures and in the remainder of the description, the same references represent identical or similar elements. In addition, the different elements are not shown to scale so as to enhance the clarity of the figures. Furthermore, the different embodiments and variants are not mutually exclusive and can be combined with each other.

[0035] In the following, the terms "substantially", "approximately", or "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and ...", or equivalent terms, mean that the limits are included, unless explicitly stated otherwise.

[0036] By the expression "formed from", used in reference to a material and to an element of interest, it is meant that the material is a compound formed from a plurality of elements including at least said element of interest.

[0037] The expression "material predominantly comprising" an element of interest means a material of which at least 50% by volume is formed by, or comprises said element of interest.

[0038] The term "wafer" refers to a very thin plate of monocrystalline semiconductor material (also called a "wafer" by borrowing this term from the Anglo-Saxon language), on which microelectronic devices can be made. Wafers are used in the microelectronics industry as a support for manufacturing microstructures, to manufacture microelectronic devices, before their integration into a package ("packaging" in English) to obtain an integrated circuit. Wafers comprise a base of doped semiconductor material, such as silicon (Si), gallium arsenide (GaAs) or indium phosphide (InP). This doped semiconductor material serves as a substrate for the creation of microstructures forming the active microelectronic devices which are part of the composition of integrated circuits, transistors, power semiconductor products, MEMS or NEMS, etc. This manufacturing uses design techniques such as, for example and without limitation: photolithography, doping, etching, deposition of other materials in layers or by diffusion or by any other physicochemical reaction, polishing, etc. Industrially produced wafers generally have dimensions between 25.4 mm (1" technology) and 300 mm (8" technology), for a thickness of around 0.7 mm.

[0039] By "layer" is meant an area of ​​a crystalline material whose thickness along the Z axis is less, for example ten times or even twenty times, than its longitudinal dimensions of width and length in the XY plane.

[0040] By "anisotropic etching" is meant that the etching speed of the silicon is not the same in all directions during the etching process. On the contrary, only the vertical direction of the silicon is etched during the etching process, the lateral direction not being etched. Conversely, "isotropic etching" does not favor any etching direction, so that all exposed surfaces are etched simultaneously, regardless of their orientation in space, i.e., whether they are horizontal, vertical, or inclined.

[0041] Chemical-Mechanical Polishing or CMP (from the English "Chemical-Mechanical Polishing") is a surface smoothing process using the combined action of mechanical abrasion forces and chemical attacks on the surface of a material to be treated by the use of an abrasive polishing suspension ("slurry"), having the effect of removing the material(s) on the surface of the wafer and erasing any surface topography, resulting in the planarization of the surface of the wafer exposed to this process. The duration of the CMP process is given by the removal speed as well as by the thickness of material to be removed before reaching a possible stop layer.

[0042] The term "photoresist" refers to a material used in photolithography, more specifically a polymer resin, which is sensitive to light and is used to form a pattern on a wafer. This is done by using an optical mask formed of opaque areas and transparent areas that define the pattern that is to be reproduced on the wafer, through which the photoresist is illuminated. The photoresist has its properties modified at the transparent areas of the optical filter, due to this illumination.For example, a "positive" photoresist is a light-sensitive polymer which, when exposed to ultraviolet (UV) light, transforms into a soluble material: the areas exposed to this illumination can then be dissolved using a solvent, leaving behind (known as development in the jargon of the person skilled in the art) a patterned, intaglio layer which can be used as a mask for the formation of a . structure through the mask thus formed. For example, the structure may be formed by etching a pre-existing underlying material that is selective to the mask material, or by ion implantation into such an underlying material, or by deposition of new material in the areas exposed by the mask.

[0043] Finally, here and for the remainder of the description, a direct three-dimensional orthogonal reference frame (X, Y, Z) is defined, where the X and Y axes form a plane parallel to the main plane of the support plate in question, and where the Z axis is oriented substantially orthogonally to the main plane of the plate, this Z axis being oriented in the direction of the axis of gravity. In the remainder of the description, the terms "vertical" and "vertically" are understood as relating to an orientation substantially parallel to the Z axis, and the terms "horizontal" and "horizontally" as relating to an orientation substantially parallel to the (X, Y) plane.Furthermore, the terms "above" and "below" and their derivatives (such as "above" and "below", or "over" and "below"), as well as the terms "lower" and "upper", used to qualify an element of the microstructure considered, are understood as being relative to an increasing positioning when moving away from the wafer upwards, i.e., along the vertical direction +Z.

[0044] The term "back" and the term "front", on the other hand, are used in reference to the face of a wafer by which the various treatments are, or have been, carried out to produce the microstructure in question. Since these treatments are systematically carried out from above when the wafer is laid flat in an enclosure used to carry out the treatment, the "front" face is generally (and by default) the upper face of the wafer. However, when a wafer or a chip cut from a wafer are turned vertically, their front face becomes the lower face and their back face becomes the upper face.The term "back" as applied to the semiconductor substrate of an individual wafer or chip is also used in reference to this convention, in that it refers to the portion of the substrate that is furthest from the face of the wafer or chip at which processing has been performed on the substrate, and is always referred to as the back face even when the wafer or chip has been turned vertically.

[0045] In the following description of embodiments of the method, the microelectronic device of interest is formed on a carrier wafer, from a base carrier wafer and a donor wafer which are assembled by bonding after vertically turning the donor wafer to form a new carrier wafer onto which a strained silicon film has been transferred. This wafer is intended for the manufacture of an integrated semiconductor product, for example in CMOS technology, and the method aims to manufacture shallow isolation trenches (STI) in a manner compatible with preserving the advantages of FD-SOI technology. The methods of implementing the process described can be adapted to the specific characteristics of each application concerned, without departing from the teachings of the invention.

[0046] As shown in [Fig.lA], the support wafer 1 is based on a carrier substrate 11, for example a monocrystalline silicon substrate. The carrier substrate 11 is lightly doped, for example with a P-type doping. Such doping can be obtained by inserting electron acceptor type atoms, such as Boron (B) atoms, into the substrate.

[0047] With reference to steps 101 and 102 of the step diagram of [Fig. 10], in step 101, a protective layer 12, typically based on oxide (Ox), is deposited on the substrate 11, then in step 102, a layer of hard material, for example based on dielectric nitride (Nx), is deposited, intended for the formation of a hard mask for an etching operation which will follow in order to form shallow isolation trenches or STI (“Shallow Trench Isolation”).

[0048] The oxide of the layer 12 may be, for example, silicon dioxide (SiO2). The deposition of SiO2 may be a deposition carried out by chemical means, such as for example low pressure chemical vapor deposition or LPCVD (standing for "Low Pressure Chemical Vapor Deposition" in English) to form high temperature oxide (HTO, standing for "High Temperature Oxide", in English). It may also be chemical deposition, for example plasma-assisted vapor deposition or PECVD (standing for "Plasma Enhanced Chemical Vapor Deposition" in English), of tetraethyl orthosilicate (or TEOS standing for "tetraethylorthosilicate", for short), of chemical formula Si(OCH2CH3)4 or more simply Si(OEt)4 as a precursor of silicon dioxide (SiO2), followed by a simple hydrolysis which then makes it possible to form SiO2 by releasing ethanol (CH3CH2OH).Alternatively, deposition can also be achieved by a physical process, such as sputtering, or spin-off deposition methods.

[0049] The dielectric nitride of layer 13 may be, for example, silicon nitride or Si3N4 (denoted SiN for short). This hard material may be deposited by chemical vapor deposition (CVD), for example by low-pressure chemical vapor deposition (LPCVD). Such a method operates at a relatively high temperature. Alternatively, the silicon nitride layer 13 may be formed by plasma-enhanced chemical vapor deposition (PECVD), which operates at a relatively lower temperature and in a vacuum. The resulting SiN layer may have a thickness, for example, of about a hundred nanometers (nm). Other dielectric materials, including titanium (TiN) and tungsten (W) nitrides, as well as different types of nitrided oxides, may also be used, as an alternative or in addition to silicon nitride (SiN).

[0050] Referring now to [Fig. 1B], the preparation of the support wafer 1 continues with the production of isolation trenches 14, namely shallow isolation trenches (STI), in the thickness of the substrate 11 of the wafer 1. According to one embodiment, and with reference to the step diagram of [Fig. 10], this production comprises the sequence of the following steps: • a photolithography step 103 defining the areas to be etched in the Si3N4 layer 13 and the SiO2 protective layer 12, by forming a hard mask for this etching; • a step 104 of etching the layer 13 and the layer 12 in Si3N4 and in SiO2, respectively, through the hard mask formed in step 103, to dig wells intended to form the isolation trenches 14 (STI) in the silicon 11; and, • a step 105 of filling the trenches with insulating material to form said STIs.

[0051] In step 103, the mask necessary for etching is exposed using a standard photolithographic process.

[0052] In step 104, the selective etching of the silicon nitride of the layer 13, then of the silicon dioxide (SiO2) of the protective layer 12 can be an anisotropic etching such as a reactive ion etching RIE (from the English "Reactive Ion Etching"). This is a variation of plasma etching (dry etching, highly anisotropic) combining the selectivity of chemical etchings and the anisotropy of physical etchings. The plasma can then be a fluoro-carbon plasma, based on a gas such as carbon tetrafluoride (CF4) for example, or based on sulfur hexafluoride (SF6) or even based on nitrogen trifluoride (NF3), or any combination of these gases. The layer of insulating material to be etched, partially protected by the etching mask formed for example by a partially open layer of silicon dioxide, is placed in a chamber in which a vacuum is created.This chamber is equipped with two horizontal and parallel electrodes, the lower electrode serving as a plate to receive the wafer. Once the vacuum in the chamber has been created, the gas is introduced. Then a strong radiofrequency (RF) electric field, for example of a hundred volts per meter or more, is applied to the lower electrode. This generates a plasma in the chamber, that is to say a partially ionized gas. Indeed, certain electrons from the gas molecules are torn off by the electric field, which ionizes said molecules. The upper face of the wafer then undergoes a bombardment of ions which disintegrates it at the level of the areas not protected by the hard mask. Alternatively, the selective etching of step 104 can be a chemical etching (or wet etching) by a hydrofluoric acid (HF) based solution by . example, or physical etching (or dry etching), i.e. plasma etching.

[0053] In step 105, a gapfill is carried out of the trenches 14 previously formed in step 104 with a thick oxide, for example silicon dioxide (SiO2). This step 105 makes it possible to deposit the insulating material from the upper surface of the microstructure to the bottom of the trenches 14. A chemical mechanical polishing or CMP makes it possible to eliminate the excess SiO2 deposited on the surface, and to smooth the upper surface of the microstructure as shown in [Fig.lB] which illustrates the microstructure after the sequence of steps 103, 104 and 105. As the person skilled in the art will have understood, the oxide deposited in step 105 in the trenches 14 makes it possible to produce the STI isolation trenches in the substrate 11 of the support wafer 1 even before the deposition of the silicon layer strained by transfer from the donor wafer 2.

[0054] In embodiments, the depth of the trenches 14 is greater than about 5 nm. It may be between about 5 nm and about 300 nm, preferably between about 50 nm and about 300 nm, and even more preferably between about 70 nm and about 300 nm.

[0055] Alternatively, the trenches 14 may be filled with a silicon nitride (SiN) for example Si3O4, instead of silicon dioxide SiO2.

[0056] Referring now to [Fig.1C], the following step 106 is a chemical-mechanical polishing (CMP) step with stopping on the silicon of the substrate 11, which allows the simultaneous removal of the hard nitride mask of the layer 13, and of the silicon dioxide residues of the layer 12. If necessary, a slight oxidation of the silicon of the substrate 11 is carried out after stopping the CMP etching, to restore protection by a thin layer of silicon dioxide (SiO2). Alternatively, the CMP etching on the nitride can be stopped. The nitride is then removed chemically and the silicon dioxide is removed for example by wet chemical means, using a hydrofluoric acid (HF) solution, for example.

[0057] The diagram of [Fig.2] shows the donor wafer 2 which comprises a strained silicon (sSi) film. For example, the sSi film is a thin layer 23 of silicon (Si) in which the silicon atoms are stretched beyond their normal interatomic distance. This can be achieved by depositing the thin silicon layer 23 on a silicon-germanium (SiGe) based substrate 22, by any suitable silicon deposition method, said SiGe substrate 22 itself being formed on a base silicon substrate 21. When the atoms of the thin silicon layer 23 align with the atoms of the underlying silicon-germanium layer 22 (which are arranged a little further apart from each other, compared to those of a bulk silicon crystal), the bonds between the silicon atoms of the layer 23 are stretched, which gives rise to a lattice of silicon atoms that is deformed. The separation of these silicon atoms reduces the atomic forces that interfere with the movement of electrons through the channel of a MOS transistor formed in such a layer 23 of strained silicon (sSi). This improves the mobility of these charge carriers, which results in better performance of the transistor and lower power consumption. The donor wafer 2 finally comprises an oxide layer 24, based for example on silicon dioxide (SiO2). Alternatively, 1, instead of silicon dioxide SiO2, the layer 24 may be made of another insulating material, in particular another oxide, for example a metal oxide such as aluminum oxide (A12O3), germanium oxide (GeO2), tin oxide SnO2 is a semiconductor and lead oxide PbO21, hafnium oxide (HfO2) or tantalum oxide (Ta2O5).

[0058] It will be noted that the production of the donor wafer 2 as shown in [Fig. 2] is not described in detail here, so as not to unnecessarily burden the present description. Indeed, this production has nothing specific to the implementations of the method of the invention. As needed, the person skilled in the art may refer to the literature available in the prior art concerning FD-SOI technology.

[0059] With reference to the schematic representation of [Fig.3A], in step 107 the donor wafer 2 is turned vertically, then aligned and bonded to the support wafer 1, to give the microstructure 3 shown in [Fig.3B] (which may sometimes be called the new support wafer 3, in what follows). The person skilled in the art will appreciate that, from the point of view of the upper surface of the microstructure 3, the oxide of the oxide layer 24 of the donor wafer 2 becomes buried oxide or BOX (from the English "Buried Oxide"). For reasons of simplicity of illustration this BOX is shown in [Fig.3A] as being only on the donor wafer 2, but the support wafer 1 can also have, in the same way, an oxide layer deposited after the CMP step 106 which concerns it, to promote the bonding conditions. Alternatively, it can be provided that only the support wafer 1 has this oxide layer, and not the donor wafer 2.

[0060] With reference to [Fig.4], the substrate 21-22 is then disassembled from (formerly) the donor wafer 1, shown by step 108 of the step diagram above [Fig. 10].

[0061] In embodiments, this can be achieved by implementing the SmartCut® process invented by the CEA, according to which the microstructure 3 consisting of the donor wafer 2 bonded to the original support wafer 1, is subjected to a heat treatment capable of creating a cleavage of the microstructure 3 at the level directly below the strained silicon (sSi) layer 23. The wafer 2 will have been previously implanted with Hydrogen (H) or Helium (He), etc., in order to create this zone of fragility.

[0062] Alternatively, the disassembly of the substrate 21-22 from the microstructure 3 can be carried out mechanically by grinding, or by mechanochemical means, for example by chemical-mechanical polishing or CMP (from the English "Chemical-Mechanical Polishing"). In still other variants, the disassembly can be carried out by a chemical wet etching process.

[0063] In step 109, the deposition of an oxide-based insulating layer 32 (Ox) on the microstructure 3 of [Fig. 4] is then carried out, followed by the deposition of a nitride layer 33 (Nx) in step 110. The microstructure 3 shown in [Fig. 5] is then obtained. The oxide layer 32 may be made of silicon dioxide (SiO2). The nitride layer 33, formed over the layer 32, may be made of silicon nitride (SiN). The layers 32 and 33 may be produced by the same technological processes as those described above with reference to [Fig. 1A] concerning the layers 12 and 13, respectively, of the support wafer 1. These processes are not described again here.

[0064] With reference to [Fig. 6], thereafter, by a photolithography step 111 and a selective etching step 112, wells 34 passing through the oxide layer 32 and the nitride layer 33 all having a bottom at the upper face of the strained silicon (sSi) layer 23 are produced, in order to form shallow isolation trenches by oxidation of the sSi of said layer 23 thus exposed. Here again, the photolithography step 111 and the selective etching step 112 making it possible to obtain this result are similar to the steps 103 and 104 which were previously described, and are therefore not described again in detail here.

[0065] In step 113, and in accordance with the embodiments of the invention, a local oxidation of the strained silicon (sSi) of the layer 23 which is exposed at the bottom of the wells 34 is carried out. This produces additional isolation trenches denoted SSTI, based on silicon dioxide (SiO2) obtained by the local oxidation of the strained silicon (sSi). In the following figures, these trenches 34 made of thin buried oxide are labeled "SSTI". The oxidation can be carried out by implementing the oxidation method known by the English acronym LOCOS. And the structure shown in [Fig.7] is obtained, in which the SSTI join the STI initially formed in the substrate 11 of the original support wafer. The person skilled in the art will appreciate that, due to the implementation of the LOCOS method, the sides of the trenches 34 are not vertical, but are slightly inclined in the vertical direction Z.

[0066] In embodiments, the SSTI additional isolation trenches 34 have a depth equal to or greater than the thickness of the strained silicon film 23, for example between approximately 10 nm and approximately 20 nm, for example of the order of 15 nm.

[0067] Local oxidation of silicon or LOCOS (standing for "LOCal Oxydation of Silicon") is a microfabrication process that forms silicon dioxide SiO2 in defined areas of a silicon wafer, with the Si-SiO2 interface below the surface of the wafer itself. This technology was originally developed (before being supplanted by shallow trench isolation, or STI) to isolate MOS field-effect transistors from each other, thus limiting interference between transistors. The main advantage of this technique comes from the formation, localized around the MOS transistors, of silicon dioxide structures penetrating below the surface of the wafer, which is not easily achieved by etching.In the context of the embodiments of the invention, thermal oxidation of the strained silicon (sSi) regions exposed by the hard mask 33 is similarly used, at a temperature between 800 and 1200°C, using either water vapor ("wet oxidation") or dioxygen ("dry oxidation"). In both cases, and under the effect of heat, the oxygen (O2) penetrates deep into the wafer, reacts with the strained silicon (sSi) that it encounters there at the level of the layer 23 and converts the latter into silica, forming a structure entering the volume of the strained silicon (sSi).

[0068] Advantageously, the implementation of the LOCOS technique under the conditions of the embodiments of the invention makes it possible to form zones 100, 200 and 300 of the strained silicon film 23 (sSi) which are disjointed and isolated from each other, without the sSi being relaxed, i.e. without the strain of the sSi being released because it is never open. The SSTI isolation oxide thus formed joins the deeper STI isolation oxide (i.e. the "Gapfill") forming the shallow STI isolation trenches which had been made in wells 14 formed in the silicon substrate of the original carrier wafer 1 before bonding the donor wafer 2 for the transfer onto the carrier wafer 1 of the strained silicon (sSi) film 23. This advantageous characteristic, taken advantage of in the embodiments of the invention, is documented for example in the scientific article by I. De Wolf, J. Vanhellemont, A. Romano-Rodrîguez, H.Norstrôm, HE Maes; “Micro-Raman study of stress distribution in local isolation structures and correlation with transmission electron microscopy”, Journal of Applied Physics 71 (2), pp. 898-906 (1992); January 15, 1992 (https: / / doi.org / 10.1063 / L351311), to which the skilled person may refer as needed.

[0069] In step 114, the hard mask 33 made of silicon nitride (SiN) and the silicon dioxide (SiO2) residues from the insulating layer 32 can then be removed, to arrive at the microstructure of [Fig. 8]. For example, the removal of the hard mask made of silicon nitride SI3N4 can be carried out by a first chemical etching wet using a phosphoric acid (H3PO4) based solution, for example diluted to 85%, and brought to a temperature of approximately 180°C. Then the removal of the silicon dioxide (SiO2) from the insulating layer 32 can be carried out by a second wet etching, for example based on hydrofluoric acid (HF). Alternatively, the removal of the hard mask 33 and silicon dioxide from the insulating layer 32 can be carried out by a single etching, for example a wet etching based on hydrofluoric acid (HF).

[0070] As the person skilled in the art will have understood, regions 100, 200 and 300 of this microstructure are disjoint regions of strained silicon (sSi) on a thin layer of insulator, namely the insulator (SiO2 in the example) of the underlying buried oxide (BOX) layer 24. By implementing the proposed method, the strain of the sSi of regions 100, 200 and 300 has not been relaxed, although said regions 100, 200 and 300 are isolated from each other laterally and vertically by additional isolation trenches or SSTI formed in the vertical extension of the isolation trenches STI which had been formed deeper in the bulk substrate 11 of the original carrier wafer before the bonding step 107.Microelectronic devices, such as for example MOS transistors or more complex devices in CMOS technology, can then be produced in the active zones corresponding to regions 100, 200 and 300, benefiting from the combined advantages of FD-SOI technology and a strained silicon substrate which were explained in the introduction to this description.

[0071] In other words, the microelectronic structure 3 illustrated in [Fig. 9] which is manufactured by embodiments of the manufacturing method according to the invention, comprises active zones 100, 200 and 300 which are disjointed (i.e. not continuous) on the surface of the same carrier substrate 11 and isolated from each other by shallow isolation trenches 14 (STI) extended vertically by the supplementary isolation trenches 34 (SSTI) via the buried oxide layer 24 (BOX), each active zone having a respective portion of strained silicon (sSi) film 23, and said portions of sSi film resting on the same insulating layer 24 which is itself located above the carrier substrate 11.

[0072] An integrated circuit may comprise the above microelectronic structure, and furthermore at least one MOS type field effect transistor produced in an active area such as areas 100, 200 and 300 of said microstructure, the strained silicon film portion 23 of which serves as a fully depleted silicon on insulator (FD-SOI) substrate in which the channel of the MOS transistor can be produced. This transistor then benefits from the combined advantages of FD-SOI technology and the good electrical conduction properties provided by the strain of the silicon.

[0073] The person skilled in the art will appreciate that the junction between the insulating material, namely silicon dioxide (SiO2) which fills the boxes 34 to form trenches additional insulation trenches (SSTI) as well as the boxes 14 of the shallow isolation trenches (STI), to form the final insulation structures, is carried out by means of the buried oxide (BOX) of the layer 24 of silicon dioxide (SiO2), which is continuous. This is why we speak of complex insulation structures STI-BOX-SSTI.

[0074] At least some of the SSTI supplementary insulation trenches 34 have the same horizontal dimensions as associated shallow STI insulation trenches 14, and are respectively horizontally aligned with said associated trenches 14. In other words, each of these trenches 34 is exactly superimposed with a trench 14 in the vertical direction Z, without the vertical projection of one of them projecting relative to the other in the longitudinal direction X or in the transverse direction Y. These trenches 34 and 14 are then said to be vertically aligned. An example of such aligned trenches is shown at the bottom right of the diagram of an example of structure 3' shown in [Fig.l 1] (see below).

[0075] According to another advantage of the implementations of the method, it is possible to obtain by a single process relatively deep isolations, namely here for example the STI between the active zones 100 and 200 whose thickness can preferably be between approximately 70 nm and approximately 300 nm, and at the same time relatively shallow isolations such as here the SSTI between the active zones 200 and 300 for example, whose thickness is between approximately 10 nm and approximately 20 nm. It is recalled that these depths are considered along the vertical direction Y. MOS transistors on FD-SOI substrate can be formed at the zones 200 and 300, respectively, in respective wells of the silicon substrate 11 which have identical dopings (type of doping, and level of doping).On the other hand, another MOS transistor on FD-SOI substrate can be made at the level of the zone 100 in a well in the silicon substrate 11 which can have a different doping, thanks to the presence of the relatively deep insulation STI which separates it from the well in the silicon substrate 11 which corresponds to the zone 200 to the zone 300.

[0076] According to another advantage, in addition, a device produced on the wafer 2 on a silicon-on-insulator (SOI) substrate can be placed above an STI, so that it will then be extremely far from any silicon on the support wafer 1. As a result, in operation, it will be extremely far from a polarizing electric field, which makes it a unique structure.

[0077] Finally, nothing prevents the formation, by etching, of third isolation trenches distinct from the second additional isolation trenches 34 SSTI. These third trenches can be made through a second mask, previously made by photolithography in the layer of hard material 33 of [Fig. 5] which in the example is a nitride, and which is deposited over the layer of associated insulating material 32, which is itself deposited on the strained silicon layer 23 after disassembly of the donor substrate 22. Residues of this second mask and of said associated insulating material layer are removed after the formation of said third trenches. The formation of trenches by etching using a mask certainly results in the loss of stress in the sSI film, but this loss may be acceptable in certain applications in which third isolation trenches can thus be produced in addition to the second additional isolation trenches 34 SSTI already formed by oxidation, which make it possible to maintain the stress in the sSI film 23.

[0078] Finally, with reference to another example of microelectronic structure 3' shown in [Fig. 11] (which would be obtained by the same process steps as structure 3 of [Fig. 9]) and as shown by block 115 in the step diagram of [Fig. 10], at least one opening may be made through the thickness of one or more additional trench(es) 34 (SSTI) and through the buried oxide layer 24 (BOX) to expose the underlying bulk silicon substrate 11, as in region 400 and in region 700 in the example shown. In [Fig. 11], the additional isolation trench 34 which is thus crossed is shown surrounded by a broken line frame.For example, the openings 400 and 700 may be made by etching, through a hard mask obtained by photolithography, the insulating material (SSTI) of the layer 34 and the insulating material (BOX) of the layer 24 in order to expose the underlying support substrate 11, in respective areas of said support substrate 11 in which there are no shallow isolation (STI) trenches 14. Since the etching mask is made after the STI and SSTI trenches, the alignment patterns of any of these trenches may be aligned.

[0079] It will be noted that the opening 400 divides the relevant additional SSTI isolation trench 34 into two such derived SSTI trenches, of smaller horizontal dimensions, and which are horizontally adjacent. In the example shown in [Fig.l 1], the derived SSTI trench which is on the right is vertically aligned with a shallow STI isolation trench 14 associated with it, with which it is in material continuity via a portion of the buried oxide layer 24 BOX associated with them. This mutual alignment results from the alignment of the masks used to form these three respective elements, and gives a complex isolation structure (STLBOX-SSTI) in the form of a unitary SiO2 isolation trench.

[0080] Once the openings 400 and 700 have been formed in the SSTI, the silicon (Si) of the support substrate 11 can be grown upwards, by epitaxial growth, in said openings 400 and 700, at least up to and including the level of the layer 24 of insulating material (BOX). Accesses to the silicon (Si) of the substrate have thus been made. carrier 11 without relaxing the stress of the strained silicon (sSi) film 23 of the active areas 500 and 600 shown in [Fig.l 1].

[0081] More generally, if new trenches have to be made on the surface of the microelectronic structure 3' to access the silicon of the carrier substrate 11, and knowing that this cannot be done by direct etching of the strained silicon (sSi) layer 23 without this resulting in the loss of the strain of said sSi film, then this can be done in an additional SSTI isolation trench 34 made as described above. Such etching in an SSTI trench does not, in fact, have the consequence of relaxing the sSi of the film 23, i.e., of affecting the strain of the sSI film 23.

[0082] This gives the possibility, if necessary, of producing at these regions 400 and 700 microelectronic devices of the NOSO (from the English “Not-On-SOI”) type, in and / or on the support substrate 11 which is a bulk substrate based on doped silicon. It is thus possible to produce active components, for example in conventional CMOS technology on a bulk substrate, in active zones under the surface of the bulk substrate 11 shown, at the region 400 or the region 700, in addition to components, such as the transistor 601 shown which can be produced in the active zones 500 and 600 in FD-SOI technology on a strained silicon film.

[0083] Another possibility offered by the zones 400 and 700 for accessing the silicon of the substrate 11 is, for example, to be able to polarize (via metallizations not shown) a well in the substrate 11 forming an active zone in which the source and the drain of the transistor 601 are produced. In [Fig. 11], this polarization via the zone 400 is symbolized by the arrow 401. Also, the deep well between the shallow isolation trenches 14 (STI) can be polarized, via the zone 700 of [Fig. 11] which is located on the other side of one of these trenches with respect to the well in question. In [Fig. 11], this polarization via the zone 700 is symbolized by the arrow 701.

[0084] Particular embodiments have just been described. Different variants and modifications will appear to those skilled in the art. For example, the solid substrate 11 of the support wafer 1 does not necessarily need to be doped. It may be an undoped silicon substrate if there is no need to produce components in this substrate, unlike the possibility explained above with reference to regions 400 and 700.

Claims

Claims

1. A method of manufacturing a microelectronic device, said method comprising: • the provision of a first plate (1) comprising a support substrate (11); • the formation, on the support substrate (11) of the first plate (1), of first insulation trenches (14); • providing a second plate (2) comprising a donor substrate (21-22); • the formation, on the donor substrate (21-22) of the second plate (2), of a strained silicon film (23); • bonding the second plate (2) to the first plate (1), so that the strained silicon film (23) is found on the first plate (1) via at least one layer of insulating material (24) formed, before bonding, on the first plate (1) after the formation of the first trenches and / or on the second plate (2) after the formation of the strained silicon film (23); • dismantling the donor substrate (21-22) while retaining the layer of insulating material (24) and the strained silicon film (23) on the first plate (1); and, • the formation of second isolation trenches (34) around and / or along portions of the strained silicon film (23).

2. A method according to claim 1, wherein: • the first isolation trenches (14) formed in the support substrate (11) of the first wafer (1) are so-called “shallow trenches”, or STI, the depth of which is greater than approximately 5 nm, or between approximately 5 nm and approximately 300 nm, preferably between approximately 50 nm and approximately 300 nm, and even more preferably between approximately 70 nm and approximately 300 nm; and / or • the second isolation trenches (34) have a depth equal to or greater than the thickness of the constrained silicon film (23), for example between approximately 10 nm and approximately 20 nm, for example of the order of 15 nm.

3. A method according to claim 1 or claim 2, wherein the insulating material of the first trenches (14), the insulating material of the second trenches (34) and / or the insulating material of the insulating material layer (24), is silicon dioxide, SiO2.

4. A method according to any one of claims 1 to 3, wherein the formation of the first trenches (14) in the donor substrate (11) is carried out by etching through a first mask previously produced by photolithography in a layer of hard material (13) such as for example a nitride, which covers the support substrate provided by means of an associated layer of insulating material (12), residues of said first mask (13) and of said associated layer of insulating material (12) being removed from the support substrate (11) after the formation of said first trenches (14).

5. Method according to any one of claims 1 to 4, in which it comprises the formation of third isolation trenches made through a second mask previously made by photolithography in a layer of hard material (33) such as for example a nitride, which is deposited over an associated layer of insulating material (32) itself deposited on the strained silicon layer (23) after disassembly of the donor substrate, residues of said second mask (13) and of said associated layer of insulating material (12) being removed after the formation of said third trenches.

6. A method according to any one of claims 1 to 5, wherein the second isolation trenches (34) join the first trenches (14) via the layer of insulating material (24) to form an isolation structure around and along the strained silicon film.

7. A method according to any one of claims 1 to 6, wherein the second trenches (34) are made by local oxidation of the silicon of the strained silicon film (23), for example the local oxidation of the silicon of the strained silicon film (23) is a thermal oxidation, for example a LOCOS type oxidation.

8. A method according to any one of claims 1 to 7, wherein the disassembly of the donor substrate (21-22) is carried out by grinding, by selective removals or by implantation fracture, for example by implementing the Smart-cut® process.

9. A method according to any one of claims 1 to 8, wherein the donor substrate (21-23) of the second wafer (2) comprises a silicon-germanium, Si-Ge, layer adapted to strain the silicon of the strained silicon film (23).

10. A method (1) according to any one of claims 1 to 9, wherein at least one opening (400) is made through the thickness of one of the second trenches (34) and through the layer of insulating material (24) to expose the underlying support substrate (11), in an area of ​​said support substrate (11) in which there are no first trenches (14), and wherein, in addition, the silicon (Si) of the support substrate (11) is grown upwards by epitaxial growth in the opening (400), at least up to and including the level of the layer of insulating material (24).

11. A method according to any one of claims 1 to 10, wherein at least some of the second isolation trenches (34) have the same horizontal dimensions as associated first trenches (14), and are respectively vertically aligned with said associated first trenches (14).

12. Microelectronic structure obtained by implementing the manufacturing method according to any one of claims 1 to 11, said structure comprising active zones (100,200,300) disjointed on the surface of the same carrier substrate (11) and isolated from each other by deep and less deep isolation trenches (14-24-34), each active zone having a respective portion of strained silicon film (23), and said portions of strained silicon film resting on the same insulating layer (24) which is itself located above the carrier substrate (11).

13. A microelectronic structure according to claim 12, wherein the insulating material of the first trenches (14), the insulating material of the second trenches (34) and / or the insulating material of the insulating material layer (24), is silicon dioxide, SiO2.

14. A microelectronic structure according to claim 12 or claim 13, wherein the second trenches (34) have non-vertical sides.

15. Integrated circuit comprising the microelectronic structure according to one of claims 12 to 14, and further comprising at least a MOS type field effect transistor produced in an active zone (100,200,300) of said microstructure, the strained silicon film portion (23) of which serves as a fully depleted silicon on insulator (FD-SOI) substrate in which the channel of the MOS transistor is produced.

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