QUANTUM DEVICE WITH STACKED QUBITS AND NO DIAGONAL COUPLING

Abstract

A quantum electronic device comprising: - a first set of semiconductor regions (102L, 104L), - a second set of semiconductor regions (102R, 104R), the first set of semiconductor regions (102L, 104L) being arranged opposite the second set of semiconductor regions (102R, 104R), at least one dielectric region (RD) separating the first set of semiconductor regions (102R, 104R) from the second set of semiconductor regions (102R, 104R), said dielectric region (RD) being provided with a heterogeneous composition so as to prevent electrostatic coupling between a lower first semiconductor region (102L) and an upper second semiconductor region (104R), and so as to prevent electrostatic coupling between an upper first semiconductor region (104L) and a second region lower semiconductor (102R). Figure for the abstract: 24

Description

Title of the invention: Quantum device with stacked qubits and NO DIAGONAL COUPLING

[0001] TECHNICAL FIELD AND STATE OF THE PRIOR ART

[0002] The present application relates to the field of quantum devices in in which at least one quantum information based on a given quantum state among at least two measurable levels is used. This quantum state is called a qubit or quantum bit or even "quantum bit" in English.

[0003] A special type of qubit is the spin qubit when the intrinsic degree of freedom of the spin of individual electrons is used to encode quantum information.

[0004] Qubits can be formed in a semiconductor material within confinement structures of nanometric size and defined electrostatically and / or physically. These confinement structures are typically called “quantum dots”.

[0005] A quantum dot behaves like a potential well confining one or more elementary charges (electrons or holes) in a semiconductor region.

[0006] To measure the state of a qubit, it is known to carry out a spin / charge conversion which makes it possible to convert the spin state of the charged particles into a charge state of the quantum dots containing said particles. It is then necessary to measure this charge state in order to deduce the spin state of the charged particles before conversion. For this, a means for measuring the charge state is generally arranged opposite or close to each quantum dot.

[0007] Reading a qubit can in particular be carried out using another quantum box called a “reading island” or “detection island” coupled to that of the qubit intended to be read. These two elements form two potential wells separated by a potential barrier.

[0008] Devices in which the detection islands and quantum dots are arranged opposite and in the same plane parallel to the main plane of a substrate on which the quantum dots and the detection islands are formed are known.

[0009] The document by R Pillarisetty “High Volume Electrical Characterization of Semiconductor Qubits”, 2019 IEEE International Electron Devices Meeting (IEDM) proposes for example a device with quantum dots formed in a first semiconductor block of elongated shape (“thin” according to Anglo-Saxon terminology) and detection islands formed in a second semiconductor block of elongated shape and parallel to the first block.

[0010] The problem arises of producing a new quantum device which is preferably improved in terms of integration density while retaining good detection sensitivity. Statement of the invention

[0011] According to one aspect, the present invention relates to a quantum electronic device provided with a substrate, this substrate being coated:

[0012] - of a first set of semiconductor regions comprising at least a first lower semiconductor region and at least one first upper semiconductor region, superimposed on, and separated from, the first lower semiconductor region by means of a first so-called “separation” zone,

[0013] - of a second set of semiconductor regions comprising at least a second lower semiconductor region and at least one second upper semiconductor region, superimposed on, and separated from, the first lower semiconductor region by means of a second so-called “separation” zone

[0014] the first set of semiconductor regions being arranged opposite the second set of semiconductor regions so that the first lower semiconductor region is arranged opposite the second lower semiconductor region and so that the first upper semiconductor region is arranged opposite the second upper semiconductor region,

[0015] - at least one dielectric region separating the first set of semi- conductive of the second set of semiconductor regions, said dielectric region (RD) having a heterogeneous composition.

[0016] The dielectric region may be configured to allow electrostatic coupling between the first lower semiconductor region and the second lower semiconductor region and to allow electrostatic coupling between the first upper semiconductor region and the second upper semiconductor region.

[0017] The dielectric region, due to its heterogeneous composition, may also be provided so as to prevent electrostatic coupling between the first lower semiconductor region and the second upper semiconductor region and so as to prevent electrostatic coupling between the first upper semiconductor region and the second lower semiconductor region.

[0018] Thus, a device is implemented with quantum dots which can be arranged in different planes and here a coupling is allowed between these quantum dots and semiconductor regions or detection islands arranged opposite or opposite while preventing a coupling with regions of different levels.

[0019] Advantageously, the dielectric region between the first set of semiconductor regions and the second set of semiconductor regions is provided with a heterogeneous dielectric composition such that in a central portion located between the first lower semiconductor region and the second upper semiconductor region and between the first upper semiconductor region and the second lower semiconductor region, the dielectric region is formed of an empty space or has a given dielectric material composition and a given dielectric constant k2, and that in another portion located between the first lower semiconductor region and the second lower semiconductor region or between the first upper semiconductor region and the second upper semiconductor region,the dielectric region has a second composition and a higher relative dielectric constant than the given dielectric constant k2. ,

[0020] According to one embodiment, the dielectric region between the first set of semiconductor regions and the second set of semiconductor regions can be formed:

[0021] - of a lower dielectric portion arranged between the first semi- lower conductive and the second lower semiconducting region,

[0022] - of an upper dielectric portion located between the first semi- upper conductive region and the second upper semiconductive region,

[0023] - of a central dielectric portion, arranged between the lower dielectric portion and the upper dielectric portion, the lower dielectric portion, the central dielectric portion and the upper dielectric portion being superimposed,

[0024] the central dielectric portion being made of a given dielectric material having a first dielectric constant k2, the lower dielectric portion and the upper dielectric portion being based on one or more dielectric materials different from said given dielectric material and with respective dielectric constant(s) greater than k2.

[0025] According to another possible implementation, the dielectric region with heterogeneous composition between the first set of semiconductor regions and the second set of semiconductor regions is formed:

[0026] - of at least one dielectric material having a dielectric constant kl coating each of the first and second lower and upper semiconductor regions, so as to form lower insulating shells against the first and second lower semiconductor regions and upper insulating shells against the first and second upper semiconductor regions, and

[0027] - at least one insulating space between an upper insulating bump located on the first or second upper semiconductor region a lower insulating bump located on the first or second lower semiconductor region, the insulating space being:

[0028] - filled with a given dielectric material having a dielectric constant k2, such that k2 < kl, or

[0029] - being an empty space.

[0030] According to a particular embodiment, the separation zones may be provided so as to allow electrostatic coupling between the first lower semiconductor region and the first upper semiconductor region, and so as to allow electrostatic coupling between the second lower semiconductor region and the second upper semiconductor region.

[0031] According to one possible implementation of the device, the first lower semiconductor region and the first upper semiconductor region are regions respectively of a lower semiconductor bar and an upper semiconductor bar, the lower semiconductor bar and the upper semiconductor bar extending parallel to a first direction parallel to a main plane of the substrate. Thus, several quantum dots can be distributed along the same first semiconductor bar and several detection islands can be distributed along a second semiconductor bar located opposite the first semiconductor bar.

[0032] Advantageously, the quantum electronic device may further comprise: a plurality of control gates for the lower semiconductor bar and the upper semiconductor bar, the control gates extending in a second direction forming a non-zero angle with the first direction and advantageously orthogonal to the first direction.

[0033] According to one embodiment, the quantum electronic device may further comprise:

[0034] - a first group of superimposed grids comprising at least one first grid lower and a first upper grid superimposed on, and separated from the first lower grid by a first insulation zone, the first lower grid and the first upper grid being arranged against, and facing, respectively the first lower semiconductor region and the first upper semiconductor region so as to respectively exercise electrostatic control of the first lower semiconductor region and the first upper semiconductor region,

[0035] - a second group of superimposed grids comprising at least a second lower grid separated from a second upper grid superimposed on, and separated from the second lower grid by a second insulation zone, the second lower grid and the second upper grid being arranged against, and facing, respectively of the second lower semiconductor region and the second upper semiconductor region so as to respectively exercise electrostatic control of the second lower semiconductor region and the second upper semiconductor region, the first group of superimposed grids and the second group of superimposed grids being arranged on either side of the first set of semiconductor regions and the second set of semiconductor regions.

[0036] According to another aspect, the present invention relates to a method for producing a quantum electronic device and in particular a quantum device as defined above.

[0037] One embodiment provides a method of manufacturing a quantum device as defined above and wherein forming the first set of semiconductor regions and the second set of semiconductor regions comprises steps of:

[0038] - production on the substrate of a structure formed from a superposition of layers composed of an alternation of layers based on a first given material, and layers based on a second material, the second material being semiconducting, the first given material being capable of being selectively etched with respect to the second given material,

[0039] - construction of a separation trench extending mainly in a direction parallel to the first direction by etching said superposition of layers so as to divide said structure into a first portion and a second portion, the first portion and the second portion extending parallel to the first direction, the semiconductor regions of the first set being semiconductor regions of the first portion and formed based on the second given material, the semiconductor regions of the second set being semiconductor regions of the second portion and formed based on the second given material, and in which the heterogeneous dielectric region is then formed in the separation trench between the first portion and the second portion of the structure.

[0040] The formation of the dielectric region may comprise steps of:

[0041] - depositing in the separation trench a first dielectric material to form a lower dielectric portion arranged between the first lower semiconductor region and the second lower semiconductor region,

[0042] - depositing in the separation trench a second layer based on a material given dielectric different from the first dielectric material and of given dielectric constant k2 lower than that of the first dielectric material to form a central dielectric portion,

[0043] - deposition in the separation trench of the first dielectric or a third dielectric material of dielectric constant greater than that of the given dielectric material to form an upper dielectric portion arranged between the first upper semiconductor region and the second upper semiconductor region.

[0044] According to one possible implementation, after deposition of the first dielectric material and prior to the deposition of the given dielectric material: a partial removal of the first dielectric material is carried out in the trench, and in which after deposition of the given dielectric material and prior to the formation of the upper dielectric portion, a partial removal of the given dielectric material is carried out.

[0045] According to one possible implementation, the formation of the heterogeneous dielectric region may comprise steps of:

[0046] - epitaxial growth on the first lower semiconductor region, on the first upper semiconductor region, on the second lower semiconductor region and on the second upper semiconductor region, of a sacrificial semiconductor material and so as to preserve an empty space between the first portion and the second portion of the structure,

[0047] - filling the empty space by means of a given dielectric material of given dielectric constant k2,

[0048] - removal of the sacrificial semiconductor material selective with respect to that of the first lower semiconductor region, the first upper semiconductor region, the second lower semiconductor region and the second upper semiconductor region, in order to release volumes around respectively the first lower semiconductor region, the first upper semiconductor region, the second lower semiconductor region and the second upper semiconductor region,

[0049] - fill the volumes using a dielectric material different from the material given dielectric and having a dielectric constant kl greater than k2.

[0050] According to another possible implementation, the method of forming the dielectric region may comprise steps of:

[0051] - epitaxial growth on the first lower semiconductor region, the first upper semiconductor region, the second lower semiconductor region and the second upper semiconductor region, of a sacrificial semiconductor material and so as to preserve an empty space between the first portion and the second portion of the structure,

[0052] - filling said empty space with a given dielectric material,

[0053] - removal of the sacrificial semiconductor material selective with respect to that of the first lower semiconductor region, of the first semiconductor region upper, the second lower semiconductor region and the second upper semiconductor region, in order to release volumes around respectively the first lower semiconductor region, the first upper semiconductor region, the second lower semiconductor region and the second upper semiconductor region,

[0054] - fill the volumes using another dielectric material different from the given dielectric material and capable of being selectively etched with respect to said given dielectric material,

[0055] - removal of said given dielectric material selectively with respect to said other dielectric material. Brief description of the drawings

[0056] The present invention will be better understood upon reading the description of exemplary embodiments given, for purely indicative and non-limiting purposes, with reference to the appended drawings in which:

[0057] [Fig-1] illustrates an example of a quantum device with semiconductor regions superimposed and facing each other.

[0058] [Fig.2A] illustrates an exemplary embodiment in which the quantum device is provided with several pairs of superimposed gates and in which the semiconductor regions are distributed along superimposed semiconductor bars.

[0059] [Fig.2B] is used to illustrate a superposition of semiconductor rods in the quantum device.

[0060] [Fig.3]

[0061] [Fig.4] illustrate an exemplary embodiment of the quantum device in which a insulating space is provided between neighboring grid groups and distributed along superimposed semiconductor bars.

[0062] [Fig.5]

[0063] [Fig.6A]

[0064] [Fig.6B] illustrate an exemplary embodiment of an active zone semiconductor structure for a quantum device with two sets of superimposed semiconductor regions.

[0065] [Fig.7]

[0066] [Fig.8]

[0067] [Fig.9] illustrate an example of the production of grid patterns.

[0068] [Fig. 10]

[0069] [Fig. 11]

[0070] [Fig. 12]

[0071] [Fig. 13] illustrate an example of the production of dopant reservoirs.

[0072]

[0073]

[0074]

[0075]

[0076]

[0077]

[0078] [Fig. 14] [Fig.15] [Fig.16] [Fig.17] [Fig.18] [Fig.l9A] [Fig.l9B] illustrate an example of producing superimposed grids from the grid patterns.

[0079]

[0080] [Fig.20A] [Fig.20B] illustrate an example of producing a separation trench for separating an active zone semiconductor structure into distinct portions arranged face to face with each other and comprising superimposed semiconductor regions.

[0081]

[0082] [Fig.21] [Fig.22] illustrate an example of producing dielectric separation zones interposed between superimposed semiconductor regions.

[0083]

[0084] [Fig.23A] [Fig.23B] illustrate an example of embodiment of an intermediate dielectric region between a first portion and a second portion of active zone structure.

[0085] [Fig.24] illustrates a particular embodiment of the quantum device and as implemented according to the invention, the device being here provided with an intermediate dielectric region having a heterogeneous composition in order to allow electrostatic coupling between semiconductor regions located at the same level and facing each other while preventing electrostatic coupling between on the one hand semiconductor regions of the first portion and on the other hand semiconductor regions of the second portion located in different levels.

[0086]

[0087]

[0088]

[0089]

[0090] [Fig.25] [Fig.26] [Fig.27] [Fig.28] [Fig.29] illustrate a first example of a method for manufacturing a quantum device according to the invention.

[0091] [Fig.30] illustrates another particular embodiment of a quantum device according to the invention.

[0092]

[0093]

[0094]

[0095] [Fig.31] [Fig.32] [Fig.33] [Fig.34] .

[0096] [Fig.35] illustrate a second example of a method for producing a quantum device according to the invention.

[0097] [Fig.36]

[0098] [Fig.37]

[0099] [Fig.38]

[0100] [Fig.39]

[0101] [Fig.40] illustrate a third example of a manufacturing process of the second mode of particular realization of the quantum device.

[0102] [Fig.41]

[0103] [Fig.42] illustrate an example of the production of exchange grids.

[0104] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0105] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0106] Furthermore, in the following description, terms that depend on the orientation of the structure such as "above", "below", "lower", "upper", "juxtaposed", "superimposed" apply considering that the structure is oriented in the manner illustrated in the figures.

[0107] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0108] We first refer to [Fig.l] which gives an example of the production of a quantum device.

[0109] The device is arranged on a substrate 5 which may for example be of the semiconductor on insulator type, in particular of the SOI type (SOI for “Silicon On insulator” or silicon on insulator) or of the bulk type, for example made of silicon.

[0110] The device is provided here with quantum dots BQ1, BQ2 formed in a first set of superimposed semiconductor regions 102L, 104L, for example made of silicon or germanium. A quantum dot BQ1 is thus produced in a first semiconductor region 102L called “lower” while another quantum dot BQ2 arranged above the first lower semiconductor region is formed in a first semiconductor region called “upper” 104L.

[0111] The quantum boxes BQ1, BQ2 each ensure the confinement of at least one elementary charge (electron(s) or hole(s)). Preferably, each quantum box BQ1, BQ2 here comprises a single elementary charge. The spin of this charge, in particular an electron, can be provided to encode the quantum information. In this case, the qubits associated with the quantum boxes BQ1, BQ2 are spin qubits.

[0112] To enable the detection of a quantum state also called “charge state” of the quantum boxes BQ1, BQ2, a charge detection structure is provided in the vicinity and in this example opposite the quantum boxes BQ1, BQ2.

[0113] This detection structure comprises detection islands ID1, ID2 formed in a second set of superimposed semiconductor regions 102R, 104R, typically based on the same semiconductor material as the regions 102L, 104L. A detection island ID1 is thus produced in a second lower semiconductor region 102R which faces the first lower semiconductor region 102L while another detection island ID2 is formed in a second upper semiconductor region 104R arranged above the second lower semiconductor region 102R and faces the first upper semiconductor region 104L.

[0114] The first semiconductor regions 102L, 104L are thus provided here to each form a qubit, while the second semiconductor regions 102R, 104R are here dedicated to reading the qubits.

[0115] In the particular embodiment illustrated, the lower semiconductor regions 102L, 102R are arranged in the same first plane PI, while the upper semiconductor regions 104L, 104R are arranged in the same second plane P2, the first and second planes PI and P2 being parallel to a main plane of the substrate 5 (i.e. a plane defined throughout the description as a plane passing through the substrate 5 and which is parallel to the plane [0; x; y] of the orthogonal reference frame [0; x; y; z]).

[0116] The device is also provided with at least one dielectric region RD based on at least one dielectric material located between, on the one hand, the superposition of quantum dots BQ1, BQ2 and, on the other hand, the superposition of islands ID1, ID2.

[0117] In this embodiment, the operation of the device is based on a capacitive coupling also called "electrostatic coupling" between each quantum box BQ1, BQ2 and a detection island ID1, ID2 arranged opposite the quantum box BQ1, BQ2. In this case, the dielectric material(s) of the dielectric region RD are chosen in particular in terms of relative permittivity or dielectric constant and the dimensions D1, D2 (corresponding respectively to the distance between upper semiconductor regions and to the distance between lower semiconductor regions) of this dielectric region RD to enable such electrostatic coupling to be obtained. Such coupling can result in a measurable useful signal greater than a parasitic signal and which can be of the order of several fF (femto Farad).

[0118] For example, to enable electrostatic coupling to be obtained between a quantum dot and an island opposite this dot, the dielectric region RD can be formed based on SiO2, SiN, Al2O3, HfO2, and dimensions Dl, D2 of, for example, between 10 nm and 60 nm, advantageously between 20 nm and 40 nm.

[0119] To enable electrostatic control of the quantum dots and detection islands to be carried out, grids are provided formed from a conductive or semiconductive block of grid material 22, for example polysilicon, against a grid dielectric layer 21 arranged between the grid block and the semiconducting regions. The arrangement proposed in [Fig.l] here has the particularity of providing the same grid dielectric layer 21 common to the two superimposed grids GI1, GSI and semiconducting regions 102L, 104L.

[0120] The quantum dots BQ1, BQ2 are controlled by a first group of superimposed grids GI1, GSI, each grid GI1, GSI being here arranged against a quantum dot BQ1, BQ2. A first so-called "lower" grid GI1 for the electrostatic control of the first lower semiconductor region 102L is located in the first plane PI, while a first so-called "upper" grid GSI for the electrostatic control of the first upper semiconductor region 104L is located in the second plane P2.

[0121] The first upper gate GSI is superimposed on, and separated from, the first lower gate GI1 by means of a first insulation zone ZIL. This first insulation zone ZI1 of the lower gates GI1 and upper gates GSI from each other is typically made of insulating material and preferably of thickness e0 sufficient to electrically insulate the gates GI1, GSI from each other. For example, the first insulation zone ZI1 is formed from SiO2 and has a thickness e0 which may be for example between 5 nm and 20 nm.

[0122] To enable electrostatic control of the semiconductor regions 102R, 104R, a second group of superimposed gates GI2, GS2 is provided, each gate GI2, GS2 being juxtaposed against a semiconductor region 124a, 124b. A second lower gate GI2 is located in the first plane PI, while a second upper gate GS2 is located in the second plane P2 and isolated from the lower gate GS2 by means of an isolation zone ZI2. This second isolation zone ZI2 of the lower gates GI2 and upper gates GS2 is advantageously provided with a thickness and a material similar to that of the first isolation zone ZIL.

[0123] In this embodiment, there is thus advantageously an alignment of the lower gates GSI, GR1 and the lower semiconductor regions 102L, 102R in the same plane PI and an alignment of the upper gates GS2, GR2 and the upper semiconductor regions 104L, 104R in the same upper plane P2 distinct from the plane PL.

[0124] According to a possible implementation of the device, it can be provided that each qubit stage is independent of the other stages and thus provide for preventing electrostatic coupling between the first lower semiconductor region 102L and the first upper semiconductor region 104L. An electrostatic coupling between the second lower semiconductor region 102R and the second upper semiconductor region 104R is then also typically prevented. In this case, only horizontal interactions (in other words in directions parallel to the main plane of the substrate) are favored between quantum dots BQ1, BQ2 and detection islands ID1, ID2.

[0125] To enable the lower stage to be isolated from the upper stage, so-called "separation" zones ZS1, ZS2 arranged respectively between the first lower and upper semiconductor regions 102L and 104L and between the second lower and upper semiconductor regions 102R and 104R are provided, here preferably made of dielectric material, for example SiO2 and with a sufficient thickness (also called height) H1, H2, for example at least 30 nm, and typically between 30 nm and 100 nm.

[0126] It is possible to integrate several other quantum boxes in the lower stage Ni in which the quantum box BQ1 is located and several other quantum boxes in the upper stage N2 in which the quantum box BQ2 is located. In this case, the first lower semiconductor region 102L may be a region of a semiconductor block typically in the form of a bar (seen in section in [Fig.l]), for example of parallelepipedal or substantially parallelepipedal shape and called the first lower semiconductor bar, in which other semiconductor regions forming other quantum boxes each controlled by a gate are arranged.

[0127] Similarly, the first upper semiconductor region 104L may be formed in another semiconductor rod called the first upper semiconductor rod in which other semiconductor regions forming other quantum dots each controlled by a gate are arranged. The second lower semiconductor region 102R may be a region of a second lower semiconductor rod located in the same first PI plane as the first lower semiconductor rod and in which other semiconductor regions forming other detection islands each controlled by a gate are arranged. Similarly, the second upper semiconductor region 104R may be formed in a second upper semiconductor rod in which other semiconductor regions forming other detection islands each controlled by a gate are arranged. A partial perspective view given in [Fig.2B] serves to illustrate a superposition of bars 104', 104” in which the second region is respectively formed. upper semiconductor region 104R and the second lower semiconductor region 102R. The bars can be made here from a superposition of distinct layers of the substrate.

[0128] The first and second lower and upper semiconductor bars all extend in a first direction (direction orthogonal to the plane of [Fig.l] and parallel to the y axis of the orthogonal reference frame [0;x;y;°z]).

[0129] As can be seen in the embodiment illustrated in [Fig.2A] (where the dielectric region RD is not shown for greater readability and where only the second upper bar 104” is visible) other groups of superimposed grids can be provided to control a lower and upper row of quantum dots as well as a lower and upper row of detection islands. The different groups of grids are distributed in the first direction along the bars and the grids typically extend in a second direction orthogonal to the first direction (and parallel to the x axis of the orthogonal reference frame [0;x;y;°z]).

[0130] Gates GI3, GS3, of a third group of superimposed gates, juxtaposed with the first group of superimposed gates GI1, GSI ([Fig.2A]) are thus dedicated to the electrostatic control respectively, of a third lower semiconductor region of the first lower semiconductor bar and, of a third upper semiconductor region of the first upper semiconductor bar. A fourth group of superimposed gates GI4, GS4 juxtaposed with the second group of superimposed gates GI2, GS2 is also provided here, to control respectively a fourth lower semiconductor region of the second lower semiconductor bar and a fourth upper semiconductor region of the second upper semiconductor bar.

[0131] Advantageously, the device may also be provided with DTI and DT2 dopant reservoirs at the ends of the lower and upper rows of quantum dots and detection islands. These dopant reservoirs may be in the form of blocks, typically made of doped semiconductor material, for example phosphorus-doped silicon or boron-doped silicon germanium. In the particular embodiment illustrated, each block forming a DTI, DT2 dopant reservoir is connected to one end of the set of semiconductor rods.

[0132] Advantageously, exchange electrodes GE11, GE12, GE22 also called “exchange grids” can be provided in inter-grid spaces. In the particular embodiment of [Fig.2A], rather than a single exchange electrode in the same inter-grid space, a pair of exchange electrodes GE11, GE12 superimposed in the same inter-grid space is advantageously provided.

[0133] The exchange electrodes GE11, GE12 extend mainly in a direction parallel to that in which the grids GI1, GSI, GI3, GS3 extend and which is preference orthogonal to the first direction (the first direction being parallel to the y axis) in other words to the direction in which the semiconductor bars hosting the detection islands and the quantum dots extend. Each exchange electrode is typically separated from the adjacent grids by means of an insulating spacer layer 33.

[0134] The arrangement of the exchange electrodes GE11, GE12 may be similar to that of the gates GS3, GI3 or GSI, GI1, such that an upper exchange electrode GE12 is arranged above a lower exchange electrode GE11 and isolated from this lower exchange electrode GE11 by the insulating layer an insulating separation layer CSL The exchange electrodes make it possible to carry out charge exchanges between neighboring quantum dots or between neighboring detection islands distributed along the same semiconductor bar. Thus the exchange electrode GE11 allows an exchange of charges between a first lower semiconductor region controlled by the gate GI1 and a lower semiconductor region controlled by the gate GI3 and located on the same semiconductor bar as the first lower semiconductor region.

[0135] The implementation of exchange electrodes is optional, in particular when the pitch A of the grid distribution ("pitch according to the English terminology") is low and for example less than 40 nm. In this case, it is certain of the grids which can be used to control the exchange between adjacent quantum dots or detection islands of the same semiconductor portion.

[0136] Thus, in an alternative embodiment illustrated in Figures 3 and 4, the inter-grid spaces are devoid of exchange electrodes.

[0137] In [Fig.4] giving a cross-sectional view of the grids GI1, GSI, GI3, GS3 (in other words according to a cutting plane orthogonal to the direction in which the grids extend) the inter-grid spaces are filled with insulating material 53.

[0138] In either of the exemplary embodiments which have just been given, the device comprises two levels or stages NI, N2 of quantum dots and detection islands. However, the quantum device is not limited to this number and can integrate a higher number k (with k>2) of stages. Thus, more generally, a quantum device as implemented according to the invention can comprise a number of stages of superimposed semiconductor regions greater than two.

[0139] As a variant of one or other of the embodiments described previously and in which horizontal interactions are implemented between quantum box BQ1, (respectively BQ2) and detection island ID1, (respectively ID2), it is possible to provide a device with both horizontal and vertical interactions between different levels of semiconductor regions. In this case, it is possible to provide in particular the separation zones ZS1, ZS2 illustrated in [Fig.l] with heights Hl, H2 provided sufficiently low and based on a dielectric material of sufficiently high dielectric constant to allow electrostatic coupling between the first lower semiconductor region 102L and the first upper semiconductor region 104L as well as between the second upper semiconductor region 102R and the second upper semiconductor region 104R. For example, to allow electrostatic coupling to be obtained between an upper semiconductor region 104L, 104R and a lower semiconductor region 102L, 102R, below, the separation zones ZS1, ZS2 can be formed based on high-k material (in other words with a high dielectric constant k), for example HfO2, with a height Hl, H2 of for example between 10 nm and 30 nm, advantageously between 10 nm and 20 nm.

[0140] The capacitance, which is a measurable value, between 104L and 102L is greater than the capacitance measured between 104L and 104R.

[0141] A quantum device as described above can be adapted to different types of reading circuits. For example, it is adapted to a transport reading circuit where the quantum state of a quantum box is read by measuring the current in the associated detection Pilot. It is also adapted to a reading circuit operating by reflectometry where an RF signal is emitted in the direction of the detection Pilot and then a reflected RF signal is detected to deduce the charge state of a quantum box associated with this detection island.

[0142] A quantum device as provided according to one or more of the previously described methods may be implemented using a thin-film microelectronic manufacturing method.

[0143] We first refer to [Fig.5] which gives an example of a possible starting structure for the production of a quantum device according to the invention and which here comprises a substrate 5 which can be of the semiconductor on insulator type, for example SOI, or of the solid type and for example made of silicon.

[0144] A stack of layers formed of an alternation of layers 10i, 103, 105 in a first material 12 and of layers 102, 104, in a second material 14 is produced on the substrate 5. The materials 12, 14 are typically semiconductor materials different from one another, the first material 12 being capable of being etched selectively with respect to the second material 14. The particular embodiment illustrated in [Fig.5] provides an odd number of layers, in particular five layers, but the method can be carried out with a different and in particular higher number of layers.

[0145] The layers 10i, 103, 105 based on the first material 12 can advantageously be produced with a thickness greater than that of the layers 102, 104, based of the second material 14, and which may be, for example, more than twice that of the layers 102, 104. The layers 10i, 103, 105 based on the first material 12 may have a thickness ei of, for example, between 10nm and 50nm, while the layers 102, 104 have a thickness e2 of, for example, between 5nm and 20nm.

[0146] For example, the first material 12 is made of silicon while the second material 14 is made of Sii_xGex, with x > 0, x being for example of the order of 30%. The layers 10i, 103, 105, 102, 104, can be produced by successive epitaxies.

[0147] When the first layer 10i is made of SiGe, this layer can optionally be formed from a surface layer of silicon of an SOI substrate by a Germanium enrichment method known to those skilled in the art and which consists of carrying out silicon epitaxy and then carrying out oxidation in order to diffuse the germanium. Etching is then carried out so as to remove the oxide formed.

[0148] Then (figures 6A and 6B), by etching the stack of layers 10i, 102, 103, 104>105, an active zone structure 16 is defined, here in the form of a block, typically of oblong shape, for example parallelepiped, and which extends mainly in a first direction (direction orthogonal to the plane of [Fig.l] and parallel to the y axis of the orthogonal reference [0;x;y;°z]). This can be achieved by photolithography and etching of the stack. Dry etching using fluorocarbon chemistry through a lithography mask (not shown) can be carried out for this.

[0149] Grid patterns 25 are then formed from grid material 22 on either side of the structure 16.

[0150] For this, at least one layer 21 of at least one gate dielectric is first deposited, for example silicon oxide (SiO2) or formed from a stack of silicon oxide and a high-k material such as for example HfO2. This deposition is followed by that of at least one layer of conductive gate material 22, such as doped polysilicon ([Fig.7]).

[0151] Preferably, after deposition and possible planarization by CMP, a non-zero thickness, for example of the order of 50 nm, of conductive material 22 is left to protrude above the active zone structure 16.

[0152] Hard masks 31, typically dielectric and for example formed from a stack of SiN and SiO2 are then produced ([Fig.8]).

[0153] We then carry out ([Fig.9] giving a sectional view according to the first sectional plane parallel to the [0;y;°z] reference) lithography and etching of the grid stack to form a network of 25 parallel grid patterns. The 25 grid patterns can be distributed according to a small pitch Pg, for example of the order of 100 nm, or even smaller, for example 40 nm, to form a dense network of 25 patterns.

[0154] After the formation of the grid patterns 25, it is advantageous to form reservoirs of DTI, DT2 dopants (figures 10 to 13).

[0155] According to one method, a thin insulating spacer layer 33 is firstly deposited in a conformal manner on the gate patterns 25 ([Fig. 10] giving a sectional view along a second sectional plane parallel to the reference [0;y;°z] and distinct from the first sectional plane of [Fig.9]), for example made of silicon nitride and of a thickness which may be for example between 5 nm and 10 nm. The thin insulating spacer layer 33 is arranged on and between the gate patterns 25, for example by an ALD (for “Atomic Layer Deposition”) type technique in order to fill the inter-pattern-gate spaces without creating a filling defect.

[0156] Lithography is then carried out so as to remove portions of the thin insulating spacer layer 33 and extend this etching into parts of the active zone structure 16 located around another part 161 in line with all of the grid patterns 25 ([Fig. 10] giving a sectional view along a second sectional plane parallel to the reference [0; y; °z] and different from the first sectional plane).

[0157] To form the dopant reservoirs in contact with the semiconductor layers 102, 104 in which it is planned to form the quantum dots and detection islands without bringing these reservoirs into contact with the other layers 10i, 103, 105 of the structure, it is advantageous to carry out a partial selective etching of the first material 12 with respect to the second material 14 in order to create recesses 41. ([Fig. 11]) at the flanks of the structure 16. For example, when the first material 12 is made of SiGe, this etching is carried out, for example, by wet chemical etching, or using HCl or a HF:H2O2:CH3COOH mixture. A withdrawal of at least 5 nm, for example, may be provided to produce these recesses 41. The recesses 41 are then filled by insulating plugs 43, also called “internal spacers” ([Fig. 12]). This may be carried out, for example, by means of a conformal deposition of dielectric material, for example SiN or SiO2. This deposition is typically followed by a dry etching or a combination of dry and wet etching of the deposited dielectric, so as to form insulating plugs 43 blocking access to the layers 10i, 103, 105 based on the first material 12.

[0158] Once the caps 43 have been made, selective epitaxy of semiconductor material 48 can be carried out from the exposed ends of the layers 102, 104, based on the second material 14. The epitaxy can provide in situ doping. For example, reservoirs of DTI, DT2 dopants in Si:P or in SiGe:B can be formed by epitaxy from ends of silicon layers. The epitaxy formed may or may not follow preferential crystalline orientations, and the epitaxy fronts from the different layers of Si can possibly join together as in the embodiment shown in [Fig. 13] to form semiconductor blocks or clusters 49.

[0159] We can then form superimposed grids.

[0160] For this, one method first consists of producing an insulating encapsulation 52 around the gate patterns. The insulating encapsulation 52 can be produced for example by depositing a PMD (for “Pre Metal Dielectric”) type material such as for example SiO2 over the entire structure followed by a CMP planarization step. This step is preferably carried out so that the polishing front stops at the top of the active zone structure 16. This makes it possible to reveal the material 22 of the gate patterns, typically a conductive gate material such as polysilicon.

[0161] A partial etching of the material 22 of the grid patterns is then carried out ([Fig. 15]). The partial removal of the grid material 22 is carried out so as to retain a lower block 24 of grid material and to produce cavities 54 surrounded by the encapsulation 52 and arranged above this lower block 24 of grid material. A dry etching or a chemical etching, in particular a wet etching using TMAH (“Tetramethylammonium hydroxide”) is in particular implemented when the material 22 is polySi.

[0162] The etching is carried out so as to control the height of the lower block 24 of gate material relative to that of the semiconductor layers of the active zone structure 16. A partial removal is implemented so that this block 24 intended to form a lower gate GI is opposite only a single layer 102 based on the second material 14, in particular only the lower level semiconductor layer intended to accommodate quantum dots or qubits.

[0163] These cavities 54 are then filled ([Fig. 16]) with at least one layer of insulating material 56, for example SiO2. This deposition is optionally followed by planarization and etching to partially remove the deposited insulating material 56 ([Fig. 17]). The insulating material 56 is used to form an insulation zone ZI making it possible to insulate the superimposed gate stages from each other. A new layer of conductive material, advantageously based on the same conductive material 22 as the lower gate GI, for example polysilicon, is then deposited ([Fig. 18]) so as to fill the cavities 54. Planarization is then typically carried out by CMP (Figures 19A, 19B) to thus form an upper gate GS.

[0164] A separation trench 65 is then produced (figures 20A, 20B) in order to divide the active zone structure 16 into two distinct portions 16R, 16L. The trench 65 is typically produced until it reaches the substrate 5 through the opening 63 of a masking 61. The trench 65 extends mainly in one direction parallel to the y axis given in Figures 20A and 20B also corresponding to the main direction in which the first portion 16A and the second portion 16B extend.

[0165] The masking 61 is for example formed on the basis of a stack of litho-grahic resin typically comprising a photosensitive resin formed on an anti-reflective layer itself formed on a so-called “planarizing” layer, typically organic and for example of the SOC (for “Spin-On-Carbon”) type. The etching of the trench is typically anisotropic, for example carried out using a fluorocarbon plasma.

[0166] According to a particular embodiment, the width D (dimension measured parallel to the x axis in [Fig.20A]) of the trench 65 corresponding to the distance between the portions 16R, 16L has a dimension of between 30nm and 60nm, for example of the order of 50nm. This trench 65 leads to the production of two portions 16R, 16L which face each other, each formed from the same alternation of layers in a first material and in a second material, for example SiGe and Si.

[0167] In the particular embodiment where, rather than based on an insulating material, a first semi-conductor material 12 is used for the layers 10i, 103, 105 of the stack based on which the portions 16R, 16L are each formed, it is possible to replace this semi-conductor material 12 with a dielectric material in order to form separation zones between the different levels of layers 102, 104 based on the second material 14.

[0168] Thus, in this case, first of all ([Fig.21]) a removal of the layers 10i, 103, 105 based on the first material 12 is carried out by selective etching with respect to the second material 14. In the case where the first material 12 is made of SiGe and the second material 14 is made of silicon, this selective removal of the SiGe in order to release the silicon can be carried out by isotropic and selective etching of the SiGe layers, for example by wet chemical etching and based on HCl or HF:H2O2:CH3COOH.

[0169] Spaces 71 are thus freed between regions based on the second material 14. The dopant reservoirs (not visible in [Fig.21]) can then participate in maintaining the semi-conductor regions based on the second material 14.

[0170] It is then filled with a dielectric material 73 so as to form insulating “separation” zones ZS1, ZS2.

[0171] The choice of the dielectric material of the insulating zones ZS1, ZS2 is made in particular in terms of permittivity or dielectric constant of this material depends on whether or not it is desired to promote coupling in the vertical direction (direction parallel to the z axis) between successive semiconductor stages of material 14 in the portions 16 A, 16B.

[0172] The insulating zones ZS1, ZS2 are typically produced by a conformal deposition of dielectric material 73 then an anisotropic etching or a combination of anisotropic / isotropic etching(s) of this dielectric material 73 so as to only retain this dielectric material 73 in spaces located directly above the remaining regions of the semiconductor layers 102, 104 based on the second material 14 ([Fig.22]). A remaining unfilled empty volume forming a reduced trench 75 is thus produced between the two portions 16R, 16L of structure 16 of the active zone.

[0173] The dielectric separation region RD is then formed (figures 23A and 23B) between the first portion 16R provided with a first set of semiconductor regions based on the second material 14 and the second portion 16L provided with a first set of semiconductor regions based on the second material 14.

[0174] For this, a conformal deposition of dielectric material 85 is typically carried out, followed by CMP planarization of this dielectric material 85 so as to fill the remaining empty volume forming a reduced trench 75 separating the two portions 16R, 16L. Two sets of semiconductor regions facing each other are then separated by this dielectric material 85. Here again, the dielectric and its permittivity are chosen so as to promote or not the coupling in the horizontal direction (direction parallel to the x axis) between the two networks of semiconductor regions facing each other.

[0175] In the example of the production method which has just been given, for the implementation of the superimposed grids GI, GS, lower grids GI are provided formed from the same material 22 as the upper grids GS. It is however possible, as a variant, to provide different materials between the lower grids GI on the one hand and the upper grids GS on the other hand.

[0176] Similarly, in the embodiment example which has just been given, the grids formed against the portion 16R of active zone dedicated for example to receiving the quantum boxes are based on the same material as those located against the portion 16L of active zone which faces it and which is dedicated for example to receiving the detection islands.

[0177] It is however possible as a variant to provide different materials between, on the one hand, the grids located against the portion 16R and, on the other hand, the grids located against the portion 16L. Such a variant can be carried out to obtain output work and consequently different operating regimes between, for example, grids controlling the quantum dots and grids controlling the detection islands. To carry out such a variant, it is possible to provide for adding one or more lithography steps and one or more additional deposition steps.

[0178] As a variant of the example of the production method which has just been given, the implementation of the superimposed grids GI, GS, which describes a commonly type approach called "gate-last" (gate last) where at least partial replacement of patterns is carried out by a stack with grids separated by an isolation zone, we can plan to carry out this stacking directly.

[0179] Thus, according to an alternative embodiment of the gates, an approach of the type called "gate-first" (gate first) can be provided. In this case, directly after the step of forming the active zone structure 16 described previously in connection with FIGS. 6A-6B, it is possible to provide for the production of a stack of layers to form the lower gate, the insulation zone, then the upper gate. The thicknesses of the conductive or semi-conductive layers of gate material(s) and of the intercalated insulating layer are then preferably adjusted according to those of the layers of first material 12 and second material 14 of the structure 16 so that each layer of gate material is arranged opposite and in the same plane parallel to the main plane of the substrate as a layer based on the second semiconductor material 14 and in which quantum dots or detection islands are provided.

[0180] In one or other of the embodiments which have just been described, the contacting on different gate levels as well as on different semiconductor layer levels can be achieved for example by providing, at the ends of the gate structures or portions of active zone, a staircase shape.

[0181] In a quantum device as described above, where horizontal interactions are favored (in other words in directions parallel to the main plane of the substrate) between, on the one hand, a quantum box BQ1 (respectively BQ2) and, on the other hand, a detection island ID1 (respectively ID2) located in the same horizontal plane as this quantum box BQ1 (resp. BQ2), it may also be desired to avoid a so-called "diagonal" coupling in a diagonal direction DIAG1 (resp. DIAG2) between a quantum box BQ1 (resp. BQ2) and a detection island ID2 (respectively ID1) located in a plane other than this quantum box BQ1 (resp. BQ2).

[0182] Thus, in an exemplary embodiment illustrated in [Fig. 24], a dielectric region RD is provided for this purpose between the set of semiconductor regions 102R, 104R and the set of semiconductor regions 102L, 104L, here with a heterogeneous composition. A central portion 244 located between a first lower semiconductor region 102R and a second upper semiconductor region 104L and between the first upper semiconductor region 104R and the second lower semiconductor region 102L is based on a dielectric material having a composition and a first relative dielectric permittivity. Another portion 242 of the dielectric region RD located between the first lower semiconductor region 102R and the second lower semiconductor region 102L is provided based on another dielectric material having a composition and a permittivity different and higher relative dielectric than that of the material of the central portion 244. A portion 246, of the dielectric region RD located this time between the first upper semiconductor region 104R and the second upper semiconductor region 102L is also provided based on a dielectric material having a composition and a higher relative dielectric permittivity than that of the material of the central portion 244.

[0183] An example of a method for producing such a type of device is illustrated in Figures 25 to 29.

[0184] We can start from a structure as described in connection with the [Fig.22]. Then ([Fig.25]) a dielectric material 241 is deposited, so as to fill the space separating the two portions 16R, 16L. This dielectric material 241 can then be planarized, for example by CMP (“Chemical mechanical planarization”, i.e. “chemical mechanical polishing”).

[0185] The dielectric material 241, for example such as SiN or HfO2, is then partially removed ([Fig.26]) typically by wet etching using H3PO4 in the case of SiN or plasma CH2F2, SF6 in the case of SiN, CF4 / Ar in the case of HfO2 in order to form the lower portion 242 of the insulation region.

[0186] Another dielectric material 243 is then deposited, typically with a lower dielectric permittivity than the dielectric permittivity of the dielectric material 241 ([Fig.27]). The other dielectric material 243 may be, for example, SiO2 and form the central portion 244 of the dielectric region RD.

[0187] A possible planarization by CMP of this other material 243 is then carried out.

[0188] In the particular embodiment illustrated in [Fig.28], a partial removal is then carried out, typically by wet etching using HF or CF4 plasma, of this other material 243 in order to form the central portion 244 of the dielectric region RD.

[0189] The dielectric material 241 can then be deposited again in order to form an upper portion 246 of the dielectric region RD ([Fig.29]) which, in this example, has a composition identical to that of the lower portion 242. This dielectric material 241 can then be planarized, for example by CMP.

[0190] Alternatively, the upper portion 246 may be formed from a third dielectric material different from that of the portions 242, 244 but with a dielectric permittivity greater than the dielectric permittivity of the dielectric material 243 of the central portion 244.

[0191] Another example of the realization of a heterogeneous RD dielectric region in terms of dielectric material composition is given in [Fig.30].

[0192] The dielectric region RD is here formed of a dielectric material 305 having a dielectric constant kl coating each of the first and second semi- lower and upper conductive regions 102R, 102L, 104R, 104L, so as to form lower insulating shells 308R, 308L against the first and second lower semiconductor regions 102R, 102L and upper insulating shells 309R, 309L against the first and second upper semiconductor regions 102R, 104R.

[0193] An insulating space formed between the insulating envelopes 308R, 308L 309R, 309L is here filled by a dielectric material 303 having a second dielectric constant k2 lower than the dielectric constant kl of the dielectric material 305. A central portion 344 of dielectric material 303 is thus provided to prevent “diagonal” coupling between the semiconductor regions 102L and 104R, and between the semiconductor regions 102R, 104L.

[0194] An example of a method for producing such a type of device is illustrated in Figures 31 to 34.

[0195] We can start from a structure such as described in connection with the [Fig.21] obtained after selective etching of the first material 12 in order to release the regions 102R, 102L, 104R, 104L based on the first material 14.

[0196] First of all, a semiconductor envelope 301 is formed ([Fig.31]) by epitaxy on the regions 102R, 102L, 104R, 104L based on a sacrificial semiconductor material 312. It is chosen to grow, preferably isotropically, a semiconductor material 312 which can be selectively etched with respect to the second material 14. In the particular example illustrated in [Fig.31], this sacrificial semiconductor envelope 301 can be identical to the first material 12, for example SiGe when the material 14 of the regions 102R, 102L, 104R, 104L is made of silicon. The growth is preferably carried out so as to form semiconductor shells and to preserve a space 302 between semiconductor shells formed on the first portion 16A of the active zone structure and the second portion 16B located opposite and separated from the first portion 16A.

[0197] This space 302 is then filled with a given dielectric material 303 having a given dielectric constant k2, for example SiO2 ([Fig.32]). This can be achieved by deposition then CMP planarization.

[0198] A selective removal of the semiconductor envelope 301 based on the sacrificial material 312 is then carried out ([Fig.33]). A selective etching of the SiGe relative to the silicon can in particular be implemented. Such etching leads to the formation of galleries 304A, 304B around the semiconductor regions 102R, 102L, 104R, 104L based on the first material 14.

[0199] The galleries 304A, 304B are then filled with a dielectric material 305 of dielectric constant kl, for example SiN or HfO2 or Al2O3. A method ALD deposition (ALD for “Atomic Layer Deposition”) can be implemented in particular to avoid any filling defects ([Fig.34]).

[0200] According to an alternative embodiment ([Fig.35]), instead of the dielectric material 303 of dielectric constant k2, it is possible to provide a dielectric region RD separating the two portions 16A, 16B of the active zone structure, with a space 313 empty or filled with air in a central portion 344 of the dielectric region RD and located between the insulating envelopes based on the dielectric material 305 of dielectric constant kl. This can make it possible to further limit the possibilities of diagonal coupling between semiconductor regions 102L, 104R and 104L, 102R.

[0201] To implement such a variant, one can start from a structure as obtained previously and described in connection with [Fig.34], then carry out a selective removal of the dielectric material 303 of dielectric constant k2 with respect to the dielectric material 305 of dielectric constant kl. Such selective removal is for example carried out using H3PO4 when the dielectric material 303 and the dielectric material 305 are respectively SiN and HfO2.

[0202] Another example of a method for producing the dielectric region RD between the two portions 16A, 16B of the active zone is illustrated in FIGS. 36 to 40.

[0203] This time we can start from a structure of the type described in connection with [Fig.22] to obtain the separation zones ZS1, ZS2 in insulating material 73.

[0204] The sacrificial semiconductor envelope 301 is then first formed ([Fig.36]) by epitaxy on the semiconductor regions 102R, 102L, 104R, 104L.

[0205] The dielectric material 303 of dielectric constant k2, for example SiO2 ([Fig.37]), is then deposited.

[0206] The sacrificial semiconductor envelope 301 based on the first material 12 ([Fig.38]) is then selectively removed so as to release volumes in the form of galleries 304A, 304B around the semiconductor regions 102R, 102L, 104R, 104L based on the first material 14.

[0207] The galleries 304A, 304B are then filled using the dielectric material 305 of dielectric constant kl, for example SiN or HfO2 or A12O3, advantageously using an ALD type deposition process in order to avoid a filling defect ([Fig.39]) to form the dielectric region RD of heterogeneous composition.

[0208] As for the embodiment example described previously, it is possible, here again, optionally, to then selectively remove the dielectric material 303 of dielectric constant k2 ([Fig.40]). An empty space is thus preserved between upper envelopes located on the upper semiconductor regions and between the lower insulating envelopes located respectively on the first and second lower semiconductor regions.

[0209] As a variant of one or other of the method examples which have just been described, it is possible to provide exchange electrodes in inter-grid spaces.

[0210] For this, a method illustrated in Figures 41 and 42 consists of starting from a structure such as obtained at the end of the production of the grids and described for example previously in connection with Figures 19A-19B. A masking 410 is then produced, typically in photosensitive resin, in an area located above the grid block assembly and which comprises openings 412 facing inter-grid spaces ([Fig.41]). The encapsulation material 52, for example SiO2, located in the inter-grid spaces selectively relative to the thin spacer layer 33, for example in SiN, is then selectively etched in order to form holes 414. A fluorocarbon dry etching method can be used in particular.

[0211] After removal of the masking 410, a deposition of conductive material 416, for example a TiN / W type stack, is carried out to fill the holes 414 thus defined ([Fig.42]). This deposition is typically followed by a CMP planarization step. The planarization is preferably stopped when the top of the active zone structure is reached (not visible in FIGS. 41 and 42). In this exemplary embodiment, a single GE exchange electrode is produced per inter-grid space.

[0212] However, it is alternatively possible to form superimposed exchange grids which follow an arrangement similar to that of the grid electrodes between which these exchange grids are inter-calated. It is thus possible to form in each inter-grid space pairs of superimposed exchange grids separated from each other by an insulator. For this, it is possible to follow a method similar to that used to produce the grids and described previously in connection with FIGS. 15 to 19A-19B.

Claims

1.

2. Claims Quantum electronic device having a substrate (5), the substrate being coated: - a first set of semiconductor regions (102L, 104L) comprising at least one first lower semiconductor region (102L) and at least one first upper semiconductor region (104L), superimposed on, and separated from, the first lower semiconductor region by means of a first so-called “separation” zone (ZS1), made of dielectric material, - a second set of semiconductor regions (102R, 104R) comprising at least one second lower semiconductor region (102R) and at least one second upper semiconductor region (104R), superimposed on, and separated from, the first lower semiconductor region by means of a second so-called “separation” zone (ZS2) made of dielectric material, the first set of semiconductor regions (102L, 104L) being arranged opposite the second set of semiconductor regions (102R, 104R) so that the first lower semiconductor region (102L) is arranged opposite the second lower semiconductor region (102R) and so that the first upper semiconductor region (104L) is arranged opposite the second upper semiconductor region (104R), - at least one dielectric region (RD) separating the first set of regions semiconductors (102R, 104R) of the second set of semiconductor regions (102R, 104R),said dielectric region (RD) having a heterogeneous composition., A quantum electronic device according to claim 1, said dielectric region (RD) being configured so as to allow electrostatic coupling between the first lower semiconductor region (102L) and the second lower semiconductor region (102R), and so as to allow electrostatic coupling between the first upper semiconductor region (104L) and the second upper semiconductor region (104R), said dielectric region (RD) being provided with a heterogeneous composition and so as to prevent electrostatic coupling between the first lower semiconductor region (102L) and the second upper semiconductor region (104R), and so as to prevent an electrostatic coupling between the first upper semiconductor region (104L) and the second lower semiconductor region (102R).

3. A device according to claim 1 or 2, wherein the dielectric region (RD) between the first set of semiconductor regions (102L, 104L) and the second set of semiconductor regions (102R, 104R) is provided with a heterogeneous dielectric composition such that in a central portion (244, 344) located between the first lower semiconductor region (102L) and the second upper semiconductor region (104R) and between the first upper semiconductor region (104L) and the second lower semiconductor region (102R), the dielectric region (RD) is formed with a given dielectric material composition and a given dielectric constant k2, and that in another portion (242, 246) located between the first lower semiconductor region and the second lower semiconductor region or between the first upper semiconductor region and the second lower semiconductor region superior,the dielectric region (RD) has a second composition and a higher relative dielectric constant than the given dielectric constant k2.,

4. A device according to one of claims 1 or 2, wherein the heterogeneous dielectric region (RD) between the first set of semiconductor regions (102L, 104L) and the second set of semiconductor regions (102R, 104R) is provided with a heterogeneous dielectric composition such that in a central portion (244, 344) located between the first lower semiconductor region (102L) and the second upper semiconductor region (104R) and between the first upper semiconductor region (104L) and the second lower semiconductor region (102R), the dielectric region (RD) is formed of an empty space (313) and that in another portion (242, 246) located between the first lower semiconductor region and the second lower semiconductor region or between the first upper semiconductor region and the second upper semiconductor region, the dielectric region (RD) is formed from a dielectric material.

5. Device according to one of claims 1 to 4, in which the dielectric region (RD) between the first set (102L, 104L) and the

6. second set (102R, 104R) of semiconductor regions is formed: - a lower dielectric portion (242) arranged between the first lower semiconductor region (102L) and the second lower semiconductor region (102R), - an upper dielectric portion (246) located between the first upper semiconductor region (104L) and the second upper semiconductor region (104L), - a central dielectric portion (244), arranged between the lower dielectric portion (242) and the upper dielectric portion (246), the lower dielectric portion (242), the central dielectric portion (244) and the upper dielectric portion (246) being superimposed, the central dielectric portion (244) being made of a given dielectric material (243) having a first dielectric constant k2, the lower dielectric portion (242) and the upper dielectric portion (246) being based on one or more dielectric materials different from said given dielectric material and with respective dielectric constant(s) greater than k2. Device according to one of claims 1 to 4, in which the dielectric region (RD) of heterogeneous composition between the first set of semiconductor regions (102L, 104L) and the second set of semiconductor regions (102R, 104R) is formed: - of at least one dielectric material (305) having a dielectric constant kl coating each of the first and second lower and upper semiconductor regions, so as to form lower insulating envelopes (308L, 308R) against the first and second lower semiconductor regions (102L, 102R) and upper insulating envelopes (309L, 309R) against the first and second upper semiconductor regions (104L, 104R), and - at least one insulating space (344) between an upper insulating bump located on the first or second upper semiconductor region and an insulating bump lower located on the first or second lower semiconductor region,the insulating space (344) being:, - filled with a given dielectric material (303) having a dielectric constant k2, such that k2 < kl, or - being an empty space (313).

7. Quantum electronic device according to one of claims 1 to 6, said separation zones (ZS1, ZS2) being provided so as to allow electrostatic coupling between the first lower semiconductor region (102L) and the first upper semiconductor region (104L), and so as to allow electrostatic coupling between the second lower semiconductor region (102R) and the second upper semiconductor region (102L).

8. A quantum electronic device according to one of claims 1 to 7, wherein the first lower semiconductor region (102L) and the first upper semiconductor region (104L) are regions of a lower semiconductor rod and an upper semiconductor rod respectively, the lower semiconductor rod and the upper semiconductor rod being arranged one above the other and extending parallel to a first direction (y) parallel to a main plane of the substrate.

9. Quantum electronic device according to claim 8, further comprising a plurality of control gates (GI1, GSI) of the lower semiconductor rod and of the upper semiconductor rod, the control gates (GI1, GSI) extending in a second direction making a non-zero angle with the first direction and advantageously orthogonal to the first direction.

10. Quantum electronic device according to one of claims 1 to 9, further comprising: - a first group of superimposed gates (GI1, GSI) comprising at least a first lower gate (GI1) and a first upper gate (GSI) superimposed on, and separated from the first lower gate by a first insulation zone (ZI1), the first lower gate (GI1) and the first upper gate (GSI) being arranged against, and facing, respectively the first lower semiconductor region (102L) and the first upper semiconductor region (104L) so as to respectively exercise electrostatic control of the first lower semiconductor region and the first upper semiconductor region, - a second group of superimposed gates comprising at least a second lower gate separated from a second upper gate superimposed on,and separated from the second lower grid by a second insulation zone (ZI2), the second lower grid and the second upper grid being arranged against, and, facing, respectively, the second lower semiconductor region (102R) and the second upper semiconductor region (104R) so as to respectively exercise electrostatic control of the second lower semiconductor region (102R) and the second upper semiconductor region (104R), the first group of superimposed grids and the second group of superimposed grids being arranged on either side of the first set of semiconductor regions and the second set of semiconductor regions.

11. A method of manufacturing a quantum device according to one of claims 1 to 10, wherein the formation of the first set of semiconductor regions (102L, 104L) and said second set (102R, 104R) of semiconductor regions comprises steps of: - producing on said substrate (5) a structure (16) formed of a superposition of layers (10i, 102, 103, 104, 105) composed of an alternation of layers (10i, 103, 105) based on a given first material (12), and of layers (102, 104) based on a second material, the second material being semiconductor, said given first material being capable of being selectively etched with respect to said given second material, - producing a separation trench (65) extending mainly in a direction parallel to the first direction by etching said superposition of layers so as to divide said structure into a first portion (16A) and a second portion (16B),the first portion (16A) and the second portion (16B) extending parallel to the first direction, the semiconductor regions of said first set being semiconductor regions of the first portion and formed from said second given material, the semiconductor regions of said second set being semiconductor regions of the second portion and formed from said second given material, and in which said heterogeneous dielectric region (RD) is then formed in the separation trench (65) between said first portion (16A) and said second portion (16B) of said structure (16).,

12. A method according to claim 11, the formation of said dielectric region (RD) comprising steps of: - depositing in the separation trench (65) a first dielectric material (241) to form a lower dielectric portion (242) arranged between the first lower semiconductor region (102L) and the second lower semiconductor region (102R), - depositing in the separation trench (65) a second layer based on a given dielectric material (243) different from the first dielectric material (241) and with a given dielectric constant k2 lower than that of the first dielectric material to form a central dielectric portion (244), - depositing in the separation trench (65) the first dielectric (241) or a third dielectric material with a dielectric constant higher than that of the given dielectric material to form an upper dielectric portion (246) arranged between the first upper semiconductor region (104L) and the second upper semiconductor region (104R).

13. Method according to claim 12, in which after deposition of the first dielectric material (241) and prior to the deposition of the given dielectric material (243): a partial removal of the first dielectric material (241) is carried out in the trench (65), and in which after deposition of the given dielectric material (243) and prior to the formation of the upper dielectric portion (246), a partial removal of the given dielectric material (243) is carried out.

14. A method according to claim 12, the formation of said dielectric region (RD) comprising steps of: - epitaxial growth on the first lower semiconductor region (102L), the first upper semiconductor region (104L), the second lower semiconductor region (102R) and the second upper semiconductor region (104R), of a sacrificial semiconductor material (312) and so as to preserve an empty space (302) between the first portion and the second portion of the structure, - filling said empty space (302) by means of a given dielectric material (303) of given dielectric constant k2, - removal of the sacrificial semiconductor material (312) selective with respect to that of the first lower semiconductor region (102L), the first upper semiconductor region (104L), the second lower semiconductor region (102R) and the

15. second upper semiconductor region (104R), in order to free volumes around respectively the first lower semiconductor region (102L), the first upper semiconductor region (104L), the second lower semiconductor region (102R) and the second upper semiconductor region (104R), - filling the volumes using a dielectric material different from the given dielectric material and having a dielectric constant kl greater than k2. The method of claim 12, wherein the formation of said dielectric region (RD) comprises steps of: - epitaxial growth on the first lower semiconductor region (102L), the first upper semiconductor region (104L), the second lower semiconductor region (102R) and the second upper semiconductor region (104R), of a sacrificial semiconductor material (312) and so as to preserve an empty space (302) between the first portion and the second portion, - filling said empty space (302) by means of a dielectric material (303), - removing the sacrificial semiconductor material (312) selective with respect to that of the first lower semiconductor region (102L), the first upper semiconductor region (104L), the second lower semiconductor region (102R) and the second upper semiconductor region (104R), in order to free volumes around respectively the first lower semiconductor region (102L), the first upper semiconductor region (104L), the second lower semiconductor region (102R) and the second upper semiconductor region (104R), - filling the volumes using another dielectric material different from the given dielectric material and capable of being etched selectively with respect to said given dielectric material, - removing said given dielectric material selectively with respect to said other dielectric material.