ELECTRONIC CIRCUITS FOR ACQUIRING THE THRESHOLD VOLTAGE OF A POWER TRANSISTOR

Abstract

The invention relates to a device (10, 20) for monitoring the state of health of a power transistor comprising: - means (8) for applying to this transistor an “ultra slow” starting voltage (VGS); - means (12-22) for measuring the dip in the gate voltage (VGS) which follows the Miller plateau. Figure for the abstract: Fig. 4

Description

Title of the invention: ELECTRONIC CIRCUITS FOR ACQUIRING THE THRESHOLD VOLTAGE OF A POWER TRANSISTOR TECHNICAL FIELD AND PRIOR ART

[0001] The invention relates to the field of power electronics, and in particular that of electrification and electrical power hybridization in general and particularly in aeronautics.

[0002] In this context, there is a need for high-performance, integrated, reliable and secure power electronic systems. The power module for motor control is a key function on which significant efforts must be concentrated. The introduction of wide-gap power semiconductor components such as the silicon carbide (SiC) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) within the power module has made it possible to reduce the on-board mass and volume by 15 to 30% and to increase electrical efficiency by 2 to 3 points.

[0003] SiC MOSFETs are power semiconductor devices that offer many advantages, such as high performance, increased energy efficiency, and improved high-temperature resistance compared to traditional silicon (Si) MOSFETs. However, their adoption in the aerospace industry still presents certain challenges that limit their maturity and widespread deployment.

[0004] In particular, there are no means available to monitor the reliability of these transistors in continuous operation and in a non-intrusive manner. The same problem arises more generally for semiconductor transistors based on wide-gap semiconductors, such as for example with GaN technology. By "wide gap" is meant an energy gap or a height of the forbidden band Eg separating the last occupied states of the valence band and the first free states of the conduction band, which is greater than for silicon. The same problem also arises for MOSFETs made of traditional silicon (Si).

[0005] However, monitoring the health status of such a transistor, particularly a large gap transistor, in particular a SiC MOSFET, is a key issue for its adoption in applications with high reliability and long potential lifetime, such as aeronautics. Indeed, during its operation within a power converter, performance drops linked to the aging of the component may appear. These performance degradations result from variations in intrinsic physical parameters, particularly in the case of a SiC MOSFET, linked to electric charge trapping phenomena, for example, in the case of a SiC MOSFET, within the silicon dioxide (SiO2) gate oxide layer in the presence of defects at the interface with the SiC substrate.

[0006] These effects are all the more marked in SiC technology than in Si technology given the lower quality of production of the gate oxide layer which is itself, in parallel, subjected to greater stress in the electric field on SiC MOSFET.

[0007] Indeed, in a silicon MOSFET, the gate oxide (SiO2) is generally well-matched to the crystalline structure of silicon. Silicon and silicon dioxide have a natural chemical affinity, which facilitates the growth of a native, uniform, and low-deficiency gate oxide layer. In contrast, silicon carbide (SiC) has a different and more complex crystalline structure compared to silicon. Growing a high-quality gate oxide layer on SiC is more difficult due to the less natural nature of the interface between SiC and SiO2.

[0008] Crystal defects in the gate oxide layer of Si MOSFETs are generally less frequent and more stable. Manufacturing technologies for SiO2 on Si are highly developed, allowing the production of high-quality oxide layers with few defects. In the case of SiC MOSFETs, the growth of the gate oxide on SiC may be more prone to the formation of defects. These defects may include oxygen vacancies, structural imperfections, and recombination sites. They may be caused by differences in the mobility of atoms between SiC and SiO2, thermal stresses during the manufacturing process, and other factors.

[0009] All of these defects can give rise to charge traps at the gate oxide. This tunneling trapping can take place either at the surface, at the SiC / SiO2 interface, or deeper in the volume of the oxide. Tunneling is a quantum process that allows electrons to "tunnel" through an energy barrier that, classically in silicon, would be too high for them to pass through. In the context of SiC MOSFETs, tunneling occurs when the channel electrons, under the influence of the gate voltage, acquire enough kinetic energy to pass through the thin gate oxide layer and become trapped in it.

[0010] These trapping phenomena on SiC MOSFETs are complex and depend on the voltage bias conditions of the gate oxide (DC component and AC component linked to the control switching). They are also exacerbated at high operating temperatures. Trapping leads on the one hand to a slow but continuous increase in the threshold voltage VTh, and on the other hand, to a decrease in the mobility p of the electrons in the channel. The combination of these two effects leads on the one hand to an increase in the channel resistance, and therefore to losses by conduction, and on the other side an increase in the amplitude of the Miller plateau, thus reducing the switching speed (especially the dv / dt at ignition whose loss component is dominant) and increasing the switching losses.

[0011] There are several secondary indicators of the health of a SiC MOSFET: the on-state resistance RDson, the duration and amplitude of the Miller plateau. These quantities are certainly impacted by the aging of the transistor, but are made up of several other components, each providing contributions that drown out the intrinsic variations due to the component's own aging. Their relevance for monitoring the health of the transistor can then be questioned.

[0012] There are other indirect indicators such as the gate leakage currents IGSS and drain IDSS, the internal gate resistance Rgint(Vgs) and the characteristic C1Ss = f(VGS ) (see in particular A.E1 Boubkari, Development of fast, precise and integrated CMOS functionalities, for optimal switching and internal protection of inverters with SiC MOSFET modules (hal.science. 2023)): • The IGSs gate leakage current increases by several orders of magnitude between a healthy component (a few hundred femtoamperes) and a component with a cracked gate (around 10mA). Measuring this parameter requires an extremely precise and stable differential measurement of the voltage across the external gate resistor, but IGSs does not act as a precursor, but rather as a final indicator of irreversible degradation. This leakage measurement as a precursor (before cracking of the gate oxide) is possible thanks to a dedicated driver channel as explained in application PCT / FR2023 / 051145 with a sensitivity of 30nA. However, its implementation remains complex. • Monitoring drain leaks is based on measuring an observable on the power side (between drain and source) and must be accurate to the order of a milliampere, making it not feasible in practice within a converter. • It is shown that by performing a VGS sweep from negative to positive values using a static characteristics tracer (e.g. Keysight B1505A), a shift in the “flatband” voltage appears for the aged component. A similar property can be obtained by sweeping on RGint(Vgs) and monitoring the variation of this value. However, this method remains difficult to apply to an on-board measurement.

[0013] The main indicator whose variations faithfully reflect the evolution of the health status of the component remains the threshold voltage VTH. However, in the current state of the art, this parameter is not currently directly measurable in real time when the transistor is integrated within a power converter in operation and subject to a cutting regime. Statement of the invention

[0014] The present invention aims to solve all or part of the problems set out above.

[0015] It proposes in particular an electronic circuit for monitoring, for example within a power converter, the state of health of a MOSFET power transistor, by measuring in real time the threshold voltage of the transistor VTh-

[0016] The invention relates in particular to a device for tracking or monitoring the state of health of a MOSFET power transistor comprising:

[0017] - means for providing or applying to a MOSFET power transistor a starting voltage (VGS) these means comprising at least one resistor (R3, R4), forming an external gate resistance, of at least 10 kΩ;

[0018] - means for measuring or estimating the dip in the grid voltage (VGS) which follows the Miller's plateau.

[0019] The first means can provide a MOSFET power transistor with an “ultra slow” start-up voltage (VGS).

[0020] The transistor is for example of the type based on a large gap semiconductor, such as for example with SiC or GaN technology. By "large gap" is meant an energy gap or a height of the forbidden band Eg separating the last occupied states of the valence band and the first free states of the conduction band, greater than silicon. Alternatively, it can also be a MOSFET transistor made of silicon (Si).

[0021] Thus the invention makes it possible to estimate the threshold voltage of the transistor by measuring the dip in the gate voltage (VGS) which follows the Miller plateau.

[0022] The invention therefore proposes a real-time monitoring device, which can be embedded. The integration of this type of device makes it possible to detect the warning signs of degradation and aging of MOSFETs, in particular SiC MOSFETs, thus allowing rapid intervention to avoid more serious problems.

[0023] According to one embodiment, a monitoring device according to the invention may comprise means or a stage for detecting the cancellation of the derivative of the gate voltage (VGs).

[0024] Optionally, means or a comparison stage may or may be provided to compare the value of the derivative of VGS to a comparison threshold value.

[0025] Preferably, the comparison threshold value is negative.

[0026] According to a particular embodiment, the comparison means or stage comprise(s) means forming hysteresis.

[0027] A device according to the invention may further comprise means for memorizing a value of said trough.

[0028] For example, it comprises at least one sample-and-hold device to maintain said trough value.

[0029] The means for storing a minimum value of said hollow may comprise a capacitor. They may further be associated with switch-forming means.

[0030] A device according to the invention may further comprise second means for applying a voltage to a power MOSFET transistor, these second means comprising at least one resistor of low value relative to said resistor forming an external gate resistor.

[0031] Such a device may further comprise means for controlling the first means and the second Pulse Width Modulation (PWM) means.

[0032] A device according to the invention may further comprise means of synchronization with a current sensor.

[0033] The invention also relates to a method for monitoring the health status of a power transistor, for example of the MOSFET-SiC or HEMT p-GaN or MOSFET-Si type or, more generally, of a power transistor of any other technology (providing a strong non-linearity of Cgd with the voltage Vds) or of a power transistor of the MOSFET-Si type, implementing a device as described above and in the remainder of the present application.

[0034] The invention also relates to a power converter or module comprising several power transistors and at least one device as described above and in the remainder of the present application.

[0035] The invention also relates to an aircraft comprising at least one converter or power module according to the invention. brief description of the figures

[0036] - [Fig.lA], [Fig. IC] illustrate the dependency link between Cgd and VDS> re showing the Cgd curve as a function of VDs ([Fig.lA]), and the time evolution of respectively VDS (figure IB), and VGS ([Fig. IC]) of a MOSFET - SiC transistor;

[0037] - [Fig.2A], [Fig.2B] represent the influence of the driver voltage VDD on the shape of the VGS trough ([Fig.2A]) and on VDS ([Fig.2B]);

[0038] - [Fig.3] represents a comparison of the LV waveforms between components new with healthy oxide (curve I) and stressed component with aged oxide (curve II);

[0039] - [Fig.4] schematically represents a measurement chain for monitoring analog of the hollow with derivative of VGs and direct sampling;

[0040] - [Fig.5A], [Fig.5B] represent simulation results of the evolution temporal of LVs and (dVGs / dt);

[0041] - [Fig.6A], [Fig.6B] represent the same curves as in figures 5A-5B with, furthermore, the sample-and-hold (EB) output;

[0042] - the [Fig.7A], [Fig.7Al], [Fig.7B][Fig.7Bl], [Fig.7C], [Fig.7Cl], represent a possible realization of means for automatically memorizing the hollow;

[0043] - [Fig.8] schematically represents another possible embodiment of means to memorize the hollow;

[0044] - [Fig.9] schematically represents a measurement chain for monitoring analog with automatic hollow memory;

[0045] - [Fig.lOA], [Fig.lOC] represent simulation results of the evolution time course of VGS ([Fig.lOA]) and (dVGS / dt) ([Fig.lOC]) with the waveforms of interest and the sample-and-hold switch opening and blocking signal ([Fig.lOB]);

[0046] - [Fig. 11] and [Fig. 12] respectively represent examples of embodiments of cut from the circuits of figures 4 and 9;

[0047] - [Fig.l3A], [Fig.l3B], [Fig.l4A] and [Fig.l4B] represent an application of the invention to a Pulse Width Modulation (PWM) control frame;

[0048] - [Fig.l5A], [Fig.l5B] represent an application of the invention to an inverter three-phase involving common-mode control on a line of low-side (A) and high-side (B) transistors;

[0049] - [Fig. 16] represents an application of the invention to a switching according to the invention around the zero of a charging current;

[0050] - [Fig. 17] represents an electronic gate control circuit.

[0051] - [Fig. 18] represents an example of control timing diagrams of the device of [Fig. 17];

[0052] - [Fig. 19] represents an implementation of the synchronization of a measurement according to the invention with a current sensor.

[0053] DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0054] The invention relates to a method for monitoring the health status of a power transistor, in particular based on a wide gap semiconductor, for example such as SiC or GaN, i.e. comprising an energy gap or a height of the forbidden band Eg separating the last occupied states of the valence band and the first free states of the conduction band, greater than silicon. This is for example a transistor of the SiC MOSFET type or a p-GaN HEMT (high electron mobility transistor made of gallium nitride) or a power transistor of any other technology (providing a strong non-linearity of Cgd with the voltage Vds). But the invention also applies to power transistors of the Si MOSFET type. In the following, most of the explanations are given for a SiC MOSFET type transistor.

[0055] According to the invention, such a monitoring method implements monitoring of the threshold voltage VTH thereof. This quantity is however not directly accessible. An observable which relatively faithfully transcribes the variations in VTH is the Miller plateau during a trigger switching. The amplitude of this plateau is dependent on several other parameters, as shown in equation (1) below.

[0056] [Math.l] -r -.......•- .........*.....----- -t- / (A * V

[0057] in which VP is the amplitude of the Miller plateau, ICH the load current, GFS the transconductance of the transistor, COss the internal output capacitance of the MOSFET, VDS the drain-source voltage, X the parameter translating the “short-channel” effect on the SiC MOSFET and generating an oblique plane evolution of the plateau.

[0058] In order to keep only the influence of VTH on this Miller plateau, we seek to minimize the parasitic contributions on the plateau voltage, therefore to minimize ICH (to minimize ICH / GFs) and to have a very large “dt” (to minimize dVDS / dt), f(X, VDS) being a parameter specific to the transistor on which we cannot act.

[0059] For example, a very slow switching of the transistor is carried out, the switching duration then being greater than that of the nominal switching with very high external gate resistance Rg (several kQ, for example RG=10kQ), whereas the nominal value Rgnom of external gate resistance RG for a “nominal” switching is for example approximately 10Q: the switching slowdown factor is therefore here 1000 compared to a normal or nominal switching, under low external gate resistance, therefore fast, at zero load current. The influence of the parameters which are not of interest here on the amplitude of the plateau is then minimized, and the duration of the plateau is increased to facilitate its reading (for example on an oscilloscope) and / or its extraction.

[0060] To this end, we seek, for example, that RG (external grid resistance) is at least 100 times greater than its nominal value RGNom-

[0061] In other words, we seek to control the switching of the transistor in a slow or very slow manner, by varying the value of the external gate resistance RG, that is to say the resistance applied to the gate of the transistor (while RGint designates the internal gate resistance, intrinsic to the transistor and its technology).

[0062] Thus, during the Miller plateau, the buffer does not supply more charge to the internal gate-source capacitance CGs than the internal gate-drain capacitance CGd pumps to it.

[0063] According to one embodiment, it is possible, for example, to increase the current delivered by the driver to the gate IG by the gate-drain current ICgd, which leads to the following condition (the numerical values are specific to the SiC MOSFET component used during tests (C2M0080120D)):

[0064] [Math.2] Rs » (VD0-VP) / C^dV^ / dt, Let Rg » (20-5) / lOOpF . 200V / gs

[0065] We therefore obtain: RG » 750Q; we can therefore take for example RG equal to approximately WkQ.

[0066] The switching is then slowed down by a factor of approximately 1000 compared to normal switching under a gate resistance RG of 10Q.

[0067] An example of an electronic circuit 100 for controlling the gate of a power transistor 32, for example a SiC MOSFET, is presented in [Fig. 17]. It comprises:

[0068] - on the one hand, first means (a buffer) 15 of conventional control, also named “Fast”, which can be set to high impedance via a dedicated control input 17 (“Enable Fast”). These means 15 are associated with the gate resistors RrR2 (Ri for ignition, R2 for blocking), which are low value resistors (for example typically 10Q);

[0069] - on the other hand, second means (buffer) 12, also called “Ultra-Slow”, connected, in parallel with the means 15, to the gate of the power transistor 32 to be driven. These means 15 are associated with the gate resistors R3-R4, which are greater than Ri and R2 by a factor of, for example, 1000 (R3 and R4 have a value of 10kQ in this example). The power supplies of these two means 12, 15 (VDdx and VSsx) can be adjusted independently of each other.

[0070] [Fig. 17] represents an architecture, called “multi-buffer” type, comprising the means or circuits 12, 15, mounted in parallel, for close electronic control of the gate of a power transistor 32, for example a transistor of a power converter as illustrated in figures 15A and 15B. This figure highlights the dedicated control channel (comprising the means 12 and the resistors R3 and R4) for measuring and monitoring VTH (VGSTh) for monitoring the health status of the transistor.

[0071] A device according to the invention, for example that of [Fig. 17], applies equally well to a measurement on a “high side” component (for example the transistor 42 of [Fig. 15A]), as on a “low side” component (for example the transistor 42 of [Fig. 15A]).

[0072] [Fig. 18] represents an example of control timing diagrams of the device of [Fig. 17], the “ultra-slow” mode being activated when the “fast” mode is inhibited and vice versa. A measurement according to the invention can be carried out when the “ultra-slow” mode is activated.

[0073] The inventors observed that VGS (represented in [Fig. IC]) corresponds to the hollow appearing after Miller's plateau.

[0074] This dip appears at low drain-source voltage VDS (represented in figure 1B): in the zone of high non-linearity of the internal drain-gate capacitance CGd (represented in [Fig.1A]), from an instant tb This strong variation in capacitance then generates a charge pump effect from the gate to the drain, thus causing a dip to appear on V GS through the high external gate resistance (here: 10kQ), a dip which is visible in [Fig. IC],

[0075] This dip appears at time tb corresponding to the end of the switching dVDS / dt, when CGd becomes highly non-linear. The electrical charges thus drawn from the gate to the drain discharge CGS and contribute to reducing VGS. On the other hand, the control circuit (or "gate driver") of the transistor injects charges to the gate through the external gate resistor. These two antagonistic phenomena are in competition, and the contribution made by the control circuit takes over when CGS stops varying, which allows the gate charge and therefore the switching to be resumed and continued.

[0076] Tests at reduced voltage VDd (control circuit supply voltage) were conducted. These tests show the impact of a reduced contribution of the charge supply by the control circuit on the dip phenomenon mentioned above. It appears that the minimum value of the dip tends towards the intrinsic threshold value VTh. This is explained by the fact that at the end of the plateau, at the beginning of the dip, the current ICGd drawn by CGD from the gate to the drain passes through the transistor channel, the formation of which depends on the gate bias VGS. As ICGD discharges the gate, the channel narrows (pinches off), and limits the current that can pass through the channel: this slows down the phenomenon and lengthens the duration of the dip.

[0077] This is valid, and visible at reduced VDD, because the driver injects few charges into the gate, which allows the dip voltage to approach, to touch the gate voltage VTH of the transistor at the limit of channel conduction, as illustrated in figures 2A and 2B; in these figures, the evolution of VGS ([Fig.2A]; in this figure, SMU means “source measurement unit”) and VDS ([Fig.2B]) is represented for various values of VDD, between 10 V and 20 V as indicated in these figures.

[0078] Therefore, the dip in the grid voltage appears as a reliable, new, low-noise indicator, corresponding to a VTH image. The value of this dip can be defined as the difference between the Miller plateau level and the absolute minimum value of the dip. We will place ourselves in good conditions to measure or estimate the dip in the grid voltage with, preferably:

[0079] - a slowed down priming switching, for example by about 1000 times, compared to to a conventional ignition; this can be achieved by using a grid resistor RG external 1000 times higher than the nominal case;

[0080] - a zero charging current during this priming; figures 15A to 16 illustrate implementations for monitoring the health status of a transistor within a three-phase power converter, and to enable measurement at zero load current. Figures 15A-15B illustrate simultaneous ultra-slow triggering on the 3 low-side transistors (15A) or on the 3 high-side transistors (15B) within a three-phase power inverter. Such a control strategy makes it possible to avoid the circulation of currents in the triggered transistors. [Fig. 16] illustrates the use of a current sensor 43 on one phase of a motor to synchronize the ultra-slow measurement around the cancellation of the load current;

[0081] - a reduced supply voltage of the driver 12 (VDDi in [Fig.17]), for example in less than or equal to 10V; whereas a nominal or "normal" voltage of the driver 12, for example between 15V and 20V, is higher than this reduced value. Indeed, as already explained above, at reduced supply voltage VDo, the minimum value of the dip tends towards the intrinsic threshold value of the transistor. In other words, the dip, an indicator of the state of health, then approaches VTh and therefore the physical phenomenon of charge trapping; this indicator then becomes all the more relevant. But this requires an adjustable VDd power supply, which means the use of additional components: the implementation is therefore more complex.

[0082] At nominal VDD (“20V; in this case, VDd is not reduced), the variations of this dip (represented as a function of time in [Fig.3] on which curve I represents these variations for a new transistor, with healthy oxide and curve II for a stressed transistor, with aged oxide) follow in a relative manner the variations of VTH and then also give an indication of the state of degradation of the gate oxide layer.

[0083] Analog implementations of tracking the dip on the gate voltage are proposed below.

[0084] A first implementation, with direct sampling, is based on a derivative of V GS: the amplitude of the plateau on VGs will increase over time depending on the trapping state of the oxide layer but its overall dynamics will remain unchanged, as shown in [Fig.3], which allows comparison of VGs waveforms between a new component with healthy oxide (curve I) and a stressed component with aged oxide (after 24 hours of stress at VGS = 35 V, curve II).

[0085] Cancelling the derivative of VGS therefore appears as a means of detecting the appearance of the dip. Comparing this derivative with a threshold, preferably adjustable, makes it possible to generate the command to control a blocking sampler on V GS. This method makes it possible to sample and store the value of VGS at the instant when its derivative intersects with a threshold.

[0086] A diagram of a circuit or device 10 for implementing this solution is given in [Fig.4], on which:

[0087] - means 8 (control isolator, optocoupler) isolate the orders from digital control of the rest of the electronic circuit; these means 8 provide the interface or link between the digital control commands and the electronic components of the circuit; they provide the “ultra slow” boot control signal; the control signal to activate these means is sent by digital control means, for example an FPGA;

[0088] - means 12 (or buffer) control the transistor under test 32 and make it possible to start it slowly; the gate control signal comes from the means 12, passes through the external gate resistor 12', the VGs signal which comes out of 12' contains information on the state of health of the transistor under test;

[0089] - means 34 forming an instrumentation amplifier (these means 34 allowing to copy and isolate the signal), which allow VGs to be read, reconstructed and processed via impedance matching; in fact, under such a high value of gate resistance (10kQ) the slightest gate leakage path becomes non-negligible. A simple resistive voltage divider bridge to capture VGS is therefore not feasible here due to the current leaks at low total resistance of such a divider bridge, and its sensitivity to high resistance noise;

[0090] - a stage 14 of calculation of the derivative is then applied to the image of VGS obtained in output of means 12;

[0091] - a stage 16 for comparison with a threshold makes it possible to compare the derivative with a pre-threshold determined ;

[0092] - means 18 forming a flip-flop make it possible to generate and maintain at a certain state a control edge from the result of the comparison of the threshold and the derivative.

[0093] The output of the means 18, as well as the VGS data obtained at the output of the means 12, are applied to the input of a sampler-blocker 20. The value(s) of Vtrough can then:

[0094] - be used as an index of the evolution of the aging of the transistor 32:

[0095] - and / or be digitized by an analog-to-digital converter (ADC) to be processed and then possibly stored in a digital control unit (FPGA type for example);

[0096] - be compared over time to monitor the evolution of the state of health of the transistor 32 tested.

[0097] Examples of embodiments of the various means 12-23 are given in figures 11 and 12 as well as below, in connection with these figures 11 and 12.

[0098] A simulation using “LTspice” software using ideal components (which come directly from the LTspice library provided with the software) was carried out.

[0099] The results of this simulation are illustrated in Figures 5A and 5B. An “Ultra-Slow” triggering under a very high external grid resistance RG (for example 1000 times higher than the normal or nominal resistance, which has a value generally around 10Q), R3, R4 (as already explained above) respecting the condition established beforehand (factor for example 1000 already mentioned above), for example RG = 10kQ was carried out on a test bench. The load curve of VGS (whose time evolution is represented in [Fig.5A]) is extracted from the oscilloscope in the form of a point file, then imported into the simulation software as a voltage source profile. [Fig.5B] represents the time evolution of the derivative of VGS (derivative obtained at the output of the derivative stage 14).

[0100] As seen in Figures 5A and 5B, comparing the derivative of VGS to a threshold of 0V leads to a risk of false triggering and generation of unwanted edges, particularly in the plateau zone. This is why a negative safety threshold is chosen (for example: -0.6V). It thus makes it possible to establish a safety margin with respect to the threshold of 0V, thus avoiding false triggers and obtaining clear intersections with the negative part of the derivative. This negative part corresponds to the start of the trough, in the decreasing zone of VGS.

[0101] The waveform 21 at the output of the sample-and-hold circuit 23 (EB) is shown in FIGS. 6A and 6B. Its output performs a value hold (around the trough) when it receives a control edge on its clock input.

[0102] It therefore appears that the output of the blocking sampler 23 is maintained at a voltage value close to that of the dip. This "direct" method has the advantage of relying on a reduced number of components. However, in order to obtain a measurement that is as faithful as possible, we seek to ensure that the control edge of the blocking sampler appears at the minimum of the dip. This can be achieved by adjusting the threshold and the bandwidth of the differentiator stage 14.

[0103] Another implementation, with memorization of the trough, is based on automatic memorization of the minimum value of the trough. It is represented in Figures 7A - 9.

[0104] [Fig.7A] schematically represents means 22a for memorizing the hollow. These means comprise 2 diodes 221, 223 arranged inverted and in parallel as well as a capacitor 224 for memorizing the value of the hollow.

[0105] Initially ([Fig.7A], [Fig.7Al]), the signal representative of VGS charges the capacity 224, until the end of the Miller plateau.

[0106] In a second step ([Fig.7B], [Fig.7Bl]), the voltage across the terminals of capacitor 224 decreases, which corresponds to the trough following the Miller plateau.

[0107] Finally, in a 3rd step ([Fig.7C], [Fig.7Cl]), the capacitor 224 recharges through the direct diode 221 during the rise of VGS.

[0108] In other words, the means 22a do not allow the hollow because the memory capacity 224 CMEM recharges through the direct diode 221 when VGS rises.

[0109] Therefore, as illustrated in [Fig.8], means 22 are used instead, comprising means forming a switch 226 upstream of the direct diode 221; these means 226 make it possible to dynamically open the circuit to prevent this undesirable recharging of the capacitor 224 CMEM and so that the voltage across the terminals of the latter is maintained (apart from leaks) at the value of the dip. As can be understood from [Fig.7Cl], the control of the opening of the means 226 preferably occurs before zone 3 and as long as VGs > Vdip-

[0110] As indicated in [Fig.9], the order to open the switch will be generated by flip-flop 18 of the trigger chain. [Fig.8] represents the contents of the means 22 forming the storage block of the hollow of [Fig.9]. The other elements of this [Fig.9] have already been described above, the reference 32 again designating the transistor tested.

[0111] In this configuration, the input of the sample-and-hold circuit 23 (EB) is now the voltage of the memory capacity CMem which corresponds to the minimum value of the dip. In comparison with the "direct" solution described above in connection with [Fig.4], an analog pre-processing stage is added (for dip storage) and makes it possible to make the dip value available at the input of the sample-and-hold circuit 23. Once the dip value has been stored by CMem, the sample-and-hold circuit 23 receives a blocking edge and their output is maintained at a value as close as possible to the true dip value.

[0112] The diodes 221, 223 used in the dip storage stage are preferably diodes compensated by AOP (operational amplifier) to overcome their threshold voltage.

[0113] The simulation results of Figures 10A - 10C show that the CMEM voltage correctly copies VGS and maintains itself at the value of the dip. As seen in [Fig.lOB], the order to open the switch (to prevent VMEM from rising) is sent at the start of the dip. A delay (see [Fig.lOA]) can be introduced (analogously, for example with an RC-type delay circuit, or digitally (flip-flops and digital control unit) at the level of the digital control unit) on the same signal which is sent to the blocking port of the sample-and-hold circuit 23 so that VMEM has time to decrease to VCreux-

[0114] [Fig. 11] represents a detailed analog implementation of a circuit 10 for analog tracking of the dip on VGS. [Fig. 12] represents a detailed analog implementation of a circuit 20 for analog tracking of the dip on VGS, with storage of the dip value.

[0115] In these figures 11 and 12:

[0116] - the means 18 forming a flip-flop make it possible to generate the control front of the sample-and-hold circuit 23 ([Fig. 11]), the control order of the analog switch of the dip storage block 22 ([Fig. 12]) and the control edge of the “Sample_Ready” signal (figures 11, 12) through an isolator 27 indicating to a digital control device (for example an FPGA) that it can start the acquisition of the dip value extracted at the output of the chain;

[0117] - the dip voltage extraction chains are illustrated with a buffer 12 of 32 power MOSFET gate drive with high gate resistance;

[0118] - a current source 25 (“2mA), controlled and regulated, makes it possible to produce a priming, in order to be able to precisely measure CGD, which is proportional to the duration of the plateau;

[0119] - the state of the means 18 forming a flip-flop is initialized from the signal of the means 8 Ultra-Slow priming;

[0120] - the derivative comparator stage 16 is provided with hysteresis means to avoid possible rebounds;

[0121] - reference 32 designates a transistor under test;

[0122] - reference 34 designates an amplifier arranged at the input of the means 14 forming comparator.

[0123] An implementation of the measurement of the dip voltage according to the invention within a Pulse Width Modulation (PWM) control frame is described below, in connection with Figures 13A-14B.

[0124] At no load, with zero charging current, an “Ultra-Slow” measurement (according to the invention) of the dip voltage under high gate resistance can be carried out punctually within a PWM frame during active switching of high duty cycle ignition to allow sufficient time for the slowed charging of VGs and the dip measurement. The example of an Ultra-Slow measurement on a high-side component is given in figures 13A.

[0125] To carry out a measurement on a low-side component ([Fig.l3B]), we wait for a half-period of modulation so that the duty cycle of the “low-side” is maximum.

[0126] In order to minimize the measurement duration and limit the impact on the PWM control frame, a measurement with switched gate resistors is presented in Figures 14A-14B. With this method, only the plateau and trough area of interest is slowed down and elongated to facilitate measurement and extraction, and also to increase the signal-to-noise ratio of this area. Such “Ultra-Slow” switching (according to the invention), called condensed, makes it possible to carry out a measurement of the trough within a switching period (for example, if the switching frequency fDEC = 20kHz, then the period TDEC = 50ps, the measurement being able to be made at most in 20ps, see Figures 6A-7C).

[0127] Figures 15A, 15B and 16, discussed below, illustrate embodiments of health monitoring within a three-phase power converter, allowing measurement at zero load current.

[0128] In connection with Figures 15A - 15B, an application of a measurement according to the invention to common mode control on a three-phase inverter (at zero speed) is presented.

[0129] A boot switching according to the invention (called “Ultra-Slow”) is carried out simultaneously on the 3 “low-side” MOSFETs 422, 424, 426 ([Fig.l5A]) then on the 3 “high-side” MOSFETs 42i, 423, 425 ([Fig.l5B]). This makes it possible to carry out the boot switching without load current which would disturb the measurement of the dip. This also makes it possible to obtain information on the state of health of 3 MOSFETs at the same time.

[0130] More precisely, when a motor 40 is connected to an inverter 42 (comprising the transistors 42r426), the cancellation of the current in the phases of the motor can be produced so as to return to the case explained above in connection with figures 13A - 14B.

[0131] For this, a homopolar (or common mode) control is applied to the transistors 42r426 so as to cancel all the compound voltages at the terminals of the motor 40 and to tend towards a zero current in the phases. The motor has previously been set to zero speed. As soon as the currents are canceled, a procedure identical or similar to that explained above in connection with figures 13A - 14B can be implemented; a device such as described above is then applied, for example in connection with figures 11 or 12, to each of the transistors 42r426,

[0132] [Fig. 16] shows an application of monitoring according to the invention to “Ultra-Slow” switching around the load current zero: in the case of a motor 40 running and in the presence of currents in the phases, it is possible to operate the “Ultra-Slow” switching as described above by synchronizing this procedure with the current crossing through zero: a measurement according to the invention (called “ultra-Slow”) is synchronized with a current sensor 43. [Fig. 19] represents an implementation of the synchronization of a measurement according to the invention, as described above, with such a current sensor 43. The signal coming from the latter is compared to a threshold by comparison means 45, then a control edge is generated by means 47 and sent to digital control means 49. The other components 8, 12 of this figure have already been described above, as well as the measuring chain 10 ([Fig. 11]) or 20 ([Fig. 12]).Reference 32 still designates the transistor under test.

Claims

Claims

1. Device for monitoring the health status of a power MOSFET transistor (32) comprising: - first means (8, 12) for applying a starting voltage (VGS) to a power MOSFET transistor, these means (8, 12) comprising at least one resistor (R3, R4), forming an external gate resistance, of at least 10 kΩ; - means (12-22) for measuring the dip in the gate voltage (VGS) which follows the Miller plateau.

2. Device according to claim 1, comprising a stage (14) for detecting the cancellation of the derivative of the gate voltage (VGS).

3. Device according to claim 2, comprising a comparison stage (16), for comparing the value of the derivative of VGS with a comparison threshold value.

4. Device according to claim 3, the comparison threshold value being negative.

5. Device according to one of claims 3 or 4, the comparison stage (16) comprising means (161) forming hysteresis.

6. Device according to one of claims 1 to 5, comprising means (23, 22, 22a) for storing a value of said hollow.

7. Device according to claim 6, comprising at least one sampler-blocker (23) for maintaining said value of the trough.

8. Device according to one of claims 6 or 7, the means for storing a minimum value of said hollow comprising a capacitor (224).

9. Device according to claim 8, the means for memorizing a minimum value of said hollow comprising means (226) forming a switch.

10. Device according to one of claims 1 to 9, further comprising second means (15) for applying a voltage to a power MOSFET transistor (32), these means comprising at least one resistor (Ri, R2) of low value relative to said resistor forming an external gate resistor (R3, RJ.

11. Device according to claim 10, further comprising means for controlling the first means (8, 12) and the second means (15) with Pulse Width Modulation (PWM).

12. Device according to one of claims 1 to 9, further comprising means (45, 47, 49) for synchronization with a current sensor (43).

13. Method for monitoring the health status of a power transistor, for example of the MOSFET-SiC or HEMT p-GaN type or of a power transistor of the MOSFET-Si type, implementing a device according to one of the preceding claims.

14. Power converter or module comprising several power transistors (42r426) and at least one device according to one of claims 1 to 12 coupled to at least one of the transistors.

15. Aircraft comprising at least one power converter or module according to claim 14.

Images