METHOD FOR INITIALIZING A CHARGE PUMP AND CORRESPONDING INTEGRATED CIRCUIT

Abstract

Integrated circuit comprising a charge pump (CHRG_PMP) comprising a Pelliconi-type transfer stage (CHRG_PMP_STG) capable of carrying out a cyclic charge transfer controlled by control signals, in order to generate an output voltage (Vout) by raising an input voltage (Vin), and at least one control circuit (DYN_SHFT1, DYN_SHFT2) configured to generate said respective control signals (VN0, VN1, VP0, VP1), in which said control circuit (DYN_SHFT1, DYN_SHFT2) is further configured, during an initialization phase before said generation of the output voltage (Vout), to force said respective control signals to at least one respective initialization voltage (V_INIT, Vout) suitable for starting said generation of the output voltage (Vout). Figure for abstract: Fig 2

Description

Title of the invention: METHOD FOR INITIALIZING A CHARGE PUMP AND COR INTEGRATED CIRCUIT RESPONDENT

[0001] Embodiments and implementations relate to initializing a charge pump.

[0002] A charge pump is typically used in low-power devices such as certain microcontrollers or connected objects which are powered by relatively low supply voltages (for example 1 volt). More particularly, the charge pump makes it possible, in operation, to generate from these supply voltages higher supply voltages (for example 2 volts) for the internal operation of these devices.

[0003] Proper operation of the charge pump is generally guaranteed when the internal voltages of the charge pump are initialized. However, initialization of the internal voltages of the charge pump can be relatively long, particularly for charge pump architectures whose internal voltages are generated on capacitive nodes.

[0004] Indeed, these capacitive nodes can be in a so-called “high impedance” state during initialization, that is to say a state in which the voltages generated by these nodes are not controlled and therefore have indeterminate values which can depend on parameters such as transistor current leaks or capacitive couplings.

[0005] These internal voltage values can lead to the charge pump being stuck in a low efficiency state that prevents it from operating. The initialization is therefore extended to allow the charge pump to exit this low efficiency state. For example, the initialization time for such charge pump architectures can be greater than 10 ps.

[0006] It may be entirely possible not to initialize the internal voltages of the charge pump but the start-up period (which is known as the "start-up phase" in English) of the charge pump risks being extended, in particular depending on the size of the components of the charge pump or the rise times of the supply voltages and therefore does not allow for a robust charge pump.

[0007] Another possibility to avoid an excessively long initialization time is to use high-voltage transistors capable of supporting the supply voltage provided by the charge pump and making it possible to accelerate the initialization of the internal voltages.

[0008] However, high-voltage transistors are bulky, degrade efficiency energy of the charge pump due to the associated parasitic capacitances, and are controlled by high voltages whose generation would require a dedicated booster stage, typically a charge pump, which would amount to moving the problem without solving it.

[0009] Thus, there is a need to propose solutions making it possible to accelerate the initialization of the charge pump without degrading the performance and robustness of the charge pump, advantageously by means of low voltage transistors.

[0010] According to one aspect, there is provided an integrated circuit comprising a charge pump comprising a transfer stage capable of carrying out a cyclic charge transfer and controlled by control signals, in order to generate an output voltage by raising an input voltage, and at least one control circuit configured to generate respective control signals, in which said control circuit is further configured, during an initialization phase before said generation of the output voltage, to force said respective control signals to a respective initialization voltage adapted to a start of said generation of the output voltage.

[0011] For example, the circuit may provide a first control circuit at the input of the charge pump and, independently or in combination, a second control circuit at the output of the charge pump.

[0012] The control circuit makes it possible to impose in a controlled manner the voltages of the control signals during the initialization phase in order to prevent uncontrolled voltages, for example those induced by capacitive coupling when the charge pump is deactivated, from causing the charge pump to be blocked in the low efficiency state.

[0013] Consequently, the charge pump returns to operating mode very quickly after an initialization phase, because the voltages of the control signals are imposed so as not to enter the low efficiency state generating a latency at start-up to exit it.

[0014] According to one embodiment, the transfer stage is configured, in a manner controlled by said control signals, to cyclically switch a capacitive element into a state capable of being charged by the input voltage, and into a state capable of transferring its charge to the output voltage.

[0015] Such a transfer stage (of the Pelliconi type and known to those skilled in the art) allows the charge pump to generate an output voltage greater than the input voltage, for example an increase in the input voltage by a factor of 2.

[0016] According to one embodiment, a first control circuit is connected to an input of the charge pump and is configured to generate first control signals from the input voltage, the first control circuit being configured to generate said respective initialization voltage, called input initialization voltage, during the initialization phase, the input initialization voltage being less than or equal to the input voltage.

[0017] The first control circuit has the advantage of preventing a mechanism for blocking the initialization of the control signals, which can occur in particular when the initial voltage of at least one of the control signals has a positive and high value compared to the input voltage.

[0018] Thus, by fixing the voltage of the control signals to the ground voltage during the initialization phase, one guards against the conditions of the blocking mechanism mentioned above.

[0019] According to one embodiment, the first control circuit comprises first switches coupling the first control signals with the input of the charge pump; and further comprises an initialization circuit comprising second switches capable of coupling said first control signals with an input initialization voltage in a manner controlled by the input voltage.

[0020] Such an initialization circuit thus makes it possible to impose the input initialization voltage, for example ground, on the first control signals. The second switches, which may be NMOS transistors for example, are consequently subjected to the input voltage on the one hand and the input initialization voltage on the other hand, and may thus be “low voltage” transistors of the same type as the first switches.

[0021] According to one embodiment, a second control circuit is connected to an output of the charge pump and is configured to generate second control signals from the output voltage, the output stage of the control circuit being configured to generate said respective initialization voltage, called output initialization voltage, the output initialization voltage being greater than or equal to the output voltage.

[0022] In a similar manner to the first control circuit, the second control circuit makes it possible to prevent the blocking mechanism from initializing the control signals, in particular those used to control the switching of the capacitive element into a state capable of transferring its charge to the output voltage.

[0023] However, the initial voltage of these control signals is fixed at the output voltage to avoid triggering the blocking mechanism which can occur when at least one of the two control signals has an initial voltage value which is, for example, negative and more generally lower than the output voltage.

[0024] Thus, by setting the voltage of the control signals to a voltage greater than or equal to the output voltage during the initialization phase, the control signals are allowed to reach a voltage suitable for starting the pump more quickly. charging without triggering a locking mechanism.

[0025] According to one embodiment, the second control circuit comprises first switches coupling the second control signals with the output of the charge pump; and further comprises an initialization circuit comprising second switches configured to couple said second control signals to the output of the charge pump during the initialization phase, and not outside the initialization phase.

[0026] According to one embodiment, the second switches, which may be PMOS transistors for example, are consequently subjected to an initialization control voltage which may have the output voltage or an initialization control voltage, and to the output voltage on the other hand.

[0027] The initialization control voltage is provided in particular for controlling second switches under “low voltage” conditions, the second switches thus being able to be produced by transistors of the low voltage type, that is to say of the same type as the first switches.

[0028] According to one embodiment, the second control circuit comprises a timing circuit configured to generate the initialization control voltage controlling a coupling of the second control signals to the output of the charge pump during a discharge period of the charge pump after a switching off of the generation of the output voltage.

[0029] The timing circuit makes it possible to maintain the initialization control voltage at the output voltage to avoid generating a voltage difference between terminals of the second switches which damages these second switches. For example, when the second switches are PMOS type transistors, this voltage difference applied between the gate and the source of these PMOS type transistors may be greater than the maximum voltage tolerated by these transistors.

[0030] At the end of the discharge period of the charge pump, the initialization control voltage can have the ground voltage without risk of damaging the second switches since the difference between the initialization control voltage and the output voltage is less than the maximum voltage tolerated by the second switches.

[0031] According to another aspect, there is proposed a method for initializing a charge pump comprising a transfer stage capable of carrying out a cyclic charge transfer and controlled by control signals in order to generate an output voltage by raising an input voltage, the method comprising an initialization phase, before a start of said generation of the output voltage, forcing respective control signals to at least one respective initialization voltage adapted to the start of said generation of the output voltage.

[0032] According to one embodiment, the cyclic charge transfer comprises cyclic switchings, controlled by the control signals, of a capacitive element into a state capable of being charged by the input voltage, and into a state capable of transferring its charge to the output voltage. The sequencing of the control signals of such a pumping cell (of the Pelliconi type) is known to those skilled in the art.

[0033] According to one embodiment, first control signals generated from the input voltage are forced to the respective initialization voltage, called the input initialization voltage, during the initialization phase, the input initialization voltage being less than or equal to the input voltage.

[0034] According to one embodiment, the first control signals are coupled to the input of the charge pump, the initialization phase forcing the first control signals to the input initialization voltage by coupling the first control signals with the input initialization voltage by means of the switches controlled by the input voltage.

[0035] According to one embodiment, second control signals generated from the output voltage are forced to the respective initialization voltage, called output initialization voltage, during the initialization phase, the output initialization voltage being greater than or equal to the output voltage.

[0036] According to one embodiment, the second control signals are coupled to the output of the charge pump, the second control signals being forced to the output initialization voltage, by coupling the second control signals with the output of the charge pump by second switches during the initialization phase, and not outside the initialization phase.

[0037] According to one embodiment, the second switches are controlled by an initialization control voltage which may have the output voltage or a ground voltage.

[0038] According to one embodiment, the control signals are coupled to the output of the charge pump during a discharge period of the charge pump after a switch-off of the generation of the output voltage.

[0039] Other advantages and characteristics of the invention will appear on examining the detailed description of the embodiment and implementation, which is in no way limiting, and the appended drawings in which:

[0040] [Fig.l] ;

[0041] [Fig.2] ;

[0042] [Fig.3] ;

[0043] [Fig.4] ; and

[0044] [Fig.5] schematically illustrate modes of implementation and embodiment of the invention.

[0045] [Fig.l] schematically illustrates an integrated circuit IC according to an embodiment of the invention. The integrated circuit IC comprises a charge pump CHRG_PMP.

[0046] The charge pump CHRG_PMP comprises a transfer stage CHRG_PMP_STG capable of carrying out a cyclic charge transfer and controlled by control signals VNO, VN1, VPO, VP1, VCO, VCL. The control signals more particularly comprise first control signals VNO and VN1 and second control signals VPO and VPL.

[0047] This type of transfer stage CHRG_PMP_STG, of Pelliconi type, is known to those skilled in the art. It makes it possible to generate an output voltage Vout, for example 2V, by raising an input voltage Vin, for example IV.

[0048] The transfer stage CHRG_PMP_STG is configured to cyclically switch a capacitive element such as a capacitor C0 and a capacitor C1, into a state capable of being charged by the input voltage Vin, and into a state capable of transferring its charge to the output voltage Vout. The cyclic switching of the capacitive element C0 controlled by said control signals VNO, VN1, VPO, VP1, VCO, VCL

[0049] The sequencing of said control signals VNO, VN1, VPO, VP1, VCO, VC1 is known to those skilled in the art and are given here by way of example and for the sake of understanding.

[0050] The first control signals VNO and VN1 control the switching of the transistors N0 and NI so that the capacitor C0 or Cl is connected to the input of the charge pump and is charged by the input voltage Vin. The signals VCO or VC1 are then for example generated at a ground voltage so as to obtain a potential difference on the capacitive elements C0 or Cl equal to the input voltage Vin.

[0051] The second control signals VPO and VP1 control the switching of the transistors PO and PI so that the capacitor C0 or Cl is connected to the output of the charge pump and transfers its charge to the output voltage Vout. The signals VCO or VC1 are then, for example, generated at the input voltage Vin.

[0052] The control signals VNO, VN1, VPO and VP1 typically have an operating voltage allowing the switching of the transistors N0, NI, PO and PI, for example a voltage equal to twice the input voltage Vin, for example 2V, during operation of the charge pump, after an initialization phase.

[0053] The initialization phase represents the phase, before the start of the charge pump, during which the control signals VNO, VN1, VPO and VP1 are not yet stabilized at their useful operating values, called “setpoint values”, starting from a substantially floating state (circuit stopped).

[0054] In particular, the start of the charge pump corresponds to a start of the generation of the output voltage Vont, typically initialized to the input voltage Vin.

[0055] The charge pump CHRG_PMP comprises a first control circuit DYN_SHFT1 connected to the input of the charge pump and a second control circuit DYN_SHFT2 connected to the output of the charge pump.

[0056] The first control circuit DYN_SHFT1 is configured to generate the first control signals VNO and VN1 from the input voltage Vin, and first timing signals VCN2, VCN3.

[0057] The second control circuit DYN_SHFT2 is configured to generate second control signals VP0 and VP1 from the output voltage Vout, and second timing signals VCP2, VCP3.

[0058] The first control circuit DYN_SHFT1 is configured to force the control signals VNO, VN1 to an input initialization voltage V_INIT and the second control circuit DYN_SHFT2 is configured to force the control signals VP0 and VP1 to an output initialization voltage. The input initialization voltage and the output initialization voltage are adapted to start the generation of the output voltage Vout, in the initialization phase.

[0059] The control signals then have, during the initialization phase preceding the start of the charge pump, initialization voltage values making it possible to avoid the triggering of blocking conditions of structures used for the generation of the control signals.

[0060] The control signals VNO and VN1 are therefore initialized at the input initialization voltage, which is less than or equal to the input voltage Vin (for example the ground voltage), and the control signals VP0 and VP1 are therefore initialized at the output initialization voltage which is greater than or equal to the output voltage Vout (for example Vout).

[0061] [Fig.2] schematically illustrates an example of a first control circuit DYN_SHFT1 as previously described in relation to [Fig.l].

[0062] The first control circuit DYN_SHFT1 is configured to generate the input initialization voltage V_INIT at a voltage less than or equal to the input voltage Vin during the initialization phase.

[0063] However, the first control circuit DYN_SHFT1 may find itself in a blocking state extending the duration of the initialization phase, if the starting conditions of the “floating levels” of the control signals VNO, VN1 are positive relative to the input voltage Vin.

[0064] Thus, by fixing the initial voltage of the control signals to the ground voltage, the risk of this potential blocking state is avoided.

[0065] The first control circuit DYN_SHFT1 comprises first switches N2 and N3. The first switches N2 and N3 couple the first control signals VNO and VN1 with the charge pump input. The first switches N2 and N3 are “low voltage” NMOS type transistors, i.e. transistors operating at relatively low voltage ranges, of the order of a volt for example.

[0066] In particular, the first switches N2 and N3 and the nodes of the control signals VNO and VN1, which can each be coupled to capacitive elements CN2 and CN3, form a dynamic voltage booster structure (“level shifter” in English) whose design is known to those skilled in the art. This skilled person will know how to size the characteristics of the transistors N2 and N3, of the capacitive elements CN2 and CN3, and will know how to generate first timing signals VCN2, VCN3 so as to ensure the operation of the voltage booster.

[0067] The first control circuit DYN_SHFT1 further comprises an initialization circuit comprising second switches N2_INIT and N3_INIT capable of coupling the first control signals VNO and VN1 with the input initialization voltage V_INIT in a manner controlled by the input voltage Vin.

[0068] The second switches N2_INIT and N3_INIT are preferably “low voltage” NMOS type transistors which have characteristics similar to the transistors N2 and N3. The input voltage Vin supplied to the charge pump CHRG_PMP advantageously makes it possible to control the switching of the transistors N2_INIT and N3_INIT, for example by being applied to their respective gates.

[0069] Such an initialization circuit makes it possible to discharge the “floating levels” of the nodes of the control signals VNO and VN1, for example when these nodes have a charge induced by the capacitive coupling or the leakage current of the transistors N2 and N3. Consequently, the first control signals VNO and VN1 are forced to a voltage less than or equal to the input voltage Vin, for example to the ground voltage, during the initialization phase.

[0070] At the end of the initialization phase, the input initialization voltage V_INIT can be chosen so as to switch the transistors N2_INIT and N3_INIT into a blocked state (open switch), for example by maintaining the input initialization voltage V_INIT at the input voltage Vin.

[0071] Therefore, the initialization circuit does not interfere with the operation of the charge pump CHRG_PMP after it has started.

[0072] [Fig.3] schematically illustrates an example of a second control circuit DYN_SHFT2 as previously described in relation to [Fig.l].

[0073] The second control circuit DYN_SHFT2 is configured to force the second control signals VP0 and VP1 to an output initialization voltage greater than or equal to the output voltage Vout during the initialization phase so as to avoid a blocking state during the start-up of the charge pump.

[0074] The second control circuit DYN_SHFT2 comprises first switches P2 and P3. The first switches P2 and P3 couple second control signals VPO and VP1 with the input of the charge pump. The first switches P2 and P3 are “low voltage” NMOS type transistors.

[0075] In particular, the first switches P2 and P3 and the nodes of the control signals VPO and VP1, which can each be coupled to capacitive elements CP2 and CP3, form a dynamic voltage booster structure whose design is known to those skilled in the art, who will be able to size the characteristics of the transistors P2 and P3, of the capacitive elements CP2 and CP3 connected to the nodes of the signals VPO and VP1, and will be able to generate second timing signals VCP2, VCP3 in order to generate the second control signals VPO and VP1.

[0076] The second control circuit DYN_SHFT2 further comprises an initialization circuit comprising second switches P2_INIT and P3_INIT capable of coupling said second control signals VPO and VP1 to the output of the charge pump during the initialization phase.

[0077] The second switches P2_INIT and P3_INIT are preferably “low voltage” PMOS type transistors which have the same dimensions as the transistors P2 and P3.

[0078] Such an initialization circuit makes it possible to charge or discharge the “floating levels” on the nodes of the signals VPO and VP1 at a voltage greater than or equal to the output voltage Vout of the charge pump, which may initially have a charge induced by the capacitive coupling or the leakage current of the transistors P2 and P3 for example, during the initialization phase.

[0079] At the end of the initialization phase, the control signals VPO and VP1 are no longer coupled to the output of the charge pump by the second switches P2_INIT and P3_INIT. Therefore, the initialization circuit does not interfere with the operation of the charge pump CHRG_PMP after its start-up.

[0080] In this regard, the second switches P2_INIT and P3_INIT are controlled by an initialization control voltage V_CLP. More particularly, the initialization control voltage V_CLP may have the ground voltage during the initialization phase, so that the transistors P2_INIT and P3_INIT are in the on state. The initialization control voltage V_CLP may have the output voltage Vout outside the initialization phase so that the transistors P2_INIT and P3_INIT are in the off state.

[0081] The initialization control voltage V_CLP (=ground voltage or =Vout) is particularly adapted to the voltage ranges supported by technology transistors “low voltage” since the potential differences at their terminals do not exceed Vout-Vin.

[0082] Furthermore, the second control circuit DYN_SHFT2 can advantageously comprise a timing circuit configured to generate the initialization control voltage V_CLP.

[0083] [Fig.4] schematically illustrates an example of a TMP timing circuit of the second control circuit DYN_SHFT2.

[0084] The initialization control voltage V_CLP generated by the control circuit TMP controls a coupling of the second control signals VP0 and VP1 to the output during a discharge period of the charge pump after a switching off of the generation of the output voltage Vout.

[0085] The timing circuit TMP comprises a delay cell DLY_CELL, better known by the English term "delay cell", and a logic gate LOG of the "OR" type configured together to generate a signal V_ENB_DLY having a time offset with a control signal V_ENB when the generation of the output voltage Vout is switched off. The cell DLY_CELL can be designed in a conventional manner, for example from an RC filter circuit or a chain of inverters, and advantageously configured so that the time offset of the signal V_ENB_DLY is at least equal to the discharge period of the charge pump CHRG_PMP.

[0086] A discharge period is understood to mean a time interval sufficient for the difference between the output voltage Vout and the ground voltage applied to the transistors P2_INIT and P3_INIT not to present a risk.

[0087] The timing circuit TMP also comprises a voltage level adapter circuit LVL_SHFT, usually referred to as a “level shifter”, and of any structure provided that it allows static operation of the voltage level adaptation. Such a circuit LVL_SHFT is in particular powered by the output voltage Vout and the ground voltage and is configured to generate, from the voltage V_ENB_DLY, the initialization control voltage V_CLP so that the voltage V_CLP has the output voltage Vout during the discharge period of the charge pump and has the ground voltage after this period.

[0088] Furthermore, the timing circuit TMP may advantageously comprise a third switch N_CLP0 configured to force the initialization control voltage V_CLP to the output voltage Vout at the end of the discharge period of the charge pump. Such a switch N_CLP0 makes it possible to overcome a possible lack of control of the LVL_SHFT circuit when the output voltage Vout is close to 0V (then not allowing correct operation of the LVL_SHFT circuit) and to ensure that the initialization control voltage V_CLP is maintained at the input voltage Vin when the charge pump CHRG_PMP is switched off.

[0089] [Fig.5] illustrates an example of a method for initializing the charge pump CHRG_PMP as described previously in relation to Figures 1 to 4.

[0090] The method comprises steps 100 to 103 of an initialization phase, before starting said generation of the output voltage Vout, forcing the control signals VN0, VN1 to the input initialization voltage V_INIT and the control signals VP0 and VP1 to the output initialization voltage. The input initialization voltage and the output initialization voltage are adapted to the start of the generation of the output voltage Vout.

[0091] The method comprises a step 101 of generating the first control signals VN0 and VN1 by the first control circuit DYN_SHFT1 during which the first control signals VN0 and VN1 are forced to the input initialization voltage V_INIT which is less than or equal to the input voltage Vin, for example the ground voltage.

[0092] Step 101 comprises coupling the first control signals VN0 and VN1 with the input initialization voltage V_INIT by means of the switches N2_INIT and N3_INIT controlled by the input voltage Vin.

[0093] The method comprises a step 102 of generating the second control signals VP0 and VP1 by the second control circuit DYN_SHFT2 during which the second control signals VP0 and VP1 are forced to the output initialization voltage which is greater than or equal to the output voltage Vout.

[0094] Step 102 comprises coupling the second control signals VP0, VP1 with the output of the charge pump Vout by the second switches P2_INIT, P3_INIT during the initialization phase so that the second control signals VP0 and VP1 are forced to the output voltage Vout.

[0095] The method comprises a step 103 of generating the initialization control voltage V_CLP capable of controlling the second switches P2_INIT and P3_INIT. The initialization control voltage V_CLP may have the ground voltage during the initialization phase.

[0096] The method comprises a step 104 of starting the charge pump CHRG_PMP which notably comprises the cyclic charge transfer carried out by the transfer stage CHRG_PMP_STG in order to generate the output voltage Vout by raising the input voltage Vin.

[0097] The charge transfer comprises cyclic switchings, controlled by the control signals VN0, VN1, VP0, VP1, VC1, VC0, of the capacitive element C0, Cl in a state capable of being charged by the input voltage Vin, and in a state capable of transferring its charge to the output voltage Vout.

[0098] The method also comprises a step 105 of coupling the control signals VP0 and VP1 to the output of the charge pump during a period of discharge of the charge pump after a shutdown of the output voltage generation Vont.

Claims

Claims

1. Integrated circuit comprising a charge pump (CHRG_PMP) comprising a transfer stage (CHRG_PMP_STG) capable of carrying out a cyclic charge transfer and controlled by control signals, in order to generate an output voltage (Vout) by raising an input voltage (Vin), and at least one control circuit (DYN_SHFT1, DYN_SHFT2) configured to generate respective control signals (VNO, VN1, VPO, VP1), in which said control circuit (DYN_SHFT1, DYN_SHFT2) is further configured, during an initialization phase before said generation of the output voltage (Vout), to force said respective control signals to at least one respective initialization voltage (V_INIT, Vout) suitable for starting said generation of the output voltage (Vout).

2. Integrated circuit according to claim 1, in which the transfer stage (CHRG_PMP_STG) is configured, in a manner controlled by said control signals (VNO, VN1, VPO, VP1, VCO, VC1), to cyclically switch a capacitive element (CO, Cl) into a state capable of being charged by the input voltage (Vin), and into a state capable of transferring its charge to the output voltage (Vout).

3. Integrated circuit according to one of claims 1 or 2, in which a first control circuit (DYN_SHFT1) is connected to an input of the charge pump and is configured to generate first control signals (VNO, VN1) from the input voltage (Vin), the first control circuit (DYN_SHFT1) being configured to generate said respective initialization voltage (V_INIT), called input initialization voltage, during the initialization phase, said input initialization voltage (V_INIT) being less than or equal to the input voltage (Vin).

4. An integrated circuit according to claim 3, wherein the first control circuit (DYN_SHFT1) comprises first switches (N2, N3) coupling the first control signals (VNO, VN1) with the input of the charge pump; and further comprises an initialization circuit comprising second switches (N2_INIT, N3_INIT) adapted to couple said first control signals (VNO, VN1) with the input initialization voltage (V_INIT) in a manner controlled by the input voltage (Vin).

5. Integrated circuit according to one of claims 1 to 4, in which a second control circuit (DYN_SHFT2) is connected to an output of the charge pump and is configured to generate second control signals (VPO, VP1) from the output voltage (Vout), the output stage of the control circuit (DYN_SHFT2) being configured to generate said respective initialization voltage, called output initialization voltage, the output initialization voltage greater than or equal to the output voltage (Vout).

6. An integrated circuit according to claim 5, wherein the second control circuit (DYN_SHFT2) comprises first switches (P2, P3) coupling the second control signals (VPO, VP1) with the output of the charge pump; and further comprises an initialization circuit comprising second switches (P2_INIT, P3_INIT) configured to couple said second control signals (VPO, VP1) to the output of the charge pump during the initialization phase, and not outside the initialization phase.

7. Integrated circuit according to claim 6, wherein the second switches (P2_INIT, P3_INIT) of the second control circuit (DYN_SHFT2) are controlled by an initialization control voltage (V_CLP) which may have the output voltage (Vout) or a ground voltage.

8. Integrated circuit according to one of claims 5 to 7, in which the second control circuit (DYN_SHFT2) comprises a timing circuit (TMP) configured to generate the initialization control voltage (V_CLP) controlling a coupling of the second control signals (VPO, VP1) to the output of the charge pump during a discharge period of the charge pump after a switching off of the generation of the output voltage (Vout).

9. Method for initializing a charge pump (CHRG_PMP) comprising a transfer stage (CHRG_PMP_STG) capable of performing a cyclic charge transfer and controlled by control signals (VNO, VN1, VPO, VP1, VCO, VC1) in order to generate an output voltage (Vout) by raising an input voltage (Vin), the method comprising an initialization phase, before starting said generation of the output voltage (Vout), forcing respective control signals to at least one respective initialization voltage (V_INIT, Vout) adapted to starting said generation of the output voltage (Vout).

10. The method of claim 9, wherein the charge transfer cyclic includes cyclic switching, controlled by the control signals (VNO, VN1, VPO, VP1, VCO, VC1), of a capacitive element (CO, Cl) in a state capable of being charged by the input voltage (Vin), and in a state capable of transferring its charge to the output voltage (Vout).

11. Method according to one of claims 9 or 10, wherein first control signals (VNO, VN1) generated from the input voltage (Vin), are forced to the respective initialization voltage, called input initialization voltage (V_INIT), during the initialization phase, the input initialization voltage (V_INIT) being less than or equal to the input voltage (Vin).

12. The method of claim 11, wherein the first control signals (VNO, VN1) are coupled to the input of the charge pump, the initialization phase forcing the first control signals (VNO, VN1) to the input initialization voltage (V_INIT) by coupling the first control signals (VNO, VN1) to the input initialization voltage (V_INIT) by means of the switches (N2_INIT, N3_INIT) controlled by the input voltage (Vin).

13. Method according to one of claims 9 to 12, in which second control signals (VPO, VP1) generated from the output voltage (Vout), are forced to said respective initialization voltage, called output initialization voltage, during the initialization phase, the output initialization voltage being greater than or equal to the output voltage (Vout).

14. The method of claim 13, wherein the second control signals (VPO, VP1) are coupled to the output of the charge pump, the second control signals (VPO, VP1) being forced to the output initialization voltage (Vout), by coupling the second control signals (VPO, VP1) with the output of the charge pump (Vout) by second switches (P2_INIT, P3_INIT) during the initialization phase, and not outside the initialization phase.

15. The method of claim 14, wherein the second switches (P2_INIT, P3_INIT) are controlled by an initialization control voltage (V_CLP) which may have the output voltage (Vout) or a ground voltage.

16. Method according to one of claims 13 to 15, wherein the control signals (VPO, VP1) are coupled to the output of the charge pump during a discharge period of the charge pump after a switching off the output voltage generation (Vont).

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