Manufacturing process of purified 28Si silicon semiconductor device

Abstract

A method of manufacturing a semiconductor device, the method comprising, starting from an initial silicon-on-insulator, SOI, structure comprising a silicon substrate (2), a buried oxide layer (4), BOX, and a first upper layer (6) of silicon on the buried oxide layer (4), epitaxially forming a first epitaxial layer (8) of silicon of isotope 28Si on the first upper layer (6), homogenization annealing by which the first epitaxial layer (8) of silicon of isotope 28Si and the first upper layer (6) of silicon then form a second upper layer with a lower concentration of the isotope 29Si than initially, and thinning the second upper layer. Figure 3

Description

Title of the invention: Method for manufacturing a silicon semiconductor device 28 So purified Technical field

[0001] The invention relates to the field of semiconductor devices, and more specifically relates to a method for manufacturing a semiconductor device having an upper layer of silicon in the 28Si isotope with very little 29Si isotope, particularly advantageous for producing spin qubits with silicon technology. Technological background

[0002] Standard silicon natively contains the 14- and 15-neutron isotopes, denoted 28Si and 29Si respectively. Thus, the silicon commonly used in electronics contains nearly 4% of the 29Si isotope. However, for certain applications, it is desirable to have a silicon layer with a very low concentration of 29Si. This is particularly the case for producing devices with spin qubits in silicon technology, where it is desirable to have a silicon layer housing the qubits that is as pure as possible in 28Si, in order to avoid rapid decoherence of the qubits.

[0003] While it is known to epitaxially grow pure layers of silicon of isotope 28Si, a problem arises when it is desired to have a pure layer of silicon of isotope 28Si on a silicon on insulator, or SOI, substrate. Such an SOI substrate comprises a silicon substrate, a buried oxide, or BOX, layer on the silicon substrate, and a first upper layer of silicon on the buried oxide layer.

[0004] The formation of pure silicon layers of isotope 28Si is very expensive, because the purified precursor gas containing only isotope 28Si is very expensive. It is therefore not economically feasible to manufacture a completely pure SOI substrate of silicon of isotope 28Si. The first upper silicon layer and / or the buried oxide layer therefore generally also contain silicon of isotope 29Si.

[0005] A pure layer of silicon of isotope 28Si made on the first upper layer of silicon is polluted by 29Si isotopes migrating from the first upper layer of silicon and / or the buried oxide layer, since these layers contain them, in particular during the subsequent stages of manufacturing the semiconductor device, such as for example the production of transistors, which generally involve high temperatures likely to cause the 29Si isotopes to migrate. The performance of the qubits in this layer of silicon is therefore not optimal. Presentation of the invention

[0006] The invention therefore aims to propose a method making it possible to obtain at lower cost a semiconductor device having a top layer of silicon with a very low concentration of the isotope 29Si.

[0007] For this purpose, the invention proposes a method for manufacturing a semiconductor device, the method comprising, from an initial silicon-on-insulator, SOI, structure comprising a silicon substrate, a buried oxide layer, BOX, and a first upper silicon layer on the buried oxide layer, the first upper silicon layer having a first concentration of the 28Si isotope and a first concentration of the 29Si isotope: a) forming by epitaxy a first epitaxial layer of silicon of isotope 28Si on the first upper layer (6) of silicon, the first upper layer of silicon having a first thickness and the first epitaxial layer of silicon of isotope 28Si having a second thickness; b) a first homogenization annealing, the first epitaxial layer of silicon of isotope 28Si and the first upper layer of silicon then forming a second upper layer of silicon with a second concentration of isotope 28Si higher than the first concentration of isotope 28Si, and a second concentration of isotope 29Si lower than the first concentration of isotope 29Si; c) thinning the second upper layer to a third thickness.

[0008] The method is advantageously supplemented by the following different characteristics taken alone or according to their different possible combinations: - the first thickness is less than the third thickness; - the first thickness is less than 5 nm, and preferably less than or equal to 3 nm; - the second thickness is greater than 50 nm, and preferably greater than 100 nm; - the third thickness is between 12 nm and 25 nm.

[0009] Advantageously, the method may comprise, following the thinning of the second upper layer: d) forming by epitaxy a second epitaxial layer of silicon of isotope 28Si on the second upper layer of silicon thinned to the third thickness, the second epitaxial layer of silicon of isotope 28Si having a fourth thickness; e) a second homogenization annealing, the second epitaxial layer of silicon of isotope 28Si and the second upper layer of silicon thinned to the third thickness (T3) then forming a third upper layer of silicon with a third concentration of isotope 28Si greater than the second concentration of isotope 28Si, and a third concentration of isotope 29Si less than the second concentration of isotope 29Si.

[0010] In this case, preferably the third thickness is less than or equal to 6 nm. Also preferably, the second thickness and the fourth thickness are greater than 20 nm. Preferably, the second thickness and / or the fourth thickness are less than 60 nm, and more preferably less than 50 nm.

[0011] In all cases, the method can advantageously be supplemented by the following different characteristics taken alone or according to their different possible combinations: - the formation by epitaxy of a first epitaxial layer of silicon of isotope 28Si and the formation by epitaxy of a second epitaxial layer of silicon of isotope 28Si are carried out from a purified precursor gas containing only the isotope 28Si; - the steps of the method are implemented for a first area of ​​a surface of the semiconductor device, and not implemented for a second area of ​​the surface of the semiconductor device, the method subsequently comprising the formation of transistors on the second area of ​​the surface of the semiconductor device, the first area of ​​the surface being configured to house qubits; - the first zone has a thickness at least 2 nm greater than the thickness of the second zone; - the method may subsequently comprise the creation of isolation trenches, and the filling of isolation trenches using a purified precursor gas containing only the isotope 28Si; - the method may comprise a subsequent step of localized bombardment of a surface of the structure with argon to standardize the thickness of the third layer of silicon; - the method may comprise a prior step of thinning the first upper layer of silicon to the first thickness. Presentation of figures

[0012] Other characteristics, aims and advantages of the invention will emerge from the following description, which is purely illustrative and non-limiting, and which must be read in conjunction with the appended drawings in which: - [Fig.l] illustrates an initial silicon-on-insulator structure, according to a possible embodiment of the invention; - [Fig.2] illustrates the structure after thinning of the first upper silicon layer, according to a possible embodiment of the invention; - [Fig.3] illustrates the structure after the formation by epitaxy of a first layer of silicon of isotope 28Si, according to a possible embodiment of the invention; - [Fig.4] illustrates the structure after the first homogenization annealing, according to a possible embodiment of the invention; - [Fig.5] illustrates the structure after thinning of the second upper silicon layer, according to a possible embodiment of the invention; - [Fig.6] illustrates the structure after the formation by epitaxy of a second layer of silicon of isotope 28Si, according to a possible embodiment of the invention; - [Fig.7] illustrates the structure after a second homogenization annealing, according to a possible embodiment of the invention; - [Fig.8] illustrates the structure after the formation of isolation trenches, according to a possible embodiment of the invention. Detailed description

[0013] With reference to [Fig.l], the method for manufacturing a semiconductor device is implemented from an initial structure 1 of silicon on insulator, SOI, comprising a silicon substrate 2, a buried oxide layer 4, BOX, and a first upper layer 6 of silicon on the buried oxide layer, the first upper layer 6 of silicon having a first concentration Ci>28 of the isotope 28Si and a first concentration Ci>29 of the isotope 29Si. The silicon of the initial structure 1 is standard, that is to say that it has not been substantially purified of its isotopes 29Si. Typically, the first concentration Ci>28 of the isotope 28Si is between 92% and 93%, while the first concentration Ci>29 of the isotope 29Si is between 4% and 5%.The isotope 30Si is also typically present at about 3%, but has no significant consequences and will not be discussed further, although the process results in the elimination of this isotope 30Si in the same way as the isotope 29Si. For non-limiting demonstration purposes, the values ​​of 96% for Ci>28 and 4% for Ci>29 are retained. In this text, the concentrations indicated are molar concentrations.

[0014] The initial silicon-on-insulator structure 1 is preferably an FDSOI structure, from the English “fully depleted silicon-on-insulator” where at least the first upper layer 6 is completely depleted. The buried oxide layer 4 is typically made of silicon oxide.

[0015] If the first upper layer 6 of silicon is not sufficiently thin, and for example if it is thicker than a first thickness less than or equal to 5 nm, the method may comprise a prior step of thinning the first upper layer 6 of silicon to a first thickness Ti less than or equal to 5 nm, and preferably less than or equal to 4 nm, and preferably less than or equal to 3 nm. For demonstration purposes for the following examples, 3 nm is used as the first thickness Tb. The thinning may for example be carried out by oxidation in a furnace, followed by an attack, for example chemical, in particular by using hydrofluoric acid (HF), known as "HF wet etching", or by a so-called dry etching, for example using plasma. [Fig.2] shows the structure with the first upper layer 6 of silicon at the first thickness Ti.

[0016] The method comprises the epitaxial formation of a first epitaxial layer 8 of silicon of isotope 28Si on the first upper layer 6 of silicon, the first epitaxial layer 8 of silicon of isotope 28Si having a second thickness T2. Preferably, the second thickness T2 is greater than or equal to 15 nm, and more preferably greater than or equal to 20 nm. The epitaxy can be carried out from a purified precursor gas containing only the isotope 28Si, i.e. at least 99.9% of isotope 28Si. For example, from a SiF4 gas, sorting according to mass makes it possible to retain only the 28SiF4. Chloride compounds then make it possible to obtain the silicon atom of isotope 28Si. We then obtain, as illustrated in [Fig.3], a first epitaxial layer 8 of silicon of isotope 28Si on the first upper layer 6 of silicon, with therefore a thickness above the buried oxide layer 4 corresponding to the sum of the first thickness Ti and the second thickness T2.

[0017] The method then comprises a first homogenization thermal annealing, aimed at homogenizing the concentrations of 28Si and 29Si isotopes between the first epitaxial layer 8 of silicon and the first upper layer 6 of silicon, which then form a second upper layer 10 of silicon, as illustrated in [Fig. 4]. The second upper layer 10 of silicon has a second concentration C2>28 of the 28Si isotope higher than the first concentration Ci>28 of the 28Si isotope, and a second concentration C2j29 of the 29Si isotope lower than the first concentration C ij29 of the 29Si isotope. During the first homogenization thermal annealing, the heating of the structure 1 allows the 29Si isotopes to migrate from the first upper layer 6 of silicon to the first epitaxial layer 8 of silicon.For example, the homogenization thermal annealing can be carried out at a temperature of at least 1000°C for at least 20 minutes, and preferably at least 1050°C for at least 30 minutes. However, it is possible to modify the temperature and duration of the thermal annealing as long as the thermal budget allows sufficient migration of the 29Si isotopes to the upper part of the second top layer 10. For example, one can refer to the article by V. Mazzocchi et al. “99.992% 28Si CVD-grown epilayer on 300 nm substrates for large scale integration of Silicon spin qubits”. Journal of Crystal Growth 509 (2019) 1-7, for information on both epitaxial growth and homogenization thermal annealing in this context.

[0018] The second concentration C2>29 of the isotope 29Si depends on the first thickness Ti and the second thickness T2, as well as on the first concentration Ci>29 of the isotope 29If:

[0019] (7 -(7 x_Zi_

[0020] Taking Cij29=4%, Ti=3 nm, and T2=30 nm, we obtain C2j29=0.36%, i.e. a division by 10 of the concentration of isotope 29Si in the second upper layer 10 of silicon compared to the first upper layer 6 of silicon, i.e. compared to standard silicon. It is however possible that certain isotopes 29Si migrate from the buried oxide layer 4 to the second upper layer 10 of silicon during the homogenization thermal annealing. This effect does not, however, call into question the substantial reduction of the second concentration C2>29 of the isotope 29Si compared to the first concentration Ci>29 of the isotope 29Si, and it is possible to limit this effect by limiting the thermal budget of the first homogenization thermal annealing.

[0021] The method then comprises thinning the second upper layer 10 to a third thickness T3, as illustrated in [Fig. 5]. The same methods as for the possible thinning of the first upper layer 6 can be used. Preferably, the third thickness T3 is less than or equal to 6 nm, and more preferably less than or equal to 4 nm. The third thickness T3 can however be greater than the first thickness Tb.

[0022] The method then comprises the formation by epitaxy of a second epitaxial layer 12 of silicon of isotope 28Si on the second upper layer 10 of silicon thinned to the third thickness T3, the second epitaxial layer 12 of silicon of isotope 28Si having a fourth thickness T4. Preferably, the fourth thickness T4 is greater than or equal to 15 nm, and more preferably greater than or equal to 20 nm. A second epitaxial layer 12 of silicon of isotope 28Si is then obtained on the second upper layer 10 of silicon, with therefore a thickness above the buried oxide layer corresponding to the sum of the third thickness T3 and the fourth thickness T4.

[0023] The method then comprises a second homogenization annealing, aimed at homogenizing the concentrations of 28Si and 29Si isotopes between the second epitaxial layer 12 of silicon and the second upper layer 10 of silicon, which then form a third upper layer 14 of silicon, as illustrated in [Fig.7].

[0024] The third upper layer 14 of silicon has a third concentration C3>28 of the 28Si isotope higher than the second concentration C2>28 of the 28Si isotope, and a third concentration C3>29 of the 29Si isotope lower than the second concentration C2>29 of the 29Si isotope. As in the first homogenization thermal annealing, heating the structure allows the 29Si isotopes to migrate from the second layer upper 10 silicon layer to the second epitaxial layer 12 silicon layer. For example, the homogenization thermal annealing may be carried out at a temperature of at least 1000°C for at least 20 minutes, and preferably at least 1050°C for at least 30 minutes. However, it is possible to modify the temperature and duration of the thermal annealing as long as the thermal budget allows sufficient migration of the 29Si isotopes to the upper part of the third upper layer.

[0025] The third concentration C3>29 of the isotope 29Si depends on the third thickness T3 and the fourth thickness T3, as well as on the second concentration C2>29 of the isotope 29Si:

[0026] pcv l JC 3 29 ~ c 2.29 x

[0027] which can also be expressed as a function of the first concentration Ci>29 of the isotope 29Si:

[0028] (j _ (jx Ll.., x Z?

[0029] Taking Cij29=4%, Ti=3 nm, T2=30 nm, T3=5 nm and T4=25 nm, we obtain C3>29 =0.06%, i.e. a division by more than 50 of the 29Si isotope concentration in the third upper silicon layer 14 compared to the first upper silicon layer 6, i.e. compared to standard silicon. A possible migration of 29Si isotopes from the buried oxide layer 4 to the third upper silicon layer 14 during the second homogenization thermal annealing can take place, but even less pronounced than before, because the 29Si isotope concentration of the buried oxide layer 4 decreases with each migration. It is also possible to limit this effect by limiting the thermal budget of the second homogenization thermal annealing. In any case, it is possible to obtain a third upper layer 14 of silicon comprising less than 0.1% of 29Si isotope.

[0030] A semiconductor device is then obtained comprising an upper layer 14 of silicon on the buried oxide layer 4 which is practically free of 29Si isotope, with only two iterations of thinning-epitaxy-thermal annealing. The method is therefore very economical because it typically requires only between 30 nm and 80 nm of epitaxial growth using an expensive precursor gas consisting only of 28Si isotopes. It is possible to increase the purity obtained by repeating a thinning and epitaxy cycle as described, and / or by thinning the upper layers 6, 10 of silicon even more during their thinning, and / or by increasing the thickness of the epitaxial layers 8, 12. It is sufficient to reduce the thickness of the epitaxial layers 8, 12 to reduce the costs, possibly to the detriment of the degree of purity obtained.

[0031] These thinning-epitaxy-thermal annealing cycles may have the disadvantage of deteriorating the thickness uniformity of the upper layer 14 of final silicon, intended to be the active layer of the semiconductor device. However, small variations in thickness are acceptable for forming qubits in the semiconductor device since the qubits are generally formed in a thicker channel (for example between 10 and 15 nm) than for a channel of a conventional transistor, whose thickness is of the order of 7 to 10 nm. If it is desired to improve the homogeneity of the thickness of the final upper layer 14 of silicon which is above the buried oxide layer 4, it is possible to carry out a shaving, or "trimming" in English, for example by bombarding the upper layer of silicon with argon.

[0032] The method may be implemented on an entire wafer, or only on the areas intended to house qubits, in order to reduce the consumption of pure 28Si precursor gas. In addition, not implementing the method on certain areas makes it possible to maintain the thinner and more uniform thickness of the upper silicon layer in the areas intended to form the transistors, and to have a greater thickness in the purified areas intended for the qubits. Thus, preferably, the steps of the method are implemented for a first area of ​​a surface of the semiconductor device, and not implemented for a second area of ​​the surface of the semiconductor device, the method subsequently comprising the formation of transistors on the second area of ​​the surface of the semiconductor device, the first area of ​​the surface being configured to house qubits.Preferably, the first region has a thickness at least 2 nm greater than the thickness of the second region, and more preferably at least 4 nm greater than the thickness of the second region. For example, it is possible to use a silicon nitride mask on the second region of the surface of the semiconductor device during the implementations of the described steps of the method.

[0033] As mentioned above, the subsequent manufacturing steps, for example to produce transistors, may involve a rise in temperature of the semiconductor device, promoting the diffusion of 29Si isotopes into the final upper layer 14 from which they were practically absent. In order to limit this diffusion, it is possible to carry out, following the method described, the production of isolation trenches 16, or STI for "shallow trench isolation", and the filling of the isolation trenches 16 using a purified precursor gas containing only the 28Si isotope, as illustrated in [Fig. 8]. Thus, the isolation trenches 16 are devoid of 29Si isotopes and these cannot therefore migrate towards the final upper layer 14 of silicon purified by the described steps of the method. Advantageously, these are at least the isolation trenches 16 close to the locations intended to house qubits.Such isolation trenches 16 pass through at least the upper layer 14, typically also the buried oxide layer 4, and . generally reach the substrate 2. However, it is possible to provide isolation trenches 16 with lesser depths.

[0034] It is also possible, using the same methods unless otherwise specified, to carry out only one cycle of formation by epitaxy of a first epitaxial layer 8 of a second thickness T2 then first homogenization annealing, and thinning of the second upper layer 10 to the third thickness T3. In this case, the second thickness T2 is preferably greater than or equal to 50 nm, and more preferably greater than 100 nm. As previously, the second concentration C2>29 of the isotope 29Si depends on the first thickness Ti and the second thickness T2, as well as on the first concentration Ci>29 of the isotope 29Si:

[0035] c — C v Tt LJ C2.29 “ 1-1.29 x ft+T,

[0036] Taking Cij29=4%, Ti=3 nm, and T2=60 nm, we obtain C2j29=0.48%, i.e. a division by more than 8 of the concentration of isotope 29Si in the second upper layer 10 of silicon compared to the first upper layer 6 of silicon, i.e. compared to standard silicon. The greater the second thickness T2, the greater the purification will be, but the cost may be higher than in the multi-cycle variants, which consume less epitaxial layer thickness.

[0037] Typically, the thinning reduces the second upper layer 10 by at least 30 nm, and preferably by at least 45 nm. The third thickness T3 is thicker, since the thinning of the second upper layer is not followed by epitaxial formation of a second epitaxial layer 12. Preferably, the third thickness T3 is between 12 nm and 25 nm. The invention is not limited to the embodiment described and shown in the appended figures. Modifications remain possible, in particular from the point of view of the constitution of the various technical characteristics or by substitution of technical equivalents, without departing from the scope of protection of the invention, which is defined by the claims below.

Claims

Claims

1. A method of manufacturing a semiconductor device, the method comprising, from an initial silicon-on-insulator, SOI, structure (1), comprising a silicon substrate (2), a buried oxide layer (4), BOX, and a first upper silicon layer (6) on the buried oxide layer (4), the first upper silicon layer (6) having a first concentration of the isotope 28Si and a first concentration of the isotope 29Si: a) epitaxially forming a first epitaxial silicon layer (8) of isotope 28Si on the first upper silicon layer (6), the first upper silicon layer (6) having a first thickness (TJ and the first epitaxial silicon layer (8) of isotope 28Si having a second thickness (T2);b) a first homogenization annealing, the first epitaxial layer (8) of silicon of isotope 28Si and the first upper layer (6) of silicon then forming a second upper layer (10) of silicon with a second concentration of isotope 28Si higher than the first concentration of isotope 28Si, and a second concentration of isotope 29Si lower than the first concentration of isotope 29Si; c) thinning of the second upper layer (10) to a third thickness (T3).;

2. The method of claim 1, wherein the first thickness (TJ) is less than the third thickness (T3).

3. Method according to any one of the preceding claims, in which the first thickness (Ti) is less than 5 nm, and preferably less than or equal to 3 nm.

4. Method according to one of the preceding claims, in which the second thickness (T2) is greater than 50 nm, and preferably greater than 100 nm.

5. Method according to one of the preceding claims, in which the third thickness (T3) is between 12 nm and 25 nm.

6. Method according to one of claims 1 to 3, comprising following the thinning of the second upper layer (10): d) the formation by epitaxy of a second epitaxial layer (12) of silicon of isotope 28Si on the second upper layer (10) of silicon thinned to the third thickness (T3), the second epitaxial layer (12) of silicon of isotope 28Si having a fourth thickness (T4); e) a second homogenization annealing, the second epitaxial layer (12) of silicon of isotope 28Si and the second upper layer (10) of silicon thinned to the third thickness (T3) then forming a third upper layer (14) of silicon with a third concentration of isotope 28Si greater than the second concentration of isotope 28Si, and a third concentration of isotope 29Si less than the second concentration of isotope 29Si.

7. The method of claim 6, wherein the third thickness (T3) is less than or equal to 6 nm.

8. A method according to any one of claims 6 to 7, wherein the second thickness (T2) and the fourth thickness (T4) are greater than 20 nm.

9. A method according to any preceding claim, wherein the epitaxial formation of a first epitaxial layer (8) of silicon of isotope 28Si and the epitaxial formation of a second epitaxial layer (12) of silicon of isotope 28Si are carried out from a purified precursor gas containing only the isotope 28Si.

10. A method according to any preceding claim, wherein the method steps are performed for a first area of ​​a surface of the semiconductor device, and not performed for a second area of ​​the surface of the semiconductor device, the method subsequently comprising forming transistors on the second area of ​​the surface of the semiconductor device, the first area of ​​the surface being configured to house qubits.

11. Method according to the preceding claim, in which the first zone has a thickness greater than at least 2 nm compared to the thickness of the second zone.

12. A method according to any preceding claim, further comprising providing isolation trenches (16), and backfilling the isolation trenches (16) using a purified precursor gas containing only the isotope 28Si.

13. A method according to any preceding claim, comprising a subsequent step of localized bombardment of a surface of the structure with argon to uniformize the thickness of the third layer (14) of silicon.

14. A method according to any preceding claim, comprising a prior step of thinning the first layer upper (6) of silicon up to the first thickness (Ti).

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