OPTOELECTRONIC DEVICE COMPRISING A LIGHT-ELECTRICAL DIODE SUPERIMPOSED ON A PHOTODETECTOR

Abstract

The invention relates to an optoelectronic device comprising a control circuit, a pixel including a photodetector, a light-emitting diode (LED), and an intermediate region interposed between the photodetector and the LED. The photodetector is sensitive to a detection wavelength λ2. The LED comprises an active stack with a cutoff wavelength λc less than λ2 and a buried electrode interposed between an interconnection stack of the circuit and the active stack, and covering a detection surface of the photodetector. The device further comprises a via passing through the active stack and extending to the interconnection stack; an electrical contact passing through the active stack and in contact with the buried electrode; and an electrical path electrically connecting the buried electrode to the control circuit and comprising the electrical contact and the via.The intermediate region is devoid of metal and the buried electrode is transparent at λ2. Figure for the abbreviation: Figure 2I.

Description

Title of the invention: OPTOELECTRONIC DEVICE COMPRISING A LIGHT-ELECTRICAL DIODE SUPERIMPOSED ON A PHOTODETECTOR technical field

[0001] The field of the invention is that of optoelectronic devices combining a light emission function and a light flux detection function. The invention relates, for example, to an interactive display screen comprising a matrix sensor and a matrix of light-emitting diodes driven by a control circuit. The invention also relates to a method for manufacturing such a device. PRIOR TECHNOLOGY

[0002] Display screens have benefited from technological advances in the field of light-emitting diodes (LEDs) for lighting. For example, there are screens of all sizes that use gallium nitride (GaN) LEDs. Among these, microdisplays generally comprise a large number of LEDs, typically smaller than 10 µm, arranged in a matrix. Each LED constitutes a pixel of the microdisplay. Gallium nitride (GaN) microdisplays offer high luminance, good resolution, are compact, and generally consume little power.

[0003] Recently, new types of displays, known as interactive displays, have emerged. One type of interactive display combines a matrix of light-emitting diodes (LEDs) with a matrix photon sensor, both powered and controlled by a control circuit. These allow for new applications requiring a response from the interactive display itself and / or from a system in which the interactive display is integrated, based on a luminous flux detected and / or measured by the matrix sensor. The matrix photon sensor is an optoelectronic component comprising several photodetectors arranged in a matrix. When each photodetector of the photon sensor is positioned opposite its respective LED, the interactive display is compact and has good resolution.

[0004] Patent application EP4148810 is such an example of an interactive display based on GaN light-emitting diodes. In this document, an integrated circuit comprises a first substrate and several interconnection levels on the first substrate. The first substrate further integrates a photon sensor comprising a photodiode array. A light-emitting diode array is fabricated on a second substrate from epitaxial layers based on AUnGaN and / or InGaN and / or AlGaN. and / or GaN. The light-emitting diodes are separated from each other by grids of conductive material, each electrically isolated from the light-emitting diodes. The latter are therefore individualized.

[0005] The first and second substrates respectively comprise first and second metallic connection pads, flush with one face of a first dielectric layer and one face of a second dielectric layer, respectively. The second substrate is transferred onto the first substrate by hybrid direct bonding of the first and second connection pads and of the first and second dielectric layers. For this purpose, the occupancy rate of the first and second connection pads is between 60% and 90% on each face. Following this step, each light-emitting diode (LED), previously separated before the transfer, is positioned opposite a photodiode and separated from it by a first connection pad bonded to a second connection pad, which is itself in contact with a second electrode of the LED. The second electrode is metallic and reflective.An assembly consisting of a first interconnecting pad, a second interconnecting pad, and a second electrode constitutes an individual buried electrode of the light-emitting diode (LED). Each buried electrode is an anode electrode of an individual LED. LEDs have a common cathode made of indium tin oxide (ITO).

[0006] In this configuration, the photodiode receives incident light on a portion of a detection surface that is not located directly above the buried electrode. This incident light may originate from the opposite light-emitting diode or from an external source. Consequently, the photodiode receives only a portion of the incident light, specifically the portion not blocked by the buried electrode. This portion of the incident light is received, for example, through a hole in the second electrode, concentric with larger holes in the first and second connection pads. Increasing the surface area of ​​the second electrode increases the quantum efficiency of the light-emitting diode, but at the expense of the amount of light reaching the photodiode.

[0007] This results in a compromise between the sensitivity of the photon sensor and the emission efficiency of the light-emitting diode array. Description of the invention

[0008] The invention aims to remedy, at least in part, the drawbacks of the prior art, and more particularly to provide an optoelectronic device comprising a light-emitting diode superimposed on a photodetector with increased sensitivity to incident light flux, without compromising efficiency of emission of the light-emitting diode. The optoelectronic device of the invention is particularly advantageous for use in a lab-on-a-chip type system.

[0009] To this end, the object of the invention is an optoelectronic device comprising a substrate; a control circuit integrated in and / or on the substrate comprising an interconnect stack; and a matrix of at least one pixel. Each pixel comprises a photodetector, a light-emitting diode (LED), and an intermediate region interposed between the photodetector and the LED. Each pixel is such that the photodetector is sensitive to a detection wavelength X2 and comprises a detection surface extending in a plane substantially parallel to a principal plane of the substrate. The LED comprises an active stack with a cutoff wavelength Xc lower than the detection wavelength X2. The active stack comprises first and second doped layers of opposite types. The LED further comprises a buried electrode in contact with the second doped layer.The light-emitting diode is arranged such that the buried electrode is interposed between the interconnect stack and the active stack, and covers the detection surface. Each pixel is such that the intermediate region is delimited by the detection surface and extends from the detection surface to the active stack. The optoelectronic device further includes a via passing through the active stack and extending to an interconnect level of the interconnect stack; an electrical contact passing through the active stack and in contact with the buried electrode; and an electrical path electrically connecting the buried electrode to the control circuit and including the electrical contact and the via. The intermediate region is metal-free. The buried electrode is transparent at the detection wavelength X2.

[0010] Some preferred but not limiting aspects of this optoelectronic device are as follows.

[0011] The optoelectronic device may be such that for each pixel, the light-emitting diode may include an active region extending between the first and second doped layers in a plane substantially parallel to the main plane; a conductive trench that may surround the active region and the intermediate region, may traverse the active stack through and through and may extend to an interconnection level of the interconnection stack; and a surface electrode in contact with the first doped layer, electrically connected to the control circuit by the conductive trench.

[0012] The optoelectronic device may be such that the conductive trench is coated with a mirror.

[0013] The matrix may comprise several pixels, and the surface electrode may be a common electrode for all pixels.

[0014] The conductive trenches of two neighboring pixels may have a part in common.

[0015] The intermediate region may include an intermediate optical function layer that can extend parallel to the main plane of the substrate.

[0016] For each pixel, the buried electrode can be made of indium tin oxide, aluminum-doped zinc oxide, or tin dioxide.

[0017] For each pixel, the surface electrode can be made of an indium-tin oxide, or of an aluminum-doped zinc oxide.

[0018] The optoelectronic device may further include a surface layer of optical function disposed on a face of the optoelectronic device opposite the substrate.

[0019] The surface layer of optical function can be an absorbing layer having an opening opposite the detection surface.

[0020] The optoelectronic device may further include a heating element disposed on a face of the optoelectronic device opposite the substrate, the heating element being able to have an opening facing the detection surface.

[0021] The detection wavelength X2 may belong to the visible spectrum and the light-emitting diode may be capable of emitting a luminous flux in the UVA range.

[0022] The invention also relates to a method for manufacturing an optoelectronic device comprising a light-emitting diode and a photodetector sensitive to a detection wavelength X2. The method includes providing a first assembly comprising, in order, a first substrate, a semiconductor stack and a lower conductive layer, such that the semiconductor stack comprises a first layer doped with a first type of conductivity and a second layer doped with a second type of conductivity opposite to the first type of conductivity, intercalated between the first doped layer and the first substrate, and such that the lower conductive layer is in physical contact with the second doped layer.

[0023] The method includes providing a second assembly comprising a second substrate, a control circuit and the photodetector, such that the control circuit is integrated in and / or on the second substrate and includes an interconnect stack.

[0024] The method includes transferring a face of the first assembly opposite the first substrate onto a face of the second assembly opposite the second substrate by direct bonding using a bonding layer transparent at the detection wavelength X2.

[0025] The process includes exposing the first doped layer by removing the first substrate, to obtain an active stack comprising the first doped layer and the second doped layer.

[0026] The method includes etching a first hole implementing an alignment of the first hole with respect to an element of the second set, such that the first hole goes all the way through the active stack and extends to an interconnection level of the interconnection stack.

[0027] The method includes etching a second hole implementing an alignment of the second hole with respect to an element of the second assembly, such that the second hole goes all the way through the active stack with stopping on the lower conductive layer.

[0028] The process includes passivating the first hole and the second hole to obtain, respectively, a first passivated hole and a second passivated hole.

[0029] The process includes filling the first and second passivated holes with a metal to obtain, respectively, a via and an electrical contact.

[0030] The method includes the formation of a conductive line electrically isolated from the active stack and in contact with the electrical contact and the via.

[0031] The method includes the formation of an active region of the light-emitting diode in the active stack opposite a detection surface of the photodetector, subsequent to the bonding step, implementing an alignment of the active region with respect to an element of the second assembly.

[0032] The formation of the active region may include a sub-step of engraving a trench that may cross the active stack from one side to the other and may extend to an interconnection level of the interconnection stack.

[0033] The bonding layer may include an intermediate layer with optical function. Brief description of the drawings

[0034] Other aspects, objectives, advantages and features of the invention will become more apparent upon reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the accompanying drawings in which:

[0035] [Fig.1A] is a schematic cross-sectional view of a first assembly comprising a semiconductor stack on a first substrate;

[0036] [Fig.1B] is a schematic cross-sectional view of a second assembly comprising a second substrate, a control circuit and a photodetector;

[0037] Figures 2A to 2H are schematic cross-sectional views of intermediate steps of a first manufacturing process of a first optoelectronic device according to the invention;

[0038] Figures 21 and 2J are respectively a schematic side section view and a schematic top section view of the first optoelectronic device;

[0039] [Fig.3A] is a schematic cross-sectional view of a first variant of the optoelectronic device according to the invention;

[0040] [Fig.3B] is a schematic cross-sectional view of a second variant of the optoelectronic device according to the invention;

[0041] [Fig.3C] is a schematic cross-sectional view of a third variant of the optoelectronic device according to the invention;

[0042] [Fig.3D] is a schematic cross-sectional view of a fourth variant of the optoelectronic device according to the invention;

[0043] [Fig.3E] is a schematic cross-sectional view of a fifth variant of the optoelectronic device according to the invention;

[0044] [Fig.4A] is a schematic cross-sectional view of a variant of the second assembly;

[0045] [Fig. 4B] is a schematic cross-sectional view of a sixth variant of the first optoelectronic device obtained at the end of the first manufacturing process applied to the variant of the second assembly;

[0046] Figures 5A and 5B are schematic cross-sectional views of intermediate steps of a second manufacturing process for a second optoelectronic device according to the invention;

[0047] Figures 5C and 5D are respectively a schematic side section view and a schematic top view of a second optoelectronic device from the second manufacturing process;

[0048] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0049] In the figures and in the following description, the same reference numerals represent identical or similar elements. Furthermore, the various elements are not drawn to scale in order to enhance the clarity of the figures. Moreover, the different embodiments and variants are not mutually exclusive and may be combined. Unless otherwise indicated, the terms "approximately," "about," and "in the order of" mean within 10%, and preferably within 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the limits are inclusive, unless otherwise stated.

[0050] The invention relates to an optoelectronic device comprising a substrate, a control circuit integrated in and / or on the substrate which includes a stack The circuit consists of interconnections, a light-emitting diode (LED), and a photodetector. The LED is superimposed on the photodetector and powered and / or controlled by the control circuit. The photodetector is arranged and configured to detect a luminous flux, called the incident flux, at a detection wavelength X2, passing through the LED to reach a detection surface of the photodetector. This is possible because the LED has a semiconductor stack with a cutoff wavelength Xc shorter than the detection wavelength X2. It therefore emits a luminous flux, called the emitted flux, at an emission wavelength Xi shorter than the detection wavelength X2.

[0051] The light-emitting diode comprises a stack of semiconductor layers and a buried electrode arranged between the stack of semiconductor layers and the detection surface.

[0052] The buried electrode is transparent at wavelength X2 and is not in physical contact with any interconnection level of the interconnection stack. It is electrically connected to an interconnection level of the interconnection stack by an electrical path comprising an electrical contact, a via, and a conductive line covering one face of the semiconductor stack opposite the buried electrode. Both the electrical contact and the via pass completely through the semiconductor stack. The electrical contact is in physical contact on the upper part of the buried electrode opposite the interconnection stack. The via extends to an interconnection level of the interconnection stack. Thus, increasing the detection area of ​​the photodetector results in an increase in the detected incident light flux without requiring a reduction in the lateral dimensions of the buried electrode.In other words, the sensitivity of the photodetector is increased without loss of emission efficiency of the light-emitting diode.

[0053] The invention also relates to a method for manufacturing such an optoelectronic device. It comprises transferring a first assembly onto a second assembly. The first assembly comprises, in order, a first substrate, a semiconductor stack, and a conductive layer. The second assembly comprises a second substrate, a control circuit, and a photodetector. The control circuit is integrated into and / or onto the second substrate and includes an interconnect stack. The conductive layer is transparent to the X2 detection wavelength of the photodetector. It is interposed between the semiconductor stack and the photodetector after the transfer.

[0054] The method includes a step, subsequent to the transfer, of forming an active region of the light-emitting diode in the semiconductor stack, by alignment on an element of the second assembly, in order to position the active region opposite the photodetector. The method further includes a step, after the transfer, of forming a via and a conductive trench that pass completely through the semiconductor stack and extend to the respective connection pads of the interconnect stack. The via and the trench are intended to electrically connect the LED to the control circuit. The formation of the via and the conductive trench involves alignment on an element of the second assembly. Thus, the alignments of the active region of the LED with respect to the photodetector, and of the via and the conductive trench with respect to the connection pads, are precise. Consequently, the effective detection area of ​​the photodetector is increased, especially since it is possible to use smaller connection pads.The sensitivity of the photodetector is therefore increased.

[0055] The detection surface of a photodetector delimits the smallest flat surface of the photodetector through which all the photons of an incident light flux pass, capable of generating a signal detected by a reading circuit of the photodetector.

[0056] An active region of an optoelectronic device is a part of the device designed to emit or detect light radiation of interest. The active region of a light-emitting diode (LED) is the region(s) within which charge carriers from the LED's electrodes recombine to produce photons. The active region of a photodiode is the region(s) within which a photon is capable of generating a signal detected by a readout circuit of the photodiode.

[0057] In the description, "metal" is given its meaning commonly used in the technical field of the invention. For the sake of clarity, however, it is specified that metal oxides, such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO) or tin dioxide (SnO2), are not metals.

[0058] In the description, "interconnect stack" is given its meaning commonly used in the technical field of the invention. For clarity, however, it is specified that an interconnect stack comprises layers called "interconnect levels," separated in pairs by layers called "interlevel layers." The interconnect levels consist of metallic lines separated by an electrically insulating material. The interlevel layers consist of metallic vias electrically connecting a metallic line of one interconnect level to another metallic line of a neighboring interconnect level or to a substrate on which the interconnect stack rests. The vias are separated by an electrically insulating material.

[0059] For the purposes of this description, a layer is defined as an area consisting of one or more sublayers of a material, the thickness of which along a z-axis is less than, for example, ten times or even twenty times, its longitudinal dimensions of width and length in a plane (x, y) perpendicular to the z-axis. A layer may be structured. When it consists of several sublayers, the sublayers may be made of different materials. The sublayer(s) extend in planes substantially parallel to the (x, y) plane. A conformal layer is a specific type of layer formed in contact with a non-planar surface, for which the thickness, measured perpendicular to the surface, is substantially constant, for example, within 10% or even 5%.

[0060] The cutoff wavelength Xc of a semiconductor material is the maximum wavelength of an incident photon that can be absorbed to excite an electron from the valence band to the conduction band of the semiconductor material, thereby creating a free electron and a hole. This absorption occurs when the energy of the incident photon is equal to or greater than the band gap energy of the semiconductor material, also known as the band gap or gap energy. The cutoff wavelength Xcd of a semiconductor stack is equal to the minimum value of the cutoff wavelengths of all the semiconductor materials that constitute the semiconductor stack.

[0061] A first element is aligned with respect to a second element if the formation of the first element involves a photolithography substep implementing the registration of the second element followed by an alignment process based on this registration. The second element can be a set of typical alignment marks used by photolithography tools. The alignment is said to be first-order, or primary, when the formation of the first element implements the photolithography substep. The alignment is said to be second-order, or secondary, when the photolithography substep is part of a formation step of an intermediate element on which the first element is aligned to the first order. It is said to be higher-order when it is neither primary nor secondary.A primary alignment is more precise than a secondary alignment; that is, the relative position of the first element with respect to the second element and with respect to any other element formed at the same time as the second element is more precise with a primary alignment than with a secondary alignment. A secondary alignment is more precise than a higher-order alignment. The first element can be a mask obtained by an additional photolithography step. In this case, the additional photolithography step is said to be aligned with respect to the second element.

[0062] Particular embodiments will be described relating to an optoelectronic device comprising a light-emitting diode superimposed on a photodetector. However, these embodiments can be adapted to other optoelectronic devices, for example to a multispectral sensor having an additional photodetector instead of the light-emitting diode.

[0063] A first manufacturing process leading to a first embodiment is described below in relation to figures 2A to 2J.

[0064] In [Fig. 2A], a first assembly is transferred onto a second assembly. The first and second assemblies are respectively shown in the cross-sectional views of Figures IA and IB. The first and second assemblies may, for example, each be supplied, in whole or in part, by a semiconductor foundry.

[0065] The first assembly 5 comprises, in order, a first substrate 100, a semiconductor stack 101, a lower conductive layer 102, and an upper bonding layer 103. The semiconductor stack 101 is in physical contact with the first substrate 100 and the lower conductive layer 102. The upper bonding layer 103 is in physical contact with the lower conductive layer 102.

[0066] Semiconductor stack 101 is a stack of semiconductor layers. It comprises a first layer doped 101.2 of a first type of conductivity and a second layer doped 101.4 of a second type of conductivity opposite to the first type of conductivity. The first doped layer 101.2 is intercalated between the second doped layer 101.4 and the first substrate 100. The semiconductor stack 101 can be grown by epitaxy on the first substrate 100. Optionally, it may include a buffer layer 101.1 for matching a lattice parameter of the first doped layer 101.2 with a lattice parameter of the first substrate 100.

[0067] Alternatively, the semiconductor stack 101 can be grown by epitaxy on a temporary substrate and transferred to the first substrate 100, for example, by directly bonding the first doped layer 101.2 to a face of the first substrate 100. For example, a p-type doped layer is epitaxially grown on the temporary substrate intended to become the second doped layer 101.4 of the semiconductor stack 101; an intrinsic layer is epitaxially bonded to the p-type doped layer; and an n-type doped layer is epitaxially bonded to the intrinsic layer destined to become the first doped layer 101.2 of the semiconductor stack 101. Optionally, the semiconductor stack 101 may include a buffer layer 101.1, in contact with the first doped layer 101.2 and the first substrate 100, serving as a bonding layer. This may, for example, be an oxide-oxide, silicon-silicon, or silicon nitride-silicon nitride bond. The bonding layer may include a bonding interface. This alternative is, for example, preferred to obtain a first p-type gallium nitride (GaN) doped layer 101.2.

[0068] The semiconductor stack 101 comprises a direct-bandgap crystalline semiconductor material, the bandgap energy value of which is suitable for enabling the emission of a luminous flux at an emission wavelength Xp

[0069] The first and second doped layers 101.2, 101.4 are made of semiconductor materials. The semiconductor stack 101 may include a semiconductor active layer 101.3, sandwiched between the first doped layer 101.2 and the second doped layer 101.4, and in physical contact with both layers. The active layer 101.3 may, for example, comprise several semiconductor sublayers with different band gap energies to create quantum wells. It may be unintentionally doped or lightly doped of the p or n type.

[0070] The first and second doped layers 101.2, 101.4 and the active layer 101.3 can, for example, be made of semiconductor materials selected from gallium nitride, gallium phosphide, gallium arsenide, and indium phosphide.

[0071] In the specific, non-limiting context of the method example described below, the first doped layer 101.2 is an n-type doped layer of gallium nitride (GaN). The second doped layer 101.4 is a p-type doped layer of gallium nitride (GaN). The first substrate 100 is silicon, for example, a silicon wafer with a diameter of 150 mm, 200 mm, or 300 mm. The buffer layer 101.1 comprises an aluminum nitride (AIN) sublayer in physical contact with the first substrate 100 and a succession of GaN / AlGaN bilayers, the AlGaN sublayers having lower aluminum concentrations the further they are from the first substrate 100. The active layer 101.3 comprises AlGaN-based quantum wells whose composition is adapted for light emission in the UVA range.

[0072] For the sake of clarity, certain elements of the description are hereinafter referred to by their intended function resulting from the specific choice of doping types for the layers described above. This designation should in no way be interpreted as a limitation. Thus, for example, a cathode trench can accommodate a conductive trench connecting the cathode of the light-emitting diode, in the specific case described below, or the anode of the light-emitting diode if the first doped layer 101.2 and the second doped layer 101.4 are doped with p-type and n-type doping, respectively.

[0073] The second assembly 6 comprises a second substrate 200, a control circuit, and a photodetector 210. The second substrate 200 is, for example, made of silicon. Advantageously, it has the same dimensions as the first substrate 100. For example, the first and second substrates can both be wafers of 150 mm, 200 mm, or 300 mm. The control circuit is integrated on one face, called the front face, of the second substrate 200 and possibly in the second substrate 200. It can be of the CMOS type. It includes an interconnect stack 201 resting on a front face of the second substrate 200, for example in contact with the front face.

[0074] The interconnection stack 201 has at least one interconnection level. The interconnection stack 201 here includes an anode connection pad 221 and a cathode connection pad 222 arranged in one interconnection level of the interconnection stack 201. The anode and cathode connection pads 221, 222 are made of metal, for example copper. In this example, the interconnection level comprising the anode and cathode connection pads 221, 222 is the last interconnection level of the interconnection stack 201, i.e., the furthest from the second substrate 200. Advantageously, the interconnection stack 201 may include a passivation layer of a dielectric material, for example silicon nitride (SiN), having one face of the interconnection stack 201 opposite the second substrate 200. In this case, the control circuit and / or the photodetector 210 are preferably not tested before the transfer step of the [Fig.2A]. .

[0075] The second assembly 6 further comprises a lower bonding layer 203 resting on the interconnection stack 201 on one side of the interconnection stack 201 opposite the second substrate 200. The lower bonding layer 203 may be the passivation layer of the interconnection stack 201 or an additional layer deposited on the passivation layer, advantageously previously polished.

[0076] The photodetector 210 comprises a detection surface 211 substantially parallel to the front face of the second substrate 200. Preferably, the detection surface 211 is located opposite a metal-free region of the interconnect stack 201, i.e., the interconnect stack 201 has no metal lines or vias directly above the detection surface. The detection surface is here in the vicinity of the front face of the second substrate 200.

[0077] The photodetector 210 is sensitive to a detection wavelength X2, for example within the visible or near-infrared spectrum, for example equal to 630 nm. In addition, it can also be sensitive to the emission wavelength Xp. The control circuit is electrically connected to the photodetector 210 and integrates functions for powering the photodetector 210 and for reading the charges generated in the photodetector 210.

[0078] The second assembly 6 may include several photodetectors 210, for example arranged in a matrix extending parallel to the front face of the second substrate 200. The interconnection stack 201 may further include one or more additional connection pads 223, for example arranged along the edge of the photodetector matrix 210. In [Fig.1B], two additional connection pads 223 are shown in the same interconnection level as the anode and cathode connection pads 221, 222. The additional connection pads 223, if they exist, and the anode and cathode connection pads 221, 222 are hereafter collectively referred to as the connection pads 221, 222, 223.

[0079] The second assembly 6 can be, for example, as shown here, a front-side illumination (FSI) image sensor. It can also be a back-side illumination (BSI) image sensor. In this case, the second substrate 200 is sandwiched between the interconnect stack 201 and the lower adhesive layer 203. The lower adhesive layer 203 can result from deposition or thermal oxidation of the second substrate 200.

[0080] The transfer step of [Fig.2A] can advantageously be a direct bonding by bringing into contact a face to be assembled of the upper bonding layer 103 opposite the first substrate 100 on a face to be assembled of the lower bonding layer 203 opposite the second substrate 200. The upper and lower bonding layers 103, 203 are transparent at the detection wavelength X2, and can in addition be transparent at the emission wavelength Xb. They transmit for example at least 50% of an incident light at normal incidence at the detection wavelength X2 and / or emission wavelength Xb or preferably at least 90%, or even at least 95%.

[0081] The direct bonding methods implemented within the framework of the invention can be of all known types. They can be direct bonding by molecular adhesion. In this case, the bonding results from chemical bonds that are established between the assembled faces. Several types of molecular adhesion bonding exist. They differ in particular by temperature, pressure, atmospheric conditions, and / or pretreatments prior to bringing the faces to be joined into contact. For example, they can be room-temperature bonding, hydrophilic or hydrophobic, with or without prior plasma activation of the faces to be joined, possibly followed by a heat treatment to strengthen the bonding interface. They can also be atomic diffusion bonding (ADB) or surface-activated bonding (SAB).

[0082] In the context of direct bonding during the transfer step of [Fig. 2A], the upper and lower bonding layers 103, 203 can both be made of silicon oxide, silicon nitride, or amorphous silicon. The upper and lower bonding layers 103, 203 are shown here to be made of silicon oxide and each has a thickness between 300 nm and 600 nm. Their faces to be bonded have been The surfaces are polished prior to transfer to obtain a roughness suitable for direct bonding by molecular adhesion. A heat treatment to consolidate the bonding interface is applied after the upper and lower bonding layers 103, 203 are brought into contact, at a temperature between 300 °C and 400 °C. Following the transfer step [Fig. 2A], the upper and lower bonding layers 103, 203 form a single bonding layer 303.

[0083] The lower conductive layer 102 is transparent at the detection wavelength X2, and may also be transparent at the emission wavelength Xp. For example, it transmits at least 50% of incident light at normal incidence at the detection wavelength X2 and / or emission wavelength Xi, or preferably at least 90%, or even at least 95%. The lower conductive layer 102 may be made of a metal oxide, for example indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), or tin dioxide (SnO2). In this example, the lower conductive layer 102 is made of indium tin oxide (ITO) and has a thickness between 40 nm and 120 nm.

[0084] Here and for the remainder of the description, a three-dimensional orthogonal (X, Y, Z) direct frame is defined, where the X and Y axes form a plane parallel to a principal plane of the second substrate 200, where the X axis is an axis of the cutting plane of Figures 2A to 2K, of Figures 3A to 3E, of Figures 4A, 4B, 5A, 5B, 5C, and where the Z axis is oriented substantially orthogonally to the principal plane of the second substrate 200, from the second substrate 200 to the interconnection stack 201 and the bonding layer 303. In the remainder of the description, the terms "vertical" and "vertically" are understood as relating to an orientation substantially parallel to the Z axis, and the terms "horizontally" and "horizontally" as relating to an orientation substantially parallel to the (X, Y) plane.Furthermore, the terms "lower" and "upper" are understood as relating to an increasing positioning when moving away from the second substrate 200 along the +Z direction. In the (X, Y, Z) coordinate system, a layer, stack, or substrate extends from a top face to a bottom face, both parallel to the (X, Y) plane. The top face and / or the bottom face may be structured.

[0085] In [Fig. 2B], the first substrate 100 is removed, for example, by a succession of grinding and / or polishing and / or wet etching substeps. In the particular example of [Fig. 2B], the first silicon substrate 100 is removed by a succession of increasingly fine grinding substeps, followed by selective wet chemical etching with respect to AlN.

[0086] The optional buffer layer 101.1 is then removed to expose the n-type doped layer 101.2, for example by dry etching and / or electropolishing. Following the removal of the first substrate 100 and the possible removal of the buffer layer 101.1 If it exists, the remaining part of the semiconductor stack 101 is a semiconductor stack, called active, 301, which has a cutoff wavelength Xc. The active stack 301 typically has a thickness equal to 1 pm.

[0087] A hard mask 320 is then deposited on the n-type doped layer 101.2 of the active stack 301. It can be made of silicon dioxide (SiO₂), silicon nitride (SiN), or silicon oxynitride (SiON). In this particular example, it is made of silicon dioxide and has a thickness between 1 pm and 1.5 pm, for example, 1.2 pm.

[0088] An anode opening 331 and a cathode opening 332 are etched into the hard mask 320 directly above the anode connection pad 221 and the cathode connection pad 222, respectively, so that they pass completely through the hard mask 320. For example, the anode and cathode openings 331, 332 can be defined by a photolithography substep aligned, preferably to the first order, with respect to an element of the second assembly 6, for example, alignment marks positioned on the second substrate 200 or in the interconnect stack 201. Thus, the position of the anode and cathode openings 331, 332 with respect to the anode and cathode connection pads 221, 222 is precise, and it is possible to reduce the horizontal dimensions of the latter.The connecting pads 221, 222, 223 typically have minimum dimensions in a plane parallel to the (X, Y) plane of between 500 nm and 5 pm, for example between 500 nm and 1 pm.

[0089] In the example of [Fig.2B], additional optional openings 333 are engraved in the hard mask 320 in line with a respective additional connection pad 223.

[0090] The cathode aperture 332 may have a loop shape in a plane parallel to the (X, Y) plane, for example, a circular, rectangular, or square loop. The anode aperture 331 and the additional apertures 333, for example, have disk shapes in a plane parallel to the (X, Y) plane. When the cathode aperture 332 has a loop shape, it surrounds the anode aperture 331. Here, the cathode aperture 332 has a loop shape, for example, a square.

[0091] The openings are for example made by a reactive dry etching through an exposed resin during the photolithography substep, with stopping on the n 101.2 type doped layer. The resin can be removed by application of an oxygen plasma and a chemical solvent.

[0092] In [Fig. 2C], the active stack 301, the lower conductive layer 102, the bonding layer 303, and the optional passivation layer are successively etched through the anode, cathode, and additional openings 331, 332, 333, until they reach the connecting pads 221, 222, 223. One or more substeps of Reactive dry etching is used, for example. The last etching substep is, for example, a selective etching of the passivation layer or the bonding layer 303, as opposed to the metallic material of the connecting pads 221, 222, 223. Chemical cleaning can advantageously be carried out after the etching step.

[0093] At the end of the step in [Fig. 2C], a first anode hole 341 is obtained opposite the anode opening 331, a cathode trench 342 opposite the cathode opening 332, and additional holes 343 opposite the additional openings 333. The first anode hole 341 has a bottom consisting of a portion of the anode connection pad 221. Similarly, the cathode trench 342 and the additional holes 343 each have a bottom consisting, respectively, of a portion of the cathode connection pad 222 and additional connection pads 223.Advantageously, the anode connection pad 221, the cathode connection pad 222, and the additional connection pads 223 have shapes similar, respectively, to the first anode hole 341, the cathode trench 342, and the additional holes 343 in a plane parallel to the (X, Y) plane, possibly with a difference in dimensions in this plane that can absorb alignment errors during the photolithography substep. The first anode hole 341, the cathode trench 342, and the additional holes 343 are hereafter collectively referred to as through trenches 341, 342, 343.

[0094] In [Fig. 2D], an additional opening is etched in the hard mask 320. A second anode hole 345 is then etched in the active stack 301 through the additional opening, until it reaches, but does not exceed, the lower conductive layer 102. The additional opening is, for example, defined by a photolithography substep aligned, preferably to first order, with an element of the second assembly 6, for example, alignment marks positioned on the second substrate 200 or in the interconnect stack 201. When the active stack 301 is gallium nitride-based and the lower conductive layer 102 is indium tin oxide (ITO), the second anode hole 345 can be etched by a BC13 plasma, selectively with respect to the indium tin oxide (ITO). Thus, it is easier to stop the etching of the second anode hole 345 on the lower conductive layer 102.The lower conductive layer 102 preferably has a thickness greater than or equal to 100 nm to absorb a change in thickness of the active stack 301, typically less than or equal to 300 nm.

[0095] In [Fig. 2E], a passivation layer is conformally deposited directly onto the hard mask 320, and onto the respective sides and bottoms of the through trenches 341, 342, 343 and the second anode hole 345. The passivation layer has substantially the same thickness on one upper face of the hard mask 320, on the respective sides and bottoms of the through trenches 341, 342, 343 and the second anode hole 345. Anode hole 345. The variation in thickness of the passivation layer is, for example, less than or equal to 10%, preferably less than 5%. Advantageously, the deposition of the passivation layer can be preceded by chemical cleaning, for example with TMAH and / or KOH.

[0096] In any section parallel to the (X, Y) plane at the flanks of the through trenches 341, 342, 343 and the second anode hole 345, the thickness of the passivation layer is such that any pair of opposing flanks is separated by two distinct parts of the passivation layer. The passivation layer may, for example, be made of alumina (Al₂O₃), silicon nitride (SiN), or aluminum nitride (Ni). In this example, the passivation layer is made of alumina (Al₂O₃) and has a thickness between 20 nm and 100 nm.

[0097] The passivation layer is then anisotropically etched perpendicular to the (X, Y) plane to obtain a lateral passivation layer 351. The etching can be a reactive dry etching. Preferably, it can be followed by chemical cleaning. During this etching substep, the portion of the passivation layer in contact with the anode and cathode connection pads 221, 222 and the additional connection pads 223 is completely removed. Similarly, the portion of the passivation layer in contact with the lower conductive layer 102 is completely removed. Preferably, the passivation layer is completely removed from the upper surface of the hard mask 320.

[0098] In [Fig. 2F], a thin layer is conformally deposited on the upper face of the hard mask 320, on the lateral passivation layer 351, and on the respective sides and bottoms of the through-cuts 341, 342, 343 and the second anode hole 345. In any section parallel to the (X, Y) plane at the sides of the through-cuts 341, 342, 343 and the second anode hole 345, the thicknesses of the passivation layer and the thin layer are such that any pair of opposing sides is separated by two distinct parts of the thin layer. The thin layer is in contact with the connecting pads 221, 222, 223 and the lower conductive layer 102. The thin layer is electrically conductive.

[0099] Next, the volumes defined by the thin layer inside the through trenches 341, 342, 343 and the second anode hole 345 are preferably completely filled with a metallic material. This step may, for example, include a substep of conformal deposition of a conductive seed layer, followed by growth of a metallic material by electrochemical deposition (ECD). The metallic material may be copper (Cu). The seed layer may consist of a titanium nitride (TiN) sublayer sandwiched between a titanium (Ti) sublayer and a copper (Cu) sublayer. The Ti sublayer is in contact with the thin sub-layer and with the TiN sub-layer. The Cu sub-layer is in contact with the TiN layer.

[0100] Next, the portion of the thin layer in contact with the hard mask 320, the portion of the lateral passivation layer 351 in contact with the hard mask, the excess metallic material located on an upper portion extending vertically from an upper face 301.1 of the active stack 301, and the hard mask 320 itself are removed. As a result, the n-type doped layer 101.2 is exposed.

[0101] Following this removal substep, a residual portion of the thin layer, a residual portion of the lateral passivation layer 351, and a residual portion of the metallic material are exposed on the upper face 301.1 of the active stack 301. This removal substep may include one or more chemical-mechanical polishing steps and optionally, one or more cleaning steps. The metallic material filling substep, followed by this removal substep, may include one or more conventional building blocks of a Damascus process.

[0102] Advantageously, the thin film is capable of reflecting a luminous flux at the emission wavelength Xi and / or the detection wavelength X2. The thin film can be, for example, made of aluminum (Al), aluminum-silicon alloy (AISi), or copper (Cu). The thickness of the thin film is, for example, 80 nm at the sides of the through-cuts 341, 342, 343 and the second anode hole 345, and 300 nm on the upper face of the hard mask 320.

[0103] Following the step in [Fig. 2F], the residual portion of the thin layer constitutes a coating 352. The residual portions of the metallic material inside the through-cuts 341, 342, 343 and the second anode hole 345 each constitute a metallic filler 353. Each metallic filler 353, in association with a portion of the coating 352 of a corresponding through-cut 341, 342, 343, constitutes an electrically conductive via 355, 359 or a conductive trench 358 in physical contact with one of the connection pads 221, 222, 223. Thus, an anode via 355, a conductive trench 358, and additional vias 359 are housed respectively in the first anode hole 341, the cathode trench 342, and the additional holes 343.The metallic filling 353 in association with the corresponding part of the lining 352 of a through trench 341, 342, 343 constitutes an electrically conductive anode contact 357 in physical contact with the lower conductive layer 102.

[0104] When the thin layer is reflective, the parts of the coating 352 facing the sides of the through trenches 341, 342, 343 and the second anode hole 345 each constitute a mirror.

[0105] In [Fig. 2G], an upper passivation layer 360 is formed on the upper face 301.1 of the active stack 301. The upper passivation layer The upper passivation layer 360 has openings that pass through it completely. A first opening is located opposite the detection surface 211 and the conductive trench 358, a second opening is located opposite the anode contact 357, and a third opening is located opposite the anode via 355. Preferably, the first opening covers the entire detection surface 211. Advantageously, the first opening covers the entire conductive trench 358. The upper passivation layer 360 can, for example, be made of silicon nitride (SiN) and have a thickness between 50 nm and 100 nm. The first, second, and third openings, and any additional openings that pass through the upper passivation layer 360, are collectively referred to hereafter as the upper openings.

[0106] Next, an upper conductive layer 361 is deposited on the upper passivation layer 360 and on a portion of the n-type doped layer 101.2 exposed in the upper openings. The upper conductive layer 361 is continuous and in physical contact with the n-type doped layer 101.2, the anode contact 357, and the anode via 355. It is transparent at the emission wavelength Xi and the detection wavelength X2. For example, it transmits at least 50% of incident light at normal incidence at the emission wavelength Xi and the detection wavelength X2, or preferably at least 90%, or even at least 95%. The top conductive layer 361 can be made of a metal oxide, for example indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), or tin dioxide (SnO2). In this example, the top conductive layer 361 is made of indium tin oxide (ITO) and has a thickness between 60 nm and 120 nm.A thickness between 100 nm and 120 nm provides satisfactory transmission and good electrical conductivity.

[0107] In [Fig.2H], a portion of the upper conductive layer 361 in contact with the anode contact 357 and the anode via 355 is isolated by etching to create a conductive line 356. The conductive line 356 is electrically isolated from the n-type doped layer 101.2 by the upper passivation layer 360. The upper conductive layer 361 is etched over its entire thickness, preferably in areas resting entirely on the upper passivation layer 360.

[0108] A remaining portion of the upper conductive layer 361 in contact with the n-type doped layer 101.2 in the first opening constitutes a surface electrode 370 of a light-emitting diode, which is here a cathode electrode 370 of the light-emitting diode. The cathode electrode 370 extends into a portion of the upper conductive layer 361 in contact with the conductive trench 358, preferably with an entire upper face of the conductive trench 358 flush with the upper face 301.1 of the active stack 301. Preferably, The cathode electrode 370 covers the entire surface of the n-type doped layer 101.2 exposed in the first opening. The portion of the lower conductive layer 102 in physical contact with the anode contact 357 constitutes a buried electrode 380 of the light-emitting diode, which is here an anode electrode 380 of the light-emitting diode. A portion of the cathode electrode 370, preferably the entire cathode electrode 370, is directly above the anode electrode 380.

[0109] The steps in Figures 2B to 2H lead to the formation of an active region of the light-emitting diode, arranged in the active layer 101.3. The geometries and relative positions of the cathode electrode 370 and the anode electrode 380 define the horizontal dimensions of the active region. Here, the anode electrode 380 and the cathode electrode 370 are delimited by the conductive trench 358. Consequently, the same is true of the active region. Thus, the formation of the conductive trench 358 contributes to the formation of the active region. Since the conductive trench 358 is aligned, preferably to a first approximation, with an element of the second assembly 6, the positioning of the active region relative to the detection surface 211 is precise. The same applies to the positioning of the anode via 355 and the anode contact 357 with respect to the detection surface 211 and the interconnection stack 201.

[0110] Figures 21 and 2J illustrate a final step of the first manufacturing process. They are views of the first embodiment of a first optoelectronic device 1 according to the invention. [Fig. 2J] is a top cross-sectional view along section plane BB of [Fig. 21]. [Fig. 2I] is a transverse cross-sectional view along section plane AA of [Fig. 2J].

[0111] In the final step, an optional encapsulation layer 375 is deposited on the upper passivation layer 360, the cathode electrode 370, and the conductive line 356. The encapsulation layer 375 may comprise one or more sublayers, for example, of a material selected from silicon dioxide (SiO₂) or silicon nitride (SiN). The encapsulation layer 375 may have a flat upper face on a portion opposite the second substrate 200. The final step may include a substep subsequent to the deposition of the encapsulation layer 375 for thinning the second substrate 200, for example, to expose vias extending deep into the second substrate 200 from its front face.

[0112] The first optoelectronic device 1 comprises a pixel 10. In the particular case of Figures 21 and 2J, the first optoelectronic device 1 comprises several identical pixels 10 arranged in a matrix. The matrix extends in a plane parallel to the plane (X, Y). Only one pixel 10 is represented on [Fig.2J]. This one is positioned on an edge of the pixel matrix.

[0113] Pixel 10 comprises a photodetector 210, a light-emitting diode, and an intermediate region 390 interposed between the photodetector 210 and the light-emitting diode. The photodetector 210 is here a photodiode, for example, a pinned photodiode. An upper surface of a doped region of the photodiode delimits the detection surface 211.

[0114] The light-emitting diode comprises the anode electrode 380 and a portion of the active stack 301 delimited by the cathode trench 342. The anode electrode 380 is also delimited by the cathode trench 342. The light-emitting diode further comprises the cathode electrode 370. The latter is delimited by the cathode trench 342 in the plane of the upper face 301.1 of the active stack 301.

[0115] The intermediate region 390 is a fictitious region extending from the detection surface 211 to the active stack 301. It has a base and a wall. The base is the detection surface 211, here located near the front face of the second substrate 200. The wall is parallel to the Z-axis. It can be a right prism or a right elliptical cylinder. The intermediate region 390 includes a through-part of the interconnect stack 201, a through-part of the bonding layer 303, and a through-part of the anode electrode 380. It is free of metallic elements.

[0116] The first optoelectronic device 1 includes an electrical path connecting the anode electrode 380 to the control circuit. The electrical path comprises the anode contact 357, the anode via 355, and the conductive line 356. The conductive line 356 is separated from the cathode electrode 370 by an insulating material, which may be air or, as shown here, a portion of the encapsulation layer 375. The conductive line 356 has a substantially rectangular shape in top view. In this example, the cathode electrode 370 surrounds the conductive line 356 in all directions of a plane parallel to the (X, Y) plane. Alternatively, the conductive line 356 can extend above the cathode trench 342, over a portion of the conductive trench 358 isolated by the upper passivation layer 360. In this case, it can electrically connect an anode contact 357 of a neighboring pixel 10.Preferably, the control circuit has components or connecting lines arranged under the anode connection pad 221, and / or under the anode contact 357, and / or under the conductive line 356. The components may, for example, be transistors or doped regions.

[0117] The conductive trenches 358 of two neighboring pixels 10 may be distinct. Alternatively, as in this particular example, the conductive trenches 358 Two neighboring pixels share a common area. Here, the conductive trenches of the pixel matrix form, in top view, a grid of orthogonal lines, delimited by external lines forming a rectangular or square frame. Each area between two neighboring intersections of the grid constitutes the common area of ​​the conductive trenches.

[0118] The cathode electrode 370 of a pixel can be electrically isolated from the cathode electrode 370 of one or more neighboring pixels. Alternatively, as shown in [Fig. 2J], several pixels 10, preferably all pixels 10, have a common cathode electrode 370, i.e. the cathode electrode 370 of one pixel 10 is electrically connected to the cathode electrodes 370 of other pixels 10, preferably all pixels 10, of the matrix by portions of the upper conductive layer 361.

[0119] Variants of the first embodiment will now be described with reference to Figures 3A to 3E. Only the differences from the first embodiment are explicitly described. These variants include additional features compared to the first embodiment, all of which can be combined to give rise to further variants within the scope of the invention.

[0120] Figure 3A describes a first useful variant, for example, when the region of the interconnect stack 201 facing the detection surface 211 includes non-metallic sublayers that are absorbing or reflective at the emission wavelength Xi and / or the detection wavelength X2, for example, one or more silicon nitride (SiN) sublayers. In this variant, prior to the transfer step of Figure 2A, a recess 410 is etched into the interconnect stack 201 facing the detection surface 211 to remove portions of absorbing sublayers. The recess 410 has sufficient dimensions to remove all parts of the absorbing sublayers directly above the detection surface 211. Preferably, as shown here, the recess 410 passes completely through the stack of interconnections 201. Advantageously, the entire detection surface 211 is opposite the recess 410.

[0121] The lower bonding layer 203 is a layer deposited after the engraving of the recess 410, completely filling the recess 410. It is possible, for example, to deposit a dielectric layer, for example a silicon oxide (SiO) of a thickness strictly greater than a depth along the Z direction of the recess 410, followed by polishing, for example a chemical mechano-polishing (CMP).

[0122] Fig. 3B describes a second variant incorporating a surface layer of optical function 430. The surface layer of optical function 430 is a layer deposited on the encapsulation layer 375 at the end of the step in Fig. 2I.

[0123] The surface layer with optical function 430 can, for example, be an antireflective layer 430 configured to obtain an antireflective function at the emission wavelength Xi and / or at the detection wavelength X2. The antireflective layer 430 can be a single layer or comprise several sublayers. The material and thickness of the layer or the materials and thicknesses of the sublayers are chosen, for example by simulation, to obtain the desired antireflective function.

[0124] For example, the antireflective layer 430 can be made of silicon nitride (SiN). It can have a thickness of between 50 nm and 65 nm, or between 175 nm and 190 nm or between 295 nm and 310 nm, this to obtain an antireflective function at an emission wavelength Xi of 365 nm, for an active stack 301 of gallium nitride (GaN), a top conductive layer 361 of indium tin oxide (ITO) of 100 nm thickness and an encapsulation layer 375 of silicon oxide (SiO). In combination with a 375 encapsulation layer thickness of less than 200 nm, the transmission of a luminous flux emitted by the light-emitting diode from the top face 301.1 of the active stack 301 is greater than 90%.The three thickness ranges of the above silicon nitride (SiN) antireflective layer 430, in combination respectively with encapsulation layer thickness ranges 375 between 100 nm and 150 nm, or between 140 nm and 170 nm, or between 50 nm and 150 nm, make it possible to obtain further a transmission rate of light flux incident on the antireflective layer 430 in the active stack 301 greater than 90% at a detection wavelength X2 equal to 630 nm.

[0125] The surface layer with optical function 430 can be an absorbing surface layer at the emission wavelength Xp. The absorbing surface layer has a through-hole (not shown in [Fig. 3B]) with respect to the active region of the light-emitting diode and extends over an area of ​​the encapsulation layer 375 opposite a region between two neighboring pixels 10. In this particular example, it also extends over an area of ​​the encapsulation layer 375 opposite the conducting line 356. Thus, a luminous flux emitted by a light-emitting diode of a pixel 10 guided by the encapsulation layer 375 is attenuated, and crosstalk can be avoided.

[0126] In [Fig. 3B], optional pads 440 are shown. The pads 440 pass completely through the encapsulation layer 375 directly above a corresponding additional via 359. The pads 440 are made of an electrically conductive material. In the presence of a surface layer with optical function 430, as shown here, they They can pass through it completely or be arranged in a through-opening made in the surface layer of optical function 430. The pads 440 can be any number greater than or equal to 1. When the first optoelectronic device 1 has a pixel matrix 10, they can be arranged in a peripheral part of the pixel matrix 10. This can, for example, be pads 440 used for the electrical testing of the first optoelectronic device 1, for example before individualization of the first optoelectronic device 1 by cutting a second substrate 200 containing several first optoelectronic devices 1.

[0127] Figure 3C describes a third variant incorporating an intermediate optical function layer 420 within the bonding layer 303. The intermediate optical function layer 420 is a sublayer of the upper bonding layer 103 or the lower bonding layer 203, or the intermediate optical function layer 420 may be formed by combining sublayers in the upper and lower bonding layers 103 and 203. This third variant can be advantageous when the photodetector 210 is sensitive to both the emission wavelength Xi and the detection wavelength X2 and is intended to operate simultaneously with the light-emitting diode. The photodetector 210 is thus not dazzled by the light-emitting diode.

[0128] The detection surface 211 of at least one pixel 10, preferably all pixels 10, is entirely opposite the intermediate optical function layer 420, i.e. the intermediate region 390 comprises at least part of the intermediate optical function layer 420. When the intermediate optical function layer 420 is integrated into the lower gluing layer 203, it is possible to etch openings through the intermediate optical function layer 420 directly above the detection surface 211 of some pixels 10.

[0129] The intermediate optical function layer 420 can be an interference filter. The interference filter can, for example, be configured to increase the ratio of a transmission of a luminous flux at the detection wavelength X2 to a transmission of a luminous flux at the emission wavelength Xp. For an emission wavelength Xi in the UVA range and a detection wavelength X2 in the visible spectrum, the intermediate optical function layer 420 can comprise an alternation of silicon nitride (SiN) and silicon oxide (SiO) sublayers, for example 9 SiN / SiO bilayers, the thickness of the silicon nitride (SiN) sublayers can, for example, be equal to 44 nm and the thickness of the silicon oxide (SiO) sublayers can, for example, be equal to 62 nm.

[0130] The intermediate optical function layer 420 can be a reflective layer. The reflective layer can, for example, be a quarter-wave plate independent of the polarization of the light, for example at the emission wavelength Xi. Thus, the ratio of the transmission of a light flux at the detection wavelength X2 to the transmission of a light flux at the emission wavelength Xi is increased. The quarter-wave plate can be made of amorphous silicon. If so, the quarter-wave plate can result from the assembly of upper and lower bonding layers 103, 203 comprising amorphous silicon on their faces to be joined by atomic diffusion bonding (ADB). The quarter-wave plate made of amorphous silicon can, for example, have a thickness of 19.2 nm.

[0131] The intermediate layer with optical function 420 can be an absorbing layer, for example made of amorphous silicon with a thickness of 100 nm.

[0132] Figure 3D describes a fourth variant incorporating the features of the variant in Figure 3B and further integrating an antireflective window 435 arranged opposite the detection surface 211. The intermediate region 390 includes the antireflective window 435. The antireflective window 435 is, for example, in contact with the front face of the second substrate 200. It has an optical layer that has an antireflective function at the detection wavelength X2. This can be, for example, a layer structured in tantalum oxide (Ta2O5), alumina (Al2O3), silicon nitride (SiN), or titanium oxide (TiO2).For a detection wavelength X2 of 630 nm, a silicon (Si) photodiode passivated by a 15 nm thick alumina (Al12O3) layer interposed between and in contact with the antireflective window 435 and the photodiode, the antireflective window 435 can, for example, be made of tantalum oxide (Ta2O5) and have a thickness greater than 70 nm, for example equal to 105 nm. It can also be made of silicon nitride (SiN) and have a thickness between 410 nm and 430 nm.

[0133] Fig. 3E describes a fifth variant incorporating the anti-reflective window 435 introduced in Fig. 3D and a heating element 432. The anti-reflective window 435 is optional here.

[0134] For this variant, at the end of the step in [Fig. 2I], a through-hole is etched through the encapsulation layer 375 with respect to an additional via 359. An additional conductive layer of an electrically conductive material is then conformally deposited in a bottom and on a side of the hole and on the upper face of the encapsulation layer 375. The additional conductive layer is in contact with the additional via 359 and extends continuously from the additional via 359 towards the upper face of the encapsulation layer. 375. It is then engraved over its entire thickness with respect to the active region of the light-emitting diode to obtain the heating element 432.

[0135] The heating element 432 has a through-hole with respect to the active region of the light-emitting diode and, preferably, extends over a surface of the encapsulation layer 375 opposite a region between two neighboring pixels 10. In this particular example, it also extends over a surface of the encapsulation layer 375 opposite the conductive line 356.

[0136] The heating element 432 is capable of heating by Joule effect when an electric current passes through it via the additional via 359. The electric current can be controlled by the control circuit, for example to stabilize a surface temperature of the first optoelectronic device 1 or to perform a thermal cycle. For example, it is capable of heating to a temperature of 55 °C. The heating element 432 can also perform the function of the absorbent surface layer of [Fig. 3B].

[0137] The additional conductive layer can, for example, be made of titanium nitride (TiN), thus providing both Joule heating and crosstalk reduction. It can, for example, have a thickness of 100 nm.

[0138] Optionally, the heating element 432 can be electrically connected to a pad 440 by a portion of the additional conductive layer extending the heating element into an opening etched in the encapsulation layer 375 and the upper passivation layer 360, as shown in [Fig.3E].

[0139] A variant of the first method leading to a sixth variant of the first optoelectronic device 1 will now be described with reference to Figures 4A and 4B. Only the differences compared to the first method and the first device are explained. The variant of the first optoelectronic device 1 illustrated in [Fig. 4B] incorporates the additional and optional features of the second variant in [Fig. 3B]. These can be combined with one or more features from among all the features described with reference to the other variants.

[0140] The transfer step of [Fig. 2A] is carried out with the second assembly 6 of [Fig. 4A]. The photodetector 210 is here integrated at least partially in and / or on a third substrate 205. The third substrate 205 has an additional interconnection stack 206 in contact with a front face of the third substrate 205. The photodetector 210 is here a photodiode flush with the front face of the third substrate 205. The third substrate 205 is transferred onto the interconnection stack 201, for example by hybrid metal-oxide bonding of the additional interconnection stack 206 onto the interconnection stack 201, as shown here. The intermediate region 390 extends from the photodiode to the active stack 301 and includes a portion of the third substrate 205, a It consists of part of the bonding layer 303 and part of the lower conductive layer 102. It has a base and a wall. The base is the detection surface 211, here located in the third substrate 205. The wall is parallel to the Z-axis. It can be a right prism or a right elliptical cylinder. The intermediate region 390 is metal-free.

[0141] The third substrate 205 preferably has the same dimensions as the second substrate 200 in a plane parallel to the (X, Y) plane. It may be made of the same or a different material than the second substrate 200. The material of the third substrate 205 may, for example, be silicon (Si), germanium (Ge), or gallium-indium arsenide (InGaAs).

[0142] At the step in [Fig.2B], the formation of the anode aperture 331 and the cathode aperture 332 may include a photolithography substep aligned, preferably to the first order, on an element of the second set 6, for example alignment marks arranged on the front face of the second substrate 200, in the interconnection stack 201, in the additional interconnection stack 206 or on the front face of the third substrate 205.

[0143] At the stage of [Fig.2C], the through trenches 341, 342, 343 extend through the third substrate 205 and the additional interconnection stack 206, to the connection pads 221, 222, 223.

[0144] A second manufacturing process leading to a second optoelectronic device 2 will now be described with reference to Figures 5A to 5D. Only the differences compared to the first process and the first device are described. It is possible to combine one or more features from among all the features described with reference to the variants of the first optoelectronic device 1 with this embodiment.

[0145] For this second process, the steps of Figures 2A to 2E of the first process are carried out first.

[0146] In [Fig. 5A], an additional cathode aperture 336 is etched into the hard mask 320. The additional cathode aperture 336 passes completely through the hard mask 320 and exposes an upper part of the n-type doped layer 101.2. The additional cathode aperture 336 is arranged with respect to the second anode hole 345 such that an imaginary line from one to the other has a portion opposite the detection surface 211. When the cathode trench 342 has a loop shape in a plane parallel to the (X, Y) plane, the additional cathode aperture 336 is arranged in a region enclosed by the cathode trench 342, as is the case here. Regardless of the shape of the cathode trench 342, the additional cathode opening 336 may have a loop shape in a plane parallel to the (X, Y) plane, as in this example. If so, it may For example, having an elliptical, circular, rectangular, or, as here, square shape in the plane. In the case of a gallium nitride (GaN) type n 101.2 doped layer, a loop shape of the additional cathode aperture 336 is advantageous for a large pixel 10, for example, larger than 50 pm, or even 100 pm.

[0147] In [Fig. 5B], a conductive layer 552 is conformally deposited on an upper face of the hard mask 320, on the lateral passivation layer 351, on the bottoms of the through-trenches 341, 342, 343, in contact with the connecting pads 221, 222, 223, and in the additional cathode aperture 336, in contact with the n-type doped layer 101.2. The conductive layer 552 is capable of conducting electricity. Advantageously, it is made of a metal. Preferably, it is reflective at the emission wavelength Xi and / or at the detection wavelength X2.

[0148] The conductive layer 552 can be made of aluminium (Al), aluminium-silicon alloy (AISi), aluminium-copper alloy (AlCu), tungsten (W) or titanium (Ti).

[0149] In [Fig. 5C], the conductive layer 552 is etched throughout to isolate a conductive line 356, in contact with the upper face of the hard mask 320, from a surface electrode 370, in contact with the exposed part of the doped layer of type n 101.2. The surface electrode is here a cathode electrode 370. The conductive line 356 and the cathode electrode 370 are two distinct parts of the conductive layer 552 isolated by the etching. The cathode electrode 370 is by definition restricted to the part of the conductive layer 552 in contact with the n-type doped layer 101.2 in the additional cathode opening 336. Following this step, the conductive line 356 extends into an anode contact 357 consisting of a part of the conductive layer 552 in contact with the lower conductive layer 102, arranged in the second anode hole 345.It also extends into an anode via 355 consisting of a portion of the conductive layer 552 in contact with the anode connection pad 221, arranged in the first anode hole 341. The cathode electrode 370 extends into a conductive trench 358 consisting of a portion of the conductive layer 552 in contact with the cathode connection pad 222, arranged in the cathode trench 342. The conductive line 356, the anode contact 357, and the anode via 355 together constitute an electrical path electrically connecting the control circuit to the anode electrode 380. The electrical path is electrically isolated from the active stack 301 by the hard mask 320 and the lateral passivation layer 351.

[0150] The conducting line 356 here has a substantially rectangular shape in top view ([Fig. 5D]). Also in this example, it is surrounded by the cathode electrode 370 which is itself surrounded by the conducting trench 358.

[0151] In the case where the second optoelectronic device 2 has pads 440, these can rest on portions of the conductive layer 552 resting on the upper face of the hard mask 320, electrically insulated from the conductive line 356, the cathode electrode 370, the anode via 355, the anode contact 357, and the conductive trench 358 by etching. The encapsulation layer 375 can fill empty volumes in the through trenches 341, 342, 343, the additional cathode aperture 336, and the second anode hole 345, if applicable.

[0152] Specific embodiments have just been described. Various variations and modifications will become apparent to a person skilled in the art. For example, a person skilled in the art could use a layer of organic adhesive 303 when transferring the first assembly 5 onto the second assembly 6, for example, a layer of silicone or a layer of polyimide.

Claims

1. Demands Optoelectronic device (1,2), comprising: • a substrate (200); • a control circuit integrated in and / or on the substrate (200) comprising an interconnect stack (201); • a matrix of at least one pixel (10), each pixel (10) comprising a photodetector (210), a light-emitting diode and an intermediate region (390) interposed between the photodetector (210) and the light-emitting diode, and each pixel being such that: • the photodetector (210) is sensitive to a detection wavelength X2 and comprises a detection surface (211) extending in a plane substantially parallel to a principal plane of the substrate; • The light-emitting diode comprises: • an active stack (301) with a cutoff wavelength Xc lower than the detection wavelength X2 comprising a first and second doped layers (101.2, 101.4) of opposite types, • a buried electrode (380) in contact with the second doped layer (101.4), • the light-emitting diode being arranged in such that the buried electrode is interposed between the interconnect stack (201) and the active stack (301), and covers the sensing surface, and such that: • the intermediate region (390) is delimited by the detection surface and extends from the detection surface to the active stack (301), the optoelectronic device (1) being characterized in that it further comprises: • a via (355) passing through the active stack (301) and extending to an interconnection level of the interconnection stack (201); • an electrical contact (357) passing through the active stack (301), in contact with the buried electrode (380); • an electrical path electrically connecting the buried electrode (380) to the control circuit and comprising the through electrical contact (357) and the via (355); and in that: • the intermediate region (390) is free of metal • the buried electrode is transparent to the detection wavelength X2.

2. Optoelectronic device (1,2) according to claim 1, such that for each pixel, the light-emitting diode comprises: • an active region extending between the first and second doped layers (101.2, 101.4) in a plane substantially parallel to the principal plane; • a conductive trench (358) surrounding the active region and the intermediate region (390), passing through the active stack (301) and extending to an interconnection level of the interconnection stack (201); and • a surface electrode (370) in contact with the first doped layer (101.2), electrically connected to the control circuit by the conductive trench (358).

3. Optoelectronic device (1,2) according to claim 2, wherein the conductive trench (358) is coated with a mirror.

4. Optoelectronic device (1,2) according to claims 2 or 3, wherein the matrix comprises several pixels (10), and the surface electrode (370) is an electrode common to all pixels (10).

5. Optoelectronic device (1,2) according to claim 4, wherein the conductive trenches (358) of two neighboring pixels (10) have a common part.

6. Optoelectronic device (1,2) according to any one of the preceding claims, wherein the intermediate region (390) includes an intermediate layer of optical function (420, 435) extending parallel to the main plane of the substrate.

7. Optoelectronic device (1,2) according to any one of the preceding claims wherein, for each pixel (10), the buried electrode (380) is made of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO) or tin dioxide (SnO2).

8. Optoelectronic device (1) according to any one of claims 2 to 7 wherein, for each pixel (10), the surface electrode (370) is made of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO) or tin dioxide (SnO2).

9. Optoelectronic device (1,2) according to any one of the preceding claims further comprising a surface layer of optical function (430, 432) disposed on a face of the optoelectronic device (1) opposite the substrate (200).

10. Optoelectronic device (1,2) according to claim 9, wherein the surface layer of optical function (432) is an absorbing layer having an opening opposite the detection surface (211).

11. Optoelectronic device (1,2) according to any one of the preceding claims, further comprising a heating element (432) disposed on a face of the optoelectronic device (1,2) opposite the substrate (200), the heating element (432) having an opening opposite the sensing surface (211).

12. Optoelectronic device (1,2) according to any one of the preceding claims wherein, the detection wavelength X2 belongs to the visible spectrum and the light-emitting diode is capable of emitting a luminous flux in the UVA range.

13. A method for manufacturing an optoelectronic device (1, 2) according to any one of claims 1 to 12 comprising a light-emitting diode and a photodetector (210) sensitive to a detection wavelength X2, the method comprising the following steps: • supplying a first assembly (5) comprising, in order, a first substrate (100), a semiconductor stack (101) and a lower conductive layer (102), wherein the semiconductor stack (101) comprises a first doped layer (101.2) of a first type of conductivity and a second doped layer (101.4) of a second type of conductivity opposite to the first type of conductivity, interposed between the first doped layer (101.2) and the first substrate (100), and wherein the lower conductive layer (102) is in physical contact with the second doped layer (101.4), provision of a second assembly (6) comprising a second substrate (200), a control circuit and the photodetector (210), wherein the control circuit is integrated in and / or on the second substrate (200) and comprises an interconnect stack (201), transfer of a face of the first assembly opposite to the first substrate (100) onto a face of the second assembly opposite to the second substrate (200) by direct bonding employing a bonding layer (303) transparent to the detection wavelength X2, exposing the first doped layer (101.2) by removing the first substrate (100), to obtain an active stack (301) comprising the first doped layer (101.2) and the second doped layer (101.4), etching a first hole (341) implementing an alignment of the first hole (341) with respect to an element of the second set, such that the first hole (341) passes completely through the active stack (301) and extends to an interconnection level of the interconnection stack (201), etching a second hole (345) implementing an alignment of the second hole (342) with respect to an element of the second set, such that the second hole (345) passes completely through the active stack (301) with a stop on the lower conductive layer (102), passivation of the first hole (341) and the second hole (345) to obtain, respectively, a passivated first hole (341) and a passivated second hole (345), • filling the first and second passivated holes (341, 345) with a metal to obtain, respectively, a via (355) and an electrical contact (357), • formation of a conductive line (356) electrically isolated from the active stack (301) and in contact with the electrical contact (357) and the via (355), • formation of an active region of the light-emitting diode in the active stack (301) opposite a detection surface (211) of the photodetector (210), subsequent to the bonding step, implementing an alignment of the active region with respect to an element of the second assembly.

14. A manufacturing method according to claim 13 wherein the active region formation step comprises a substep of engraving a trench (342) through and through the active stack (301) and extending to an interconnection level of the interconnection stack (201).

15. A manufacturing method according to claims 13, or 14 wherein the bonding layer includes an intermediate layer of optical function (420, 435).

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