IMPROVED FIELD PLATE

Abstract

An integrated circuit comprises: a high-voltage semiconductor device comprising a first doped region, a second doped region, and a drift region located between the first doped region and the second doped region; a plurality of stacked metal layers; a metal structure overlapping the drift region; a field plate structure arranged between the metal structure and the drift region, the field plate structure comprising a set of floating field plates, and a pair of field plates, comprising first and second field plates, the pair of field plates overlapping the set of floating field plates; and the first field plate and the second field plate are separated by a gap, the gap being diagonally arranged on the drift region. [Fig. 4B]

Description

Title of the invention: IMPROVED FIELD PLATE Technical field

[0001] The invention relates to improved field plates, and in particular to improved field plates in integrated circuits with a high voltage semiconductor device.

[0002] CONTEXT OF THE INVENTION

[0003] Lateral high voltage (HV) semiconductor devices in integrated circuits are used for AC / DC converters and power switches. For example, double lateral diffused MOS transistors (LDMOS) are used for high voltage (HV) applications in integrated circuits. The reliability and breakdown characteristics of LDMOS depend on the drift region (the lightly doped region between the drain and the source). Metal lines located above the drift region can significantly alter the electric field distribution there and, thus, reduce the breakdown voltage or have a negative impact on the device performance. This restricts the design freedom of the integrated circuit and may require off-chip connections (e.g., wire bonding).

[0004] Koicho Endo (Toshiba), "Power Semiconductor Integrated Circuit Device Without Concentration of Electric Field", US005315139A, June 1993, proposes a resistor placed between the HV drift region and the wiring layer passing above it. However, the resistor introduces an unwanted leakage current into the HV device when using existing layers of the given CMOS process, such as the poly-Si layer.

[0005] Akio Nakagawa et al. (Toshiba), “Planar Semiconductor Device having High Breakdown Voltage,” US005086332A, September 1989, describes how to reduce leakage using special semi-insulating polysilicon (SIPOS). However, SIPOS requires additional manufacturing steps and leakage remains significant, especially at high temperatures.

[0006] Tomohide Terashima (Mitsubishi), "Structure for Preventing Electric Field Concentration in Semiconductor Device", EP 00461877A2, December 1991, describes strips of field plates arranged so as to obtain a uniform electric field by capacitive coupling between them. A small metal line can then be passed over the field plates, if the capacitive coupling between this metal line and the field plates is negligible compared to the coupling between the field plates.

[0007] SUMMARY

[0008] Aspects of the invention relate to integrated circuits as described in the appended claims.

[0009] Alternatively, aspects of the invention may be defined by any of the following numbered paragraphs.

[0010] 1. Integrated circuit comprising:

[0011] a high voltage semiconductor device comprising a first doped region, a second doped region and a drift region located between the first doped region and the second doped region;

[0012] a plurality of stacked metal layers;

[0013] a metal structure overlapping the drift region;

[0014] a field plate structure arranged between the metal structure and the drift region, the field plate structure comprising:

[0015] a set of floating field plates, and

[0016] a pair of polarized field plates, the pair of polarized field plates overlapping the set of floating field plates.

[0017] 2. Integrated circuit according to paragraph 1, wherein said set of plates of floating fields are formed in a polysilicon layer or a first metal layer of said plurality of stacked metal layers.

[0018] 3. Integrated circuit according to paragraph 1 or 2, wherein said pair of plates polarized field layers are formed in a second metal layer of said plurality of stacked metal layers.

[0019] 4. Integrated circuit according to any one of the preceding paragraphs, in which the floating field plates have an extended dimension arranged substantially perpendicular to a current flowing through the drift region in use.

[0020] 5. Integrated circuit according to any one of the preceding paragraphs, in which the floating field plates have a rectangular shape.

[0021] 6. Integrated circuit according to paragraph 5, in which the rectangular shape has a short side whose dimension ranges from 1 pm to 5 pm, and a long side whose dimension ranges from 1 pm to 10 mm.

[0022] 7. Integrated circuit according to any one of the preceding paragraphs, in which the pair of polarized field plates comprises a first field plate electrically connected to a low voltage point, and a second field plate electrically connected to a high voltage point.

[0023] 8. Integrated circuit according to any one of the preceding paragraphs, in which the first field plate is electrically connected to the first doped region, and the second field plate is electrically connected to the second doped region.

[0024] 9. Integrated circuit according to any one of the preceding paragraphs, in which the first field plate and second field plate are separated by a space in the metal layer, and in which the gap is arranged diagonally across the drift region.

[0025] 10. Integrated circuit according to paragraph 9, in which the space has a width ranging from 0.5 pm to 5 pm.

[0026] 11. Integrated circuit according to any one of the preceding paragraphs, in which the pair of polarized field plates covers a substantially rectangular area, and wherein each of the first and second field plates has a triangular shape.

[0027] 12. Integrated circuit according to any one of the preceding paragraphs, in which the pair of polarized field plates is arranged relative to the set of floating field plates such that an electric potential increases substantially linearly from a first floating field plate located closest to the second doped region to a last floating field plate located closest to the first doped region.

[0028] 13. Integrated circuit according to any one of the preceding paragraphs, comprising in further one or more additional pairs of polarized field plates arranged on the drift region and overlapping the set of floating field plates.

[0029] 14. Integrated circuit according to paragraph 13, in which the space between the plates of field of the pair of polarized field plates and a gap between the field plates of the one or more additional pairs of polarized field plates together form a zigzag pattern on the drift region.

[0030] 15. Integrated circuit comprising:

[0031] a high voltage semiconductor device comprising a first doped region, a second doped region and a drift region located between the first doped region and the second doped region;

[0032] a plurality of stacked metal layers;

[0033] a metal structure overlapping the drift region; and

[0034] a field plate structure arranged between the metal structure and the drift region, said field plate structure comprising a metal layer defining a slot.

[0035] 16. Integrated circuit according to paragraph 15, wherein said slot separates the layer metallic in two parts and in which each part provides a continuous metallic cover over the drift region.

[0036] 17. Integrated circuit according to paragraph 15 or 16, wherein said metal layer is formed in one of said plurality of stacked metal layers.

[0037] 18. Integrated circuit according to paragraph 15, 16 or 17, wherein said layer metallic is located in Metal 4 or Metal 5 of said plurality of stacked metallic layers.

[0038] 19. An integrated circuit according to any one of paragraphs 15 to 18, wherein the slit has a width dimension ranging from 1 pm to 5 pm.

[0039] 20. An integrated circuit according to any one of paragraphs 15 to 19, wherein the slot has a longitudinal axis substantially perpendicular to a direction from said first doped region to said second doped region.

[0040] 21. An integrated circuit according to any one of paragraphs 15 to 20, wherein the slit is positioned substantially midway between said first doped region and said second doped region.

[0041] 22. An integrated circuit according to any one of paragraphs 15 to 21, wherein the slot is located under the metal structure.

[0042] 23. Integrated circuit according to paragraph 22, wherein said slot is the only slot, formed in said metallic layer, to be located under the metallic structure.

[0043] 24. Integrated circuit according to any one of the preceding paragraphs, wherein said metal structure completely covers said drift region.

[0044] 25. Integrated circuit according to any one of the preceding paragraphs, wherein said metal structure completely covers said field plate structure.

[0045] 26. Integrated circuit device comprising:

[0046] an integrated circuit according to any one of the preceding paragraphs;

[0047] a high voltage region comprising the high voltage semiconductor device of said integrated circuit; and

[0048] a low voltage region comprising a plurality of low voltage semiconductor devices;

[0049] and wherein said plurality of stacked metal layers comprises metal lines configured to provide electrical connections to the high voltage semiconductor device and the plurality of low voltage semiconductor devices.

[0050] Specific embodiments are described below with reference to the drawings. Brief description of the drawings

[0051] [Fig.l] shows a schematic top view of an integrated circuit;

[0052] [Fig.2A] shows a schematic section of an HV semiconductor device;

[0053] [Fig.2B] shows the same HT device, provided with a metal line in the fourth metal layer above the drift region;

[0054] [Fig.3] shows a schematic perspective view of a field plate structure;

[0055] [Fig.4A] shows a schematic top view of a field plate structure and a portion of an HV semiconductor device;

[0056] [Fig.4B] shows another schematic top view of the field plate structure;

[0057] [Fig.4C] shows a schematic section of the HT semiconductor device, including the field plate structure;

[0058] [Fig.5] shows a schematic top view of an HV device comprising a field plate structure;

[0059] [Fig.6] shows a schematic top view of a large area HV semiconductor device;

[0060] [Fig.7] shows a schematic top view of another field plate structure;

[0061] [Fig.8] shows a schematic section of an HV semiconductor device, comprising a field plate structure;

[0062] [Fig.9] shows a schematic section of an HV semiconductor device, comprising a field plate structure; and

[0063] Figures 10A and 10B show graphs representing the evolution of the breakdown voltage from drain to source. DETAILED DESCRIPTION

[0064] [Fig.l] shows a schematic top view of an integrated circuit 2 (e.g., an AC / DC converter) having an HT region 4 comprising two LDMOS transistors 6, including a source 8, a drain 10, and a drift region 12 therebetween. The integrated circuit 2 further comprises a low voltage (LV) region 14 comprising a plurality of BT devices 16. The HT regions 4 and BT 14 are formed on the same semiconductor wafer. The BT devices 16 are typically CMOS devices formed using conventional CMOS processes. The BT devices typically comprise transistors, diodes, resistors, and capacitors.

[0065] In order to avoid high electric field densities in the drift region 12, no metal lines or connections overlap this drift region 12. It is therefore necessary to provide external connections to the drain pad 10. These are, for example, often made by means of wire wiring to the metal connection pads. This involves additional manufacturing steps, longer connections and additional potential failure points.

[0066] [Fig.2A] shows a schematic section of an HT semiconductor device 18 (e.g., an LDMOS). This HT semiconductor device 18 may be the LDMOS transistor 6 described above in connection with [Fig.l]. The device 18 includes a source region 20, a drain region 22, and a drift region 24 therebetween. The device 18 includes a plurality of metal layers 26a to 26d (only the layers 26a to 26c are shown in Figures 2A and 2B, while layers 26a to 26d are shown in [Fig.4C]). The metal layers are: Metal 1 (Metal One) 26a (closest to the underlying semiconductor layer), Metal 2 (Metal Two) 26b, Metal 3 (Metal Three) 26c and Metal 4 (Metal Four) 26d. The metal layers 26a to 26d are typically formed using a back-end-of-line (BEOL) CMOS process to form a back-end stack. The metal layers 26a to 26d are separated by interdielectric layers (e.g., comprising silicon oxide) and connected by vias 28 passing through these interdielectric layers. The electric field lines 30 (dotted lines) are distributed substantially uniformly in and above the drift region 24.The active silicon layer, comprising the source 20 and drain 22 regions, is located on a substrate 25, which may for example be a silicon substrate or a silicon on insulator (SOI) substrate.

[0067] [Fig.2B] shows the same HV device 18, however provided with a metal line 32 in the third metal layer 26c (Metal 3) on the drift region 24. The metal line 32 distorts the electric field lines 30 and creates regions of high electric field density. Local regions of high field density can reduce the breakdown voltage. In the example illustrated, the metal line 32 is connected to the high terminal (corresponding to the drain region 22) of the lateral HV device and pushes the electric field towards the low terminal (corresponding to the source region 20), creating a region of high field density there.

[0068] To at least partially solve this problem, the present invention provides a field plate structure located between the drift region and any overlying metal line. This field plate structure protects the drift region and allows for a more uniform distribution of the electric field under the metal line.

[0069] [Fig. 3] shows a schematic perspective view of a field plate structure 34 and a graph of the voltage along a longitudinal direction (x) relative to this field plate structure 34. The field plate structure comprises a set of floating field plates 35 in a first layer 36 (e.g. Poly or Metal 1) and a pair of polarized field plates 38 overlapping the floating field plates 35 in a second layer 39 (e.g. Metal 1, Metal 2 or Metal 3). The pair of polarized field plates 38 comprises a first field plate 40 connected to a low voltage point (e.g. to the source) and a second field plate 42 connected to a high voltage point (e.g. to the drain).For example, if the floating field plates 35 are located in the Poly layer, the pair of polarized field plates may be located in the Metal 1 layer, and the metal routing may be located in the Metal 2 layer and above. If the floating field plates are located in Metal 1, the pair of . Polarized field plates 38 may be located in Metal 2 and the metal routing may be located in Metal 3 and above. The Poly layer is the same as the one in which the gate polysilicon is located. The floating field plates 35 may therefore be formed in the same process steps for deposition and patterning as for the device gate polysilicon.

[0070] The first and second field plates 40 and 42 have a substantially triangular shape and are separated by a gap 48. These triangular shapes have a right-angled corner and together cover a substantially rectangular area. The gap 48 extends diagonally across the set of floating field plates 35. The angle of the gap 48 relative to the length (x-axis) may range from 30° to 60°. The gap 48 may measure from 2 μm to 4 μm. Due to machining and manufacturing constraints, the substantially triangular shape may have a substantially flat or rounded end.

[0071] The floating field plate assembly 35 may comprise rectangular strips of metal or polysilicon. The strips are arranged in the lengthwise direction (x), with their longitudinal axis oriented in the widthwise direction (y). The extended dimension of the strips may be between 1 pm and 10 mm and generally spans the entire width of the underlying LDMOS. The gap or spacing between the strips may range from 0.5 pm to 5 pm.

[0072] As can be seen from the graph at the bottom of [Fig. 3], the voltage across the floating field plates 35 increases in the x direction. The first floating field plate 35 (far left) is largely covered by the first field plate 40 (connected to the low voltage point), while the last floating field plate 35 (far right) is largely covered by the second field plate 42 (connected to the high voltage point).

[0073] [Fig.4A] shows a schematic top view of a field plate structure 34 and a portion of an HV semiconductor device 18. The field plate structure 34 is shown transparently (by its contours), allowing the underlying semiconductor regions to be visualized. The field plate structure 34 may be the field plate structure 34 described in connection with [Fig.3] above. The device 18 includes a source region 20, a drain region 22, and a drift region 24 therebetween. The field plate structure 34 covers the drift region 24. It is apparent that a set of floating field plates 35 is arranged in the x-direction on the drift region 24, between the source region 20 and the drain region 22. The floating field plates 35 have a rectangular shape and their extended dimension is substantially oriented in the y-direction (the width direction of the drift region 24).The floating field plates 35 have a width of 46 (along x) and a spacing of 44. .

[0074] A pair of polarized field plates 38 are arranged on the floating field plates 35. The pair 38 comprises a first field plate 40 in the shape of a right triangle and a second field plate 42 in the shape of a corresponding right triangle. The first and second field plates are separated by a gap 48. A metal line 32 passes through the field plate structure 34.

[0075] [Fig.4B] shows the same schematic top view as [Fig.4A], but with opaque elements of the field plate structure 34 to illustrate their respective positions. For ease of understanding, Figures 4A and 4B show triangular field plates 40 and 42 that cover a larger area than the underlying floating field plates 35. However, in preferred embodiments, the pair of polarized field plates may be the same width as the set of floating field plates and cover substantially the same area over the drift region 24.

[0076] [Fig.4C] shows a schematic section of the HV semiconductor device 18 including the field plate structure 34 of Figs. 3, 4A and 4B. The HV device includes four stacked metal layers 26a to 26d (Metal 1 to Metal 4) separated by dielectric layers. The first metal layer 26a is directly connected to the source region 20 and the drain region 22. The floating field plates 35 are also located in the first metal layer 26a, and the pair of biased field plates 38 (including the first field plate 40 and the second field plate 42) is located in the second metal layer 26b. The metal line 32, on the drift region 24, is located in the third metal layer 26c. The metal line 32 may completely cover the drift region 24.The field plate structure also provides for the addition of further metal lines and routing in the fourth metal layer 26d, or even higher metal layer levels depending on the CMOS process employed. The advantage of this embodiment, and related embodiments, is that it allows for a complete metal covering on top of the device. For example, the metal line 32 and / or further metal lines or routing in the fourth metal layer 26d or higher metal layer levels may completely cover the drift region 24 and / or the floating metal plates 35 and / or the pair of biased field plates 38. The HT semiconductor device 18 includes or is located on a substrate 25. The substrate 25 may, for example, be a silicon-on-insulator (SOI), silicon-on-sapphire, or GaN-on-Si substrate.

[0077] The width of the pair of polarized field plates 38 (y direction) can be adjusted, to some extent, by adjusting the angle of the gap between the plates 40 and 42. However, for HV devices with dimensions in the millimeter range, the pair of polarized field plates 38 can be a unit cell repeated to cover a larger area. The space between plates of several unit cells can then form a zigzag pattern. The longitudinal dimension of the floating field plates 35 can be extended to cover the width (y-direction) of the drift region 24, and the number of floating plates 35 can be increased to cover the length (x-direction) of said drift region 24.

[0078] [Fig. 5] shows a schematic top view of a field plate structure 34 comprising two pairs of polarized field plates 38a and 38b, comprising respective plates 40a, 42a and 40b, 42b. The polarized field plates 38a, 38b overlap floating field plates 35. Neighboring plates (e.g., 40a and 40b) connected to the same voltage may be made from a single piece of a metal layer. That is, there may be no physical lines or markers between them.

[0079] [Fig. 6] shows a schematic top view of an HT semiconductor device 18 having a field plate structure 34. The device 18 has a multi-finger configuration comprising six fingers (SDSDSDS arrangement), but the field plate structure may be configured for a different device having a single finger (SD) or a different number of fingers. The HT semiconductor device 18 may be one of the LDMOS transistors 6 described above with reference to [Fig. 1]. The drift region 24 extends between the source region 20 and the drain region 22, connected to the source 8 and drain 10 contacts, respectively. Rows of pairs of biased field plates 38 are arranged to cover the drift region. The underlying floating field plates are not shown. The space 48 between the polarized field plates 38 comprises a zigzag pattern.In some embodiments, the field plate structure 34 covers substantially the entire HT semiconductor device 18, allowing for free metal routing on the device.

[0080] With the slit having this configuration, diagonally and in a straight line, a quasi-linear potential distribution in steps occurs (see for example the graph in [Fig.3] described above), giving rise to a substantially uniform electric field. A change in the shape of the slit allows a non-linear potential distribution. The resulting electric field can thus be freely adjusted. For example, the electric field can be moved to the left or to the right.

[0081] This may be particularly advantageous for covering curved portions of the drift region, such as the region surrounding drain 10 of [Fig.l] described above. In these racetrack-like ends of the drift region (also referred to as termination areas), achieving electric field uniformity may be difficult, but the field plate structure described herein provides a possible solution.

[0082] [Fig.7] shows a schematic top view of a semiconductor device HT 18 having a field plate structure 34. The field plate structure 34 comprises a set of floating field plates 35 and a pair of polarized field plates 38. The pair of polarized field plates 38 comprises a first field plate 40 connected to a low voltage point (e.g. the source) and a second field plate 42 connected to a high voltage point (e.g. the drain). The gap 48 between the field plates 40 and 42 has a curved shape, ensuring a non-linear variation of the potential at the floating field plates 35 in the x direction.

[0083] An alternative solution proposes a field plate structure comprising a metal layer on the drift region and provided with a substantially straight slot and not requiring underlying floating field strips. The slot divides the metal layer into two parts (two field plates), one being connected to the low voltage terminal and the other to the high voltage terminal of the HV semiconductor device. The length of the field plates preferably does not substantially exceed a height of the metal layer on the drift region. This solution may therefore be more efficient for devices whose drift region is of shorter length (corresponding to lower voltages). This limitation depends on the CMOS technology implemented, i.e. the number of metal layers and the thickness of the interlayer dielectric.

[0084] [Fig. 8] shows a schematic section of an HT device 52 comprising a field plate structure 54 comprising a metal layer 56 provided with a single slot 58, on the drift region 24, substantially in the middle thereof. Apart from the slot 58, the metal layer 56 covers the entire length of the drift region 24 (and may also cover the entire width of this region 24). The slot 58 is substantially perpendicular to the width direction (y) of the HT device 52. The field plate structure 54 is located in the third metal layer 26c (Metal 3), but, depending on the length of the drift region, it may be necessary to arrange it in a lower or higher metal layer (e.g. Metal 4 or Metal 5) or any other conductive layer such as poly-Si, to ensure a sufficiently uniform distribution of the electric field. The slit 58 may have a width of 1 pm to 5 pm.The field plate structure 54 is normally connected to the drain and source region by the underlying metal layers 26a to 26b and the vias 28.

[0085] The advantage of this embodiment, and related embodiments, is that it allows for a complete metal coating on top of the device. For example, the metal line 32 and / or other metal lines or routing in the fourth metal layer 26d, or higher levels of metal layers may completely cover the drift region 24 and / or the field plate structure 54.

[0086] [Fig. 9] shows a schematic cross-section of an HT semiconductor device 18 (e.g., an LDMOS), having a field plate structure 54 including a metal layer 56 with a single slot 58. The HT semiconductor device 18 may be the LDMOS transistor 6 described above in connection with [Fig. 1]. The device 18 includes a source region 20, a drain region 22, and a drift region 24 therebetween. The device 18 includes a plurality of metal layers 26a to 26d: Metal 1 (Metal One) 26a (closest to the underlying semiconductor layer), Metal 2 (Metal Two) 26b, Metal 3 (Metal Three) 26c, and Metal 4 (Metal Four) 26d. Metal layers 26a to 26d are typically formed using a back-end-of-line (BEOL) CMOS process to form a back-end stack.The metal layers 26a-26d are separated by interdielectric layers (e.g., comprising silicon oxide) and connected by vias 28 passing through the interdielectric layers. The field plate structure 54 provides a substantially uniform distribution of the electric field lines 30 (dotted lines) in and above the drift region 24.

[0087] Figures 10A and 10B show graphs representing the evolution of the drain-to-source breakdown voltage (BVdss) for the two different embodiments described above in comparison to a bare NMOS device (without field plate structure).

[0088] [Fig. 10A] plots A BVdss as a function of the voltage applied to a metal plate located in the fourth metal layer (Metal 4) on the drift region for a 155 V NMOS device. As can be seen, the embodiment implementing the set of floating field plates and a pair of biased triangular field plates as well as the embodiment implementing a central slot provide a significant improvement over the bare NMOS device. This effect is particularly noticeable at high voltage (155 V and 400 V on the graph).

[0089] [Fig. 10B] shows A BVdss as a function of the voltage applied to a metal plate located in the fourth metal layer (Metal 4) on the drift region for a 290 V NMOS device. In this case, the triangular field plate embodiment provides better performance than the center slot embodiment, but both of these embodiments are superior to a case without field plates.

[0090] The described embodiments allow for a complete metal coating on top of the device. This promotes improved design of high power devices. The described embodiments not only allow for the implementation work of small connecting wires for “signals” surrounded by large structures to protect them, but also allow to connect large metallic structures, polygons and / or complete layers to obtain a connection with low ohmic resistance and / or low thermal resistance.

[0091] Overall, the embodiments described herein provide an integrated circuit (IC) comprising a high voltage region comprising a high voltage semiconductor device (e.g., an LDMOS FET) comprising a first doped region, a second doped region, and a drift region located between the first and second doped regions, and a low voltage region comprising a plurality of low voltage semiconductor devices. The circuit further comprises a plurality of stacked metal layers (e.g., six metal layers) comprising metal lines configured to provide electrical connections to the high voltage semiconductor device and the plurality of low voltage semiconductor devices. A metal structure overlaps the drift region.The circuit further includes a field plate structure arranged between the metal structure and the drift region, the field plate structure including a set of floating field plates in a first layer and a pair of polarized field plates in a second layer, the pair of polarized field plates overlapping the set of floating field plates.

[0092] The device may be a lateral PIN diode, the first doped region of which is the N-type region which is a cathode region of the device, and the second doped region of which is the P-type region which is an anode region of the device. The device may also be an LDMOS transistor, in which the first doped region is a drain region and the second doped region is a source region. Alternatively, the device may be a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or another HV transistor, such as a lateral HV bipolar transistor. For a transistor, the first doped region may be a collector or drain region, and the second doped region may be an emitter or source region. For a diode, the first doped region may be a cathode region and the second doped region may be an anode region.The first doped region may be an N-type region connected to a high voltage (HV) point or terminal, and the second doped region may be a P-type doped region connected to a low voltage (LV) point or terminal. When the device is a bipolar device (e.g., an IGBT), the first and second doped regions may have the same doping type. For example, the first and second doped regions may both be P-type.

[0093] The metal structure may be a metal line or plate and may be indirectly connected to the first or second doped region. For example, the metal structure may be a wide (low resistance) metal line. carrying a high voltage to the first doped region (e.g., to the drain of an LDMOS). In order to reduce the resistance, the metal structure can cover a major part of the drift region. The metal structure could normally distort and concentrate the electric field lines in the drift region, thus negatively affecting the breakdown behavior of the high-voltage semiconductor device. The field plate structure between the metal line and the drift region mitigates this phenomenon and can ensure a uniform distribution of the electric field in the drift region.

[0094] The plurality of stacked metal layers may include Metal 1, Metal 2, Metal 3, Metal 4, Metal 5, and Metal 6; Metal 1 being closer to the underlying silicon and doped semiconductor regions. The device may include more or fewer metal layers, depending on the technology employed. For example, 28 nm CMOS technology may allow for up to twelve metal layers. Metal 6 may be the top metal layer, furthest vertically from the silicon. Metal 1 may be directly connected to the doped semiconductor regions (e.g., the first and second doped regions) and connected to Metal 2 and the other metal layers of said plurality by vias.

[0095] The first and second doped regions may be formed in a silicon active layer (e.g., an epitaxial silicon layer) on a substrate. The substrate may be a silicon substrate or an SOI substrate including a buried oxide (BOX) layer. In other embodiments, the substrate may be silicon on sapphire or GaN on Si.

[0096] The floating field plates may have an extended dimension, arranged substantially perpendicular to the current flowing through the drift region in use. For example, the floating field plates may be strips arranged perpendicular to the gap between the source and drain of a transistor. The drift region may include a substantially rectangular area with one side at a first interface with the first doped region and a second, opposite side at a second interface with the second doped region. The floating field plates may then be arranged parallel to the first and second sides. The floating field plates may have a substantially rectangular shape. Generally, all of the floating field plates in the assembly have the same dimensions. For example, each field plate may have the same width and length.The array may extend from above the second doped region to above the first doped region, thereby covering substantially the entire length of the drift region. The array may also be present only on the drift regions if the source and drain extend slightly into the drift regions. drift, thus forming short source and drain field plates. The extended dimension (along the y axis) of the floating field plates is at least sufficient to cover the metal structure over the drift region. Typically, the extended dimension ranges from 1 pm to 10 mm, depending on the width of the drift region. The rectangular shape has a small dimension (along x) ranging from 1 pm to 5 pm. A gap between neighboring floating field plates can range from 1 pm to 5 pm.

[0097] The pair of polarized field plates may include a first field plate electrically connected to a low voltage point and a second field plate electrically connected to a high voltage point. The pair of polarized field plates may include a first field plate electrically connected to the first doped region and a second field plate electrically connected to the second doped region. The first and second field plates are separated by a gap (e.g., a rectangular slot) in the second layer, and the gap may be arranged diagonally across the drift region. By "diagonal," it is meant that the gap forms an angle with the width dimension of the drift region. The drift region may include a rectangular area, and the gap may extend diagonally across this rectangular area, in a meandering or zigzag pattern.For example, in one embodiment, the gap extends from above one corner of the drift region to a diagonally opposite corner. The angle formed by the gap with a width direction of the drift region may range from 30 to 60 degrees. The gap may have a width ranging from 1 μm to 5 μm.

[0098] The pair of polarized field plates may cover a substantially rectangular area, for example, each of the first and second field plates having a substantially triangular shape (also referred to as a "wedge shape"). For example, each field plate in the pair may have the shape of a right triangle. The hypotenuses may face each other, forming a gap between them. Due to manufacturing constraints, the triangular shape may have flat or rounded ends. The edges of the triangular shape along the diagonal (e.g., the edge forming the hypotenuse) may be irregular. For example, the patterning may be constrained to linear movements along x and y, creating a stepped diagonal. The rectangular area may completely cover (except for the location of the gap) the underlying set of floating field plates.The pair of polarized field plates may be arranged relative to the set of floating field plates such that an electric potential increases substantially linearly from a first floating field plate located closest to the second doped region to a last floating field plate located closest to the first doped region.

[0099] The first layer (which includes the set of floating field plates) may be the Poly-Si, Metal 1, or Metal 2 layer of the plurality of stacked metal layers. For example, the set of floating field plates may be formed in the polysilicon layer (e.g., the same polysilicon layer used to form the gate Poly layer of a transistor), the metal layer closest to the underlying silicon, or the metal layer immediately after the closest to the underlying silicon, for example.

[0100] The second layer (which comprises the pair of polarized field plates) may be the Metal 1, Metal 2 or Metal 3 layer of said plurality of stacked metal layers (depending on the layer in which the floating field plates are located). The pair of polarized field plates is preferably located in the metal layer directly above the layer containing the floating field plates. However, there may not be any other metal layer between the first and second layers.

[0101] Other embodiments described herein may provide an integrated circuit (IC) comprising a high voltage region comprising a high voltage semiconductor device (e.g., an LDMOS FET) comprising a first doped region, a second doped region, and a drift region located between the first and second doped regions, and a low voltage region comprising a plurality of low voltage semiconductor devices. The circuit further comprises a plurality of stacked metal layers (e.g., six metal layers) comprising metal lines configured to provide electrical connections to the high voltage semiconductor device and the plurality of low voltage semiconductor devices. A metal structure is connected to the high voltage semiconductor device and overlaps the drift region.The circuit further comprises a field plate structure arranged between the metal structure and the drift region, the field plate structure comprising a continuous metal layer provided with a slot located under the metal structure. The second doped region can be connected to the low voltage region.

[0102] The slit separates the metal layer into two parts (two field plates). A first part may be connected to the first doped region and a second part to the second doped region. The two parts of the metal layer are continuous over the drift region, but other parts of the metal layer may be used and include other metal connections laterally spaced from the drift region. The slit is generally single and may be located substantially in the center of the drift region (e.g., equidistant from the source and drain). In other embodiments, the slit may be located between 40% and 60% of the center. The width of the slit may range from 1 to 5 μm, and is preferably between 2 μm and 4 μm.

[0103] The field plate structure may be located in Metal 4 or Metal 5 layers of the plurality of stacked metal layers. For example, the plurality of stacked metal layers may include six metal layers and the field plate structure may be located in the second metal layer from the top, while the metal structure may be located in Metal 6 (the top metal layer). The required height of the field plate structure depends on the length of the drift region. For a short drift region, a lower metal layer (e.g., Metal 2 or Metal 3) may be used, which provides greater freedom for metal routing because there are more metal layers available on the field plate structure. For a device having a long drift region, a taller metal layer may be required.The height of the field plate structure can be greater than or equal to half the length of the drift region.

[0104] Although specific embodiments of the invention have been described above, it is understood that the invention may be practiced otherwise than as described. The above descriptions are given for illustrative purposes and are not intended to be limiting. Those skilled in the art will understand that modifications may be made to the disclosed invention without departing from the scope of the claims below.

[0105] Each feature disclosed or illustrated in this specification may be incorporated into the invention, alone or in any suitable combination with any other feature disclosed or illustrated herein.

Claims

Claims

1. An integrated circuit comprising: a high-voltage semiconductor device comprising a first doped region, a second doped region, and a drift region located between the first doped region and the second doped region; a plurality of stacked metal layers; a metal structure overlapping the drift region; a field plate structure arranged between the metal structure and the drift region, the field plate structure comprising a set of floating field plates, and a pair of field plates, comprising first and second field plates, the pair of field plates overlapping the set of floating field plates; and the first field plate and the second field plate being separated by a gap, and the gap being diagonally arranged on the drift region.

2. The integrated circuit of claim 1, wherein said set of floating field plates is formed in a polysilicon layer or a first metal layer of said plurality of stacked metal layers.

3. An integrated circuit according to claim 1 or claim 2, wherein said pair of field plates are formed in a second metal layer of said plurality of stacked metal layers.

4. An integrated circuit according to any preceding claim, wherein the floating field plates have an extended dimension arranged substantially perpendicular to a current flowing through the drift region in use.

5. An integrated circuit according to any preceding claim, wherein the floating field plates have a rectangular shape.

6. An integrated circuit according to claim 5, wherein the rectangular shape has a short side whose dimension ranges from 1 pm to 5 pm, and a long side whose dimension ranges from 1 pm to 10 mm.

7. An integrated circuit according to any preceding claim, wherein the pair of field plates comprises a first field plate electrically connected to a low voltage point, and a second field plate electrically connected to a high voltage point.

8. An integrated circuit according to any preceding claim, wherein the first field plate is electrically connected to the first doped region, and the second field plate is electrically connected to the second doped region.

9. An integrated circuit according to any preceding claim, wherein the first field plate and the second field plate are formed from one of said plurality of stacked metal layers.

10. An integrated circuit according to claim 9, wherein the gap has a width ranging from 0.5 pm to 5 pm.

11. An integrated circuit according to any preceding claim, wherein the pair of field plates covers a substantially rectangular area, and wherein each of the first and second field plates has a triangular shape.

12. An integrated circuit according to any preceding claim, wherein the pair of field plates are arranged relative to the set of floating field plates such that an electric potential increases substantially linearly from a first floating field plate located closest to the second doped region to a last floating field plate located closest to the first doped region.

13. An integrated circuit according to any preceding claim, further comprising one or more additional pairs of field plates arranged on the drift region and overlapping the set of floating field plates.

14. The integrated circuit of claim 13, wherein the gap between the field plates of the pair of field plates and a gap between field plates of the one or more further pairs of field plates together form a zigzag pattern on the drift region.

15. An integrated circuit according to any preceding claim, wherein said pair of field plates are polarized field plates.

16. Integrated circuit comprising: a high voltage semiconductor device comprising a first doped region, a second doped region and a drift region located between the first doped region and the second doped region; a plurality of stacked metal layers; a metal structure overlapping the drift region; and a field plate structure arranged between the metal structure and the drift region, said field plate structure comprising a metal layer which is connected to said first and second doped regions and which defines a slot; the slot being located under the metal structure; and the slot being the only slot, formed in said metal layer, to be located under the metal structure.

17. Integrated circuit according to claim 16, wherein said slot separates the metal layer into two parts and wherein each part provides a continuous metal coverage over the drift region.

18. An integrated circuit according to claim 16 or 17, wherein said metal layer is formed in one of said plurality of stacked metal layers.

19. An integrated circuit according to claim 16, 17 or 18, wherein said metal layer is located in Metal 4 or Metal 5 of said plurality of stacked metal layers.

20. An integrated circuit according to any one of claims 16 to 19, wherein the slot has a width dimension ranging from 1 pm to 5 pm.

21. An integrated circuit according to any one of claims 16 to 20, wherein the slot has a longitudinal axis substantially perpendicular to a direction from said first doped region to said second doped region.

22. An integrated circuit according to any one of claims 16 to 21, wherein the slot is positioned substantially midway between said first doped region and said second doped region.

23. An integrated circuit according to any preceding claim, wherein said metal structure completely covers said drift region.

24. An integrated circuit according to any preceding claim, wherein said metal structure completely covers said field plate structure.

25. An integrated circuit device comprising: an integrated circuit according to any preceding claim; a high voltage region comprising the high voltage semiconductor device of said integrated circuit; and a low voltage region comprising a plurality of low voltage semiconductor devices; and wherein said plurality of stacked metal layers comprises metal lines configured to provide electrical connections to the high voltage semiconductor device and the plurality of low voltage semiconductor devices.

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