Quantum Box Matrix and Coupling Region Device

Abstract

QUANTUM BLOCK AND COUPLING REGION MATRIX DEVICE This description relates to an electronic device (100) comprising: - a semiconductor layer (102) comprising a quantum dot matrix (104) and coupling regions (106) each arranged between two adjacent quantum dots; - several first control grids (114), arranged side by side on the side of a first face (116) of the semiconductor layer; - several second control grids (122), arranged side by side on the side of a second face (124) of the semiconductor layer; in which the first control grids extend along their longest dimension parallel to a first axis and the second control grids extend along their longest dimension parallel to a second axis, and in which projections of the first and second axes into the same plane are intersecting. Figure for the summary: Fig. 2

Description

Title of the invention: DEVICE WITH A MATRIX OF QUANTUM DOTS AND COUPLING REGIONS Technical field

[0001] The present description relates generally to the field of quantum electronic devices and quantum computing. Prior art

[0002] There are quantum electronic devices comprising qubits based on the formation of quantum dots ensuring the confinement of elementary charges (electrons or holes) in a semiconductor. In these devices, the quantum information is, for example, coded on the spin of these charges. The confinement of the elementary charges in the quantum dots is achieved according to the three spatial dimensions of these dots (length, width and height). This confinement can be ensured structurally, for example by using an alternation of materials according to at least one dimension of space, and / or electrostatically, for example by applying an electric potential to a portion of conductive material.

[0003] Qubits can be arranged in a semiconductor layer in the form of a matrix, i.e., by forming a two-dimensional array of qubits in a principal plane of the semiconductor layer. Compared to a one-dimensional arrangement, such a matrix arrangement allows for better interconnectivity between nearest neighbor quantum dots, and thus allows for more efficient execution of quantum error correction algorithms, as described in the paper by A.G. Fowler et al., “Surface codes: Towards practical large-scale quantum computation,” Phys. Rev. A 86, 032324 (2012).

[0004] Several solutions have been proposed for superimposing two or three levels of gates through which electrical confinement potentials, or chemical potentials, of quantum dots are created in a semiconductor material. Such solutions are described for example in documents FR 3 066 297 A1, US 10 593 756 B2 or R. Li et al., “A crossbar network for Silicon quantum dot qubits”, Sci.Adv.4, July 6, 2018, Vol. 4, Issue 7 (2018). These gates make it possible to locally adjust the electrostatic potential of the quantum dots, i.e. the depth of the potential wells of the quantum dots, as well as the tunnel coupling, i.e. the height of the tunnel barriers or blocking sites, between neighboring quantum dots. These solutions all have at least some of the following drawbacks:

[0005] - too many lithographs to be implemented to produce the grids;

[0006] - etching step(s) to be implemented in the presence of significant topographies;

[0007] - electrostatic screening of the lower grid levels, which makes the structure very asymmetrical;

[0008] - need to move qubits to perform operations between them;

[0009] - large number of operations required per error correction code cycle. Summary of the invention

[0010] There is a need to propose an electronic device with a two-dimensional matrix of quantum dots which does not have at least some of the drawbacks previously described.

[0011] One embodiment overcomes all or part of these drawbacks and proposes an electronic device comprising:

[0012] - a semiconductor layer comprising a matrix of quantum dots and coupling regions each arranged between two adjacent quantum dots;

[0013] - several first control grids, arranged next to each other of the side of a first face of the semiconductor layer, covering at least a portion of the matrix of quantum dots and / or the coupling regions, and configured to each control the electrostatic potential of at least one of the quantum dots or of at least one of the coupling regions;

[0014] - several second control grids, arranged next to each other of the side of a second face, opposite the first face, of the semiconductor layer, covering at least a portion of the matrix of quantum dots and / or of the coupling regions, and configured to each control the electrostatic potential of at least one of the quantum dots or of at least one of the coupling regions;

[0015] wherein the first control grids extend along their largest dimension parallel to a first axis and the second control grids extend along their largest dimension parallel to a second axis, and wherein projections of the first and second axes in the same plane are intersecting.

[0016] According to a particular embodiment, the first and second control gates are configured such that, for each of the coupling regions, the first control gate arranged opposite said coupling region is adjacent to the first control gates arranged opposite the two neighboring quantum dots intended to be coupled to each other by said coupling region, and that the second control gate arranged opposite said coupling region is adjacent to the second control gates arranged opposite said two quantum dots.

[0017] According to a particular embodiment, the first control grids are aligned in a first direction perpendicular to a second direction in which the second control grids are aligned.

[0018] According to a particular embodiment, the semiconductor layer comprises holes passing through it and which are each arranged between two adjacent quantum dots arranged opposite the same first control gate and / or between two adjacent quantum dots arranged opposite the same second control gate.

[0019] According to a particular embodiment, each hole is arranged opposite a first control grid and a second control grid, each configured to control the electrostatic potential of at least one of the quantum dots.

[0020] According to a particular embodiment, the electronic device further comprises first electrical contact elements coupled to the first control grids and second electrical contact elements coupled to the second control grids, and the first and second electrical contact elements are arranged at the same face of the electronic device.

[0021] According to a particular embodiment, first electrical contact elements are coupled to ends of first conductive portions of the first control gates and arranged at different distances relative to a first edge of the semiconductor layer, and / or second electrical contact elements are coupled to ends of second conductive portions of the second control gates and arranged at different distances relative to a second edge of the semiconductor layer.

[0022] A method of producing an electronic device is also proposed, comprising at least the following steps: - production of several first control grids arranged next to each other on the side of a first face of a semiconductor layer comprising a matrix of quantum dots and coupling regions each arranged between two adjacent quantum dots, covering at least a part of the matrix of quantum dots and / or the coupling regions, and configured to each control the electrostatic potential of at least one of the quantum dots or of at least one of the coupling regions; - production of several second control grids, arranged next to each other on the side of a second face, opposite the first face, of the semiconductor layer, covering at least part of the matrix of quantum dots and / or the coupling regions, and configured to each control the electrostatic potential of at least one of the quantum dots or of at least one of the coupling regions;

[0023] wherein the first control grids extend along their largest dimension parallel to a first axis and the second control grids extend along their largest dimension parallel to a second axis, and in which projections of the first and second axes in the same plane are intersecting.

[0024] According to a particular embodiment, the method further comprises, between the production of the first control gates and the production of the second control gates, a production of holes passing through the semiconductor layer and each arranged between two adjacent quantum dots arranged opposite the same first control gate and / or between two adjacent quantum dots arranged opposite the same second control gate.

[0025] According to a particular embodiment, the semiconductor layer corresponds to at least part of a surface layer of a semiconductor-on-insulator type substrate.

[0026] According to a particular embodiment, the production of the first control grids comprises at least the implementation of the following steps:

[0027] - production of at least a first dielectric layer and a first layer conductive on the surface layer;

[0028] - etching of the first conductive layer such that the remaining portions of the first conductive layer and the first dielectric layer form the first control grids.

[0029] According to a particular embodiment, the method may further comprise, between the production of the first control grids and the production of the second control grids, the implementation of the following steps:

[0030] - production of a first encapsulation layer covering at least the first control grids;

[0031] - securing a mechanical support layer on the first layer encapsulation;

[0032] - removal of a support layer and a buried dielectric layer from the substrate, revealing a second face of the surface layer corresponding to the second face of the semiconductor layer.

[0033] According to a particular embodiment, the method further comprises, between the removal of the support layer and the buried dielectric layer and the production of the second control gates, a step of etching a part of the surface layer such that a remaining portion of the surface layer forms the semiconductor layer, or an oxidation of a part of the surface layer such that a non-oxidized portion of the surface layer forms the semiconductor layer.

[0034] According to a particular embodiment, the production of the second control grids comprises at least the implementation of the following steps:

[0035] - production of at least one second dielectric layer and a second layer conductive on the second face of the surface layer;

[0036] - etching of the second conductive layer and the second dielectric layer such that the remaining portions of the second conductive layer and the second dielectric layer form the second control gates.

[0037] According to a particular embodiment, the method further comprises the production of first electrical contact elements coupled to the first control grids through the first encapsulation layer, and the production of second electrical contact elements coupled to the second control grids through a second encapsulation layer previously deposited and covering the second control grids. Brief description of the drawings

[0038] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0039] - [Fig.l], [Fig.2], [Fig.3] and [Fig.4] represent different schematic views of an electronic device according to a particular embodiment;

[0040] - [Fig.5A], [Fig.5B], [Fig.6A], [Fig.6B], [Fig.7A], [Fig.7B], [Fig.8A], [Fig.8B], [Fig.9A], [Fig.9B], [Fig.10A], [Fig.10B], [Fig.11A], [Fig.11B], [Fig.12A], [Fig.12B], [Fig.13A], [Fig.13B], [Fig.14A] and [Fig.14B] represent steps of a method of producing an electronic device according to a particular embodiment. Description of the embodiments

[0041] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different examples and embodiments may have the same references and may have identical structural, dimensional and material properties.

[0042] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0043] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements. Furthermore, throughout the text, the terms "coupled" and "coupling" are used to designate an electrical coupling between at least two elements. Similarly, the term "conductor" is used to designate an electrical conduction. In the case of tunnel coupling, the term "coupling" refers to an overlap of particle wave functions.

[0044] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", "lateral", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", "diagonal", etc., reference is made, unless otherwise specified, to the orientation as shown in the figures in a normal position of use. However, these terms do not presume the actual position and orientation of the device during its use or manufacture.

[0045] Throughout the document, the terms "row" and "column" are used considering an arbitrary orientation of the device described, these terms being able to be interchanged depending on the arrangement of the device in space.

[0046] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0047] An example of an electronic device 100 according to a particular embodiment is described below in connection with [Fig.l] which is a schematic top view of the matrix of quantum dots and coupling regions of the device 100, with Figures 2 and 3 which are schematic sectional views of the device 100, and with [Fig.4] which is a schematic perspective view of the device 100.

[0048] The device 100 comprises a semiconductor layer 102 configured to form a matrix of quantum dots 104 and coupling regions, or tunnel barriers, 106. Each of the coupling regions 106 is arranged between two neighboring or adjacent quantum dots 102, and arranged, in the example of [Fig.l], diagonally.

[0049] For example, the semiconductor layer 102 may comprise silicon, or any other semiconductor suitable for forming the quantum dots 104 and the coupling regions 106 therein. The thickness of the semiconductor layer 102 (dimension parallel to the Z axis in the example of FIGS. 1 to 4) may be between 10 nm and 15 nm.

[0050] In the embodiment described, the semiconductor layer 102 is arranged on a support formed of a first dielectric layer 108, an oxide layer 109 (visually merging with the first dielectric layer 108 in FIGS. 2 to 4), a first encapsulation layer 110 and a mechanical holding layer 112. The first encapsulation layer 110 is arranged between the oxide layer 109 and the mechanical holding layer 112, and the oxide layer 109 is arranged between the first dielectric layer 108 and the encapsulation layer 110. For example, the first dielectric layer 108 may comprise silicon oxide, or any other dielectric material suitable for forming a gate oxide, and its thickness (dimension parallel to the Z axis in the example of FIGS. 2 to 4) may be between 3 nm and 10 nm. The oxide layer 109 may comprise, for example, silicon oxide and its thickness may be equal to 5 nm or more generally between 5 nm and 15 nm. The first encapsulation layer 110 may comprise at least one dielectric material such as silicon oxide and its thickness (dimension parallel to the Z axis in the example of FIGS. 2 to 4) may be between 100 nm and 200 nm. The mechanical retaining layer 112 may comprise silicon and its thickness (dimension parallel to the Z axis in the example of FIGS. 2 to 4) may be, for example, equal to 725 pm.

[0051] The oxide layer 109 is an optional layer for spacing the encapsulation layer 110 from the semiconductor layer 102. Such spacing may be advantageous when the material(s) used to form the encapsulation layer 110 contain charged defects that are preferable not to have as close as possible to the qubits. However, the device 100 may not include this oxide layer 109.

[0052] In Figures 2 to 4, although the first encapsulation layer 110 is shown as being thicker than the mechanical retaining layer 112, the latter may actually be thicker than the first encapsulation layer 110.

[0053] The device 100 further comprises several first control gates 114 arranged next to each other on the side of a first face 116 of the semiconductor layer 102. In the example shown in FIGS. 1 to 4, the first control gates 114 are formed by portions of materials extending substantially parallel to the Y axis, that is to say having their length, or their largest dimension, parallel to the Y axis. In the example of [Fig. 1], the first control gates 114 form several lines extending parallel to each other.

[0054] The first control grids 114 are each configured to control the electrostatic potential of at least one of the quantum dots 104 or of at least one of the coupling regions 106. In the example of FIGS. 1 to 4, taking into account the dimensions of the matrix of quantum dots 104 and coupling regions 106 and the large number of quantum dots 104 and coupling regions 106, each of the first control grids 114 is configured to control the electrostatic potential of several quantum dots 104 arranged on the same row of the matrix or of several coupling regions 106 arranged on the same row of the matrix.

[0055] Furthermore, in the example shown in Figures 1 to 4, each of the first control gates 114 that is configured to control the electrostatic potential of several coupling regions 106 is disposed between two other first control gates 114 that are adjacent to it and that are configured to control the electrostatic potential of several quantum dots 104. In addition, in this example, each pair of first control gates 114 configured to control the electrostatic potential of quantum dots 104 arranged on two neighboring lines of quantum dots 104 are separated from each other by a first control gate 114 configured to control the electrical potential of coupling regions 106 intended to control the coupling, or the tunnel barriers, between these quantum dots 104. Thus, in the example described in connection with FIGS. 1 to 4, parallel to the X axis, that is to say perpendicular to the direction in which the first control gates 114 extend, those configured to control the electrostatic potential of the quantum dots 104 and those configured to control the electrostatic potential of the coupling regions 106 are arranged alternately next to each other.

[0056] Each of the first control gates 114 comprises a gate dielectric which, in the example described in connection with FIGS. 2 to 4, is formed by the first dielectric layer 108.

[0057] Furthermore, in the example described, each of the first control gates 114 further comprises a first conductive portion 118 arranged against the first dielectric layer 108. Each of the first conductive portions 118 has, for example, an elongated shape extending substantially parallel to the Y axis. The first conductive portions 118 may comprise, for example, polysilicon or any other conductive material suitable for forming gate conductors.Each of the first conductive portions 118 has for example a width (which corresponds to the smallest dimension of each of the conductive portions 118 in a plane parallel to the first face 116 of the semiconductor layer 102) of between 15 nm and 30 nm, and a length (which corresponds to the largest dimension of each of the conductive portions 118 in a plane parallel to the first face 116 of the semiconductor layer 102) which depends on the dimensions of the matrix of quantum dots 104 and coupling regions 106. In addition, each of the first conductive portions 118 has for example a thickness, or height (which corresponds to the dimension perpendicular to the first face 116 of the semiconductor layer 102) of between 15 nm and 30 nm.

[0058] In the embodiment shown in Figures 2 to 4, first dielectric portions 120 are arranged against the first conductive portions 118 such that each of the first conductive portions 118 is arranged between the first dielectric layer 108 and one of the first dielectric portions 120. These first dielectric portions 120 correspond to the mask used for producing the first conductive portions 118 and comprise, for example, silicon nitride.

[0059] Alternatively, the device 100 may not include these first portions di electrical 120, for example when the etching mask is removed after etching forming the first conductive portions 118.

[0060] In the embodiment shown in FIGS. 2 to 4, the first control gates 114 are encapsulated in the first encapsulation layer 110 which covers the first conductive portions 118, the first dielectric portions 120 and possibly the oxide layer 109.

[0061] The device 100 further comprises several second control gates 122 arranged next to each other on the side of a second face 124 of the semiconductor layer 102. In the example shown in FIGS. 1 to 4, the second control gates 122 are formed by portions of materials extending substantially parallel to the axis X. Thus, in the example described, the first control gates 114 are aligned in a first direction, or orientation, substantially perpendicular to a second direction, or orientation, in which the second control gates 122 are aligned. Alternatively, the angle formed between the alignment directions of the first and second control gates 114, 122 may not be a right angle, but in all cases this angle is not zero.In other words, the first control grids 114 extend along their largest dimension parallel to a first axis and the second control grids 122 extend along their largest dimension parallel to a second axis, and in which projections of the first and second axes in the same plane are intersecting (and therefore necessarily not coincident).

[0062] Like the first control gates 114, the second control gates 122 are each configured to control the electrostatic potential of at least one of the quantum dots 104 or of at least one of the coupling regions 106. In the example of FIGS. 1 to 4, taking into account the dimensions of the matrix of quantum dots 104 and coupling regions 106 and the large number of quantum dots 104 and coupling regions 106, each of the second control gates 122 is configured to control the electrostatic potential of several quantum dots 104 or of several coupling regions 106.

[0063] Furthermore, in the example shown in Figures 1 to 4, each of the second control gates 122 that is configured to control the electrostatic potential of several coupling regions 106 is disposed between two other second control gates 122 adjacent thereto and configured to control the electrostatic potential of several quantum dots 104. Furthermore, in this example, each pair of second control gates 122 configured to control the electrostatic potential of quantum dots 104 disposed on two neighboring columns of quantum dots 104 are separated from each other by a second control gate 122 configured to control the electric potential of coupling regions 106 intended to control the coupling, or the tunnel barriers, between these quantum dots 104. Thus, in the example described in connection with FIGS. 1 to 4, parallel to the Y axis, that is to say perpendicular to the direction in which the second control grids 122 extend, those configured to control the electrostatic potential of the quantum dots 104 and those configured to control the electrostatic potential of the coupling regions 106 are arranged alternately next to each other.

[0064] Each of the second control gates 122 may comprise a gate dielectric which, in the example described in connection with FIGS. 1 to 4, is formed by a second dielectric layer 126 covering the second face 124 of the semiconductor layer 102 and which may also be in contact with parts of the first dielectric layer 108 located next to the semiconductor layer 102 or with parts of another oxide layer when the semiconductor layer 102 is formed by oxidation of certain parts of a semiconductor layer. For example, the second dielectric layer 126 may comprise silicon oxide or any other dielectric material suitable for forming a gate oxide, and its thickness (dimension parallel to the Z axis in the example of FIGS. 2 to 4) may be between 3 nm and 10 nm.

[0065] Furthermore, in the example described, each of the second control gates 122 further comprises a second conductive portion 128 disposed against the second dielectric layer 126. Each of the second conductive portions 128 has, for example, an elongated shape extending substantially parallel to the X axis. The second conductive portions 128 may comprise, for example, polysilicon or any other conductive material suitable for forming gate conductors. The dimensions of the second conductive portions 128 may be similar to those indicated previously for the first conductive portions 118.

[0066] The pitch of the first control gates 114, which corresponds to the distance between the longitudinal axes of two adjacent first conductive portions 118, may be between 30 nm and 40 nm. The pitch of the second control gates 122 may be similar to that of the first control gates 114. For example, by producing the first and second control gates 114, 122 with a pitch equal to 35 nm, the distance between two quantum dots 104 intended to interact with each other during an error correction code operation may be equal to approximately 100 nm.

[0067] In the embodiment shown in Figures 2 to 4, second dielectric portions 130 are arranged against the second conductive portions 128 such that each of the second conductive portions 128 is arranged between the second dielectric layer 126 and one of the second dielectric portions 130. These second dielectric portions 130 correspond to the mask used for producing the second conductive portions 128 and comprise, for example, silicon nitride or silicon oxide. Alternatively, the device 100 may not comprise these second dielectric portions 130, for example when the etching mask is removed after the etching forming the second conductive portions 128.

[0068] In the exemplary embodiment described, the second control gates 122 and the parts of the second dielectric layer 126 not covered by the second control gates 122 are covered by an etch stop layer 132, or CESL (Contact Etch Stop Layer). The etch stop layer 132 comprises, for example, silicon nitride and its thickness is, for example, between 20 nm and 30 nm. In the example of FIGS. 2 to 4, the device 100 further comprises a second encapsulation layer 134 which covers the etch stop layer 132, which comprises a dielectric material corresponding, for example, to silicon oxide and whose thickness (dimension parallel to the Z axis in FIGS. 2 to 4) is, for example, between 100 nm and 200 nm.

[0069] In the described embodiment, the device 100 further comprises first electrical contact elements 136 passing through the second encapsulation layer 134, the etch stop layer 132 and the first and second dielectric layers 108, 126, and each forming an electrical access to one of the first control gates 114. In the described example, the device 100 also comprises second electrical contact elements 138 passing through the second encapsulation layer 134, the etch stop layer 132 and the second dielectric portions 130, and each forming an electrical access to one of the second control gates 122. These first and second electrical contact elements 136, 138 are arranged at the same face of the device 100 (on the side of the second face 124 of the semiconductor layer 102 in the example of figures 2 to 4).In the example described in connection with figures 2 to 4, the electrical contact elements 136, 138 open at an upper face 139 of the second encapsulation layer 134.

[0070] In a particular configuration corresponding to that shown in FIGS. 2 to 4, ends of the first conductive portions 118 are arranged at different distances from a first edge of the semiconductor layer 102. In addition, ends of the second conductive portions 128 are arranged at different distances from a second edge of the semiconductor layer 102. Such a configuration facilitates the production of the first and / or second electrical contact elements 136, 138 which come into contact with the first and / or second conductive portions 118, 128 at these ends. Indeed, with such different distances between the ends of the conductive portions 118, 128 and the edges of the semiconductor layer 102, it is possible for one or more of the electrical contact elements 136, 138 to be wider than the conductive portions 118, 128 without this causing a short circuit between adjacent or neighboring conductive portions 118, 128.

[0071] The first and second control gates 114, 122 are configured such that each of the quantum dots 104 is arranged opposite one of the first control gates 114 and one of the second control gates 122, and each of the coupling regions 106 is arranged opposite one of the first control gates 114 and one of the second control gates 122. Furthermore, the projection of each of the first control gates 114 in a plane parallel to the first and second faces 116, 124 of the semiconductor layer 102 intersects the projections of each of the second control gates 122 in said plane. In the example described, this crossing forms right angles between the projections of the first control gates 114 and those of the second control gates 122.

[0072] In the described embodiment, the first and second control gates 114, 122 are configured such that, for each of the coupling regions 106, the first control gate 114 arranged opposite said coupling region 106 is adjacent to the first control gates 114 arranged opposite the two neighboring or adjacent quantum dots 104 intended to be coupled to each other by said coupling region 106, and that the second control gate 122 arranged opposite said coupling region 106 is adjacent to the second control gates 122 arranged opposite said two quantum dots 104.

[0073] Furthermore, in the embodiment described in connection with FIGS. 1 to 4, the device 100 further comprises holes 140 passing through the semiconductor layer 102 and which are each arranged between two neighboring quantum dots 104 arranged opposite the same first control gate 114 and / or between two neighboring quantum dots 104 arranged opposite the same second control gate 122. Such holes 140 can facilitate the confinement of charges in the quantum dots 104 by avoiding having to apply an electrical confinement potential where the holes 140 are located, the absence of semiconductor at the holes 140 making it possible to prohibit the presence of charges at the locations of the holes 140. In a particular configuration corresponding to that visible in [Fig.l], each hole 140 may be arranged opposite a first control grid 114 and a second control grid 122 each configured to control the electrostatic potential of at least one of the quantum dots 104. Alternatively, the device 100 may not include the holes 140, the electrical potential of the regions not crossed by the holes 140 being in this case controlled locally. by a grid.

[0074] The matrix of quantum dots 104 and coupling regions 106 of the device 100 is such that the electrostatic potential of each quantum dot 104 is controlled by one of the first control gates 114 and one of the second control gates 122, and that the electrostatic potential of each coupling region 106 is controlled by one of the first control gates 114 and one of the second control gates 122. For this, the first and second control gates 114, 122 are here configured so that each of the quantum dots 104 is arranged opposite one of the first control gates 114 and one of the second control gates 122, and that each of the coupling regions 106 is arranged opposite one of the first control gates 114 and one of the second control gates 122.The first control grids 114 controlling the electrostatic potential of the quantum dots 104 are distinct from those controlling the electrostatic potential of the coupling regions 106. Similarly, the second control grids 122 controlling the electrostatic potential of the quantum dots 104 are distinct from those controlling the electrostatic potential of the coupling regions 106.

[0075] In the matrix shown in [Fig. 1], the error correction operations, for example of surface code, between qubits are therefore carried out within the pairs of neighboring quantum dots 104 arranged diagonally. For example, in [Fig.l], an operation can be carried out between the quantum dots designated by the references 104.1 and 104.2 between which the coupling is controlled by the coupling region designated by the reference 106.1. Thus, the arrangement of the quantum dots 104 and the coupling regions 106 proposed by the device 100 is such that it is not necessary to implement coherent displacements between quantum dots before implementing error correction operations between qubits, because the qubits formed in the quantum dots 104 are directly coupled to each other by the coupling regions 106.

[0076] The device 100 allows row / column addressing of the quantum dots 104 and the coupling regions 106 with control effects at the intersections between the rows and the columns defined by the first and second control gates 114, 122. Each quantum dot 104 and each coupling region 106 is therefore here controlled by two separate control gates. The structure of the device 100 therefore allows individual and parallel control of the quantum dots 104 and the coupling regions 106. Thus, it is possible to execute in parallel different types of surface code cycle (for example X and Z) in the matrix of quantum dots 104. Furthermore, the structure proposed for the device 100 makes it possible to carry out a surface code cycle with a reduced number of operations, independently of the length of the code (for example of the order of ten of operations or steps), since it is not necessary to move the qubits on which the operations are implemented.

[0077] In the device 100, because the first and second control gates 114, 122 are arranged on the side of two opposite faces 116, 124 of the semiconductor layer 102, the device 100 is not subject to any phenomenon of screening of the gate levels. This arrangement also avoids problems of management of the topography and / or crossings of the control gates. Finally, this arrangement avoids the presence of a bonding interface near the quantum dots 104 and the coupling regions 106.

[0078] An example of a method for producing the electronic device 100 according to a particular embodiment is described below in connection with FIGS. 5A to 14B. FIGS. 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A and 14A correspond to perspective views of the elements produced, and FIGS. 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B and 14B correspond to sectional views of the elements produced.

[0079] In the exemplary embodiment described, the device 100 is made from a substrate of the semiconductor on insulator type, for example SOI (Silicon on Insulator). Such a substrate is shown in FIGS. 5A and 5B, and comprises a support layer 150 comprising for example silicon, a buried dielectric layer 152, or BOX (Buried Oxide) comprising for example silicon oxide, and a surface layer 154 comprising for example silicon. The surface layer 154 is intended to form the future semiconductor layer 102 of the device 100. In FIGS. 5A to 8B, although the buried dielectric layer 152 is shown as being thicker than the support layer 150, the thickness of the support layer 150 is in reality greater than that of the buried dielectric layer 152.

[0080] The first control gates 114 are first produced. For this, in the embodiment described, the first dielectric layer 108 is produced, for example by deposition or by thermal oxidation, on the surface layer 154, then a first conductive layer 156 intended for producing the first conductive portions 118 is formed, for example by deposition, on the first dielectric layer 108. A first etching mask layer 158 is then formed, for example by deposition, on the first conductive layer 156. The structure obtained at this stage of the method is shown in FIGS. 6A and 6B.

[0081] In the embodiment described, an etching of the first conductive layer 156 is then implemented according to a pattern defined beforehand in an etching mask produced from the first etching mask layer 158. At the end of this etching, the remaining portions of the first conductive layer 156 correspond to the first conductive portions 118 and form, with the first dielectric layer 108, the first control grids 114. The etching mask can be kept for the rest of the process and forms the first dielectric portions 120 arranged on the first conductive portions 118.

[0082] In the embodiment described, the oxide layer 109 is produced so as to cover the parts of the first dielectric layer 108 not covered by the first conductive portions 118. The structure obtained at this stage of the method is shown in FIGS. 7A and 7B. The layer 109 may for example be formed by an oxidation step, or a deposition step advantageously followed by a heat treatment step for densification and passivation of the charged defects. Alternatively, it is possible not to produce this oxide layer 109.

[0083] In the embodiment described, the first encapsulation layer 110 is then produced, for example by deposition then chemical-mechanical planarization (or CMP for “Chemical Mechanical Polishing” in English), in particular by covering the elements and materials previously produced on the surface layer 154.

[0084] In the embodiment described, the mechanical holding layer 112 is then secured to the first encapsulation layer 110. For example, this securing may correspond to a direct bonding of the oxide / oxide type, which implies that the mechanical holding layer 112 comprises, at least at its face intended to be secured to the first encapsulation layer 110, oxide. Other types of securing / or bonding are conceivable. The structure obtained at this stage of the method is shown in FIGS. 8A and 8B.

[0085] The structure obtained can then be turned over. The support layer 150 and the buried dielectric layer 152 are then removed, for example by grinding in order to remove a major part of the thickness of the support layer 150, then by wet etching(s) in order to remove the remaining thickness of the support layer 150 and the buried dielectric layer 152. These removals reveal the face of the surface layer 154 previously arranged against the buried dielectric layer 152. The structure obtained at this stage of the method is shown in FIGS. 9A and 9B.

[0086] In the described embodiment, etching of a portion of the surface layer 154 is carried out such that a remaining portion of the surface layer 154 forms the semiconductor layer 102 of the device 100. The structure obtained at this stage of the method is shown in FIGS. 10A and 10B. Alternatively, the layer 154 may be locally oxidized such that the non-oxidized portions form the semiconductor layer 102.

[0087] In the embodiment described, the holes 140 are then made, for example by etching, through the semiconductor layer 102. The structure obtained at this stage of the process is shown in FIGS. 11A and 11B.

[0088] The second control grids 122 are then produced. For this, in the embodiment described, the second dielectric layer 126 is produced, for example by deposition, on the semi-conductor layer 102 as well as on the parts of the first dielectric layer 108 not covered by the semi-conductor layer 102, then a second conductive layer 160 intended for producing the second conductive portions 128 is formed, for example by deposition, on the second dielectric layer 126. A second etching mask layer 162 is then formed, for example by deposition, on the second conductive layer 160. The structure obtained at this stage of the method is shown in FIGS. 12A and 12B.

[0089] In the described embodiment, an etching of the second conductive layer 160 is then implemented according to a pattern defined beforehand in an etching mask produced from the second etching mask layer 162. At the end of this etching, the remaining portions of the second conductive layer 160 correspond to the second conductive portions 128 and form, with the second dielectric layer 126, the second control gates 122. The etching mask can be kept for the rest of the method and forms the second dielectric portions 130. Optionally, an oxide layer similar to the oxide layer 109 can be produced on the produced structure. The structure obtained at this stage of the method is shown in FIGS. 13A and 13B.

[0090] In the embodiment described, the etch stop layer 132 is then produced, for example by deposition, by covering the second control gates 122 and the parts of the second dielectric layer 126 not covered by the second conductive portions 128. The second encapsulation layer 134 is then produced, for example by deposition then CMP on the etch stop layer 132. The structure obtained at this stage of the method is shown in FIGS. 14A and 14B.

[0091] Finally, the first and second electrical contact elements 136, 138 are produced through the layers covering the first and second conductive portions 118, 128, i.e. the second encapsulation layer 134, the etch stop layer 132 and the second etch mask layer 166 for the second conductive portions 128, and also through the first and second dielectric layers 108, 109, 126 for the first conductive portions 118. For this, at least one lithography step can be implemented to form holes defining the locations of the first and second electrical contact elements 136, 138. The holes are then filled with at least one electrically conductive material to form the first and second electrical contact elements 136, 138. The device 100 obtained corresponds to that visible in FIGS. 1 to 4 previously described.

[0092] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art.

[0093] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. For example, the nature of the deposits and etchings implemented can be chosen in particular depending on the material(s) to be deposited or etched.

Claims

Claims

1. Electronic device (100) comprising: - a semiconductor layer (102) comprising a matrix of quantum dots (104) and coupling regions (106) each arranged between two adjacent quantum dots (104); - several first control gates (114), arranged next to each other on the side of a first face (116) of the semiconductor layer (102), covering at least a part of the matrix of quantum dots (104) and / or the coupling regions (106), and configured to each control the electrostatic potential of at least one of the quantum dots (104) or of at least one of the coupling regions (106);- several second control gates (122), arranged next to each other on the side of a second face (124), opposite the first face (116), of the semiconductor layer (102), covering at least a part of the matrix of quantum dots (104) and / or the coupling regions (106), and configured to each control the electrostatic potential of at least one of the quantum dots (104) or of at least one of the coupling regions (106); in which the first control gates (114) extend along their largest dimension parallel to a first axis and the second control gates (122) extend along their largest dimension parallel to a second axis, and in which projections of the first and second axes in the same plane are intersecting.;

2. The electronic device (100) of claim 1, wherein the first and second control gates (114, 122) are configured such that, for each of the coupling regions (106), the first control gate (114) arranged opposite said coupling region (106) is adjacent to the first control gates (114) arranged opposite the two neighboring quantum dots (104) intended to be coupled to each other by said coupling region (106), and that the second control gate (122) arranged opposite of said coupling region (106) is adjacent to the second control grids (122) arranged opposite said two quantum dots (104).

3. An electronic device (100) according to any preceding claim, wherein the first control grids (114) are aligned in a first direction perpendicular to a second direction in which the second control grids (122) are aligned.

4. Electronic device (100) according to any one of the preceding claims, in which the semiconductor layer (102) comprises holes (140) passing through it and which are each arranged between two adjacent quantum dots (104) arranged opposite the same first control gate (114) and / or between two adjacent quantum dots (104) arranged opposite the same second control gate (122).

5. The electronic device (100) of claim 4, wherein each hole (140) is disposed opposite a first control gate (114) and a second control gate (122) each configured to control the electrostatic potential of at least one of the quantum dots (104).

6. An electronic device (100) according to any preceding claim, further comprising first electrical contact elements (136) coupled to the first control grids (114) and second electrical contact elements (138) coupled to the second control grids (122), and wherein the first and second electrical contact elements (136, 138) are disposed at a same face of the electronic device (100).

7. An electronic device (100) according to any preceding claim, wherein first electrical contact elements (136) are coupled to ends of first conductive portions (118) of the first control gates (114) and arranged at different distances from a first edge of the semiconductor layer (102), and / or wherein second electrical contact elements (138) are coupled to ends of second conductive portions (128) of the second control gates (122) and arranged at different distances from a second edge of the semiconductor layer (102).

8. Method for producing an electronic device (100), comprising at minus the following steps: - production of several first control gates (114) arranged next to each other on the side of a first face (116) of a semiconductor layer (102) comprising a matrix of quantum dots (104) and coupling regions (106) each arranged between two adjacent quantum dots (104), covering at least a part of the matrix of quantum dots (104) and / or the coupling regions (106), and configured to each control the electrostatic potential of at least one of the quantum dots (104) or of at least one of the coupling regions (106); - production of several second control grids (122), arranged next to each other on the side of a second face (124), opposite the first face (116), of the semiconductor layer (102), covering at least a part of the matrix of quantum dots (104) and / or the coupling regions (106), and configured to each control the electrostatic potential of at least one of the quantum dots (104) or of at least one of the coupling regions (106); wherein the first control grids (114) extend along their largest dimension parallel to a first axis and the second control grids (122) extend along their largest dimension parallel to a second axis, and wherein projections of the first and second axes in the same plane are intersecting.

9. Production method according to claim 8, further comprising, between the production of the first control gates (114) and the production of the second control gates (122), a production of holes (140) passing through the semiconductor layer (102) and each arranged between two adjacent quantum dots (104) arranged opposite the same first control gate (114) and / or between two adjacent quantum dots (104) arranged opposite the same second control gate (122).

10. Production method according to one of claims 8 or 9, in which the semiconductor layer (102) corresponds to at least part of a surface layer (154) of a semiconductor-on-insulator type substrate.

11. Production method according to claim 10, wherein the production of the first control grids (114) comprises at least the implementation of the following steps: - production of at least a first dielectric layer (108) and a first conductive layer (156) on the surface layer (154); - etching of the first conductive layer (156) such that the remaining portions (118) of the first conductive layer (156) and the first dielectric layer (108) form the first control grids (114).

12. Production method according to one of claims 10 or 11, further comprising, between the production of the first control gates (114) and the production of the second control gates (122), the implementation of the following steps: - production of a first encapsulation layer (110) covering at least the first control gates (114); - securing a mechanical holding layer (112) on the first encapsulation layer (110); - removal of a support layer (150) and a buried dielectric layer (152) from the substrate, revealing a second face of the surface layer (154) corresponding to the second face (124) of the semiconductor layer (102).

13. Production method according to claim 12 further comprising, between the removal of the support layer (150) and the buried dielectric layer (152) and the production of the second control gates (122), a step of etching a portion of the surface layer (154) such that a remaining portion of the surface layer (154) forms the semiconductor layer (102), or an oxidation of a portion of the surface layer (154) such that a non-oxidized portion of the surface layer (154) forms the semiconductor layer (102).

14. Production method according to one of claims 12 or 13, in which the production of the second control grids (122) comprises at least the implementation of the following steps: - production of at least one second dielectric layer (126) and a second conductive layer (160) on the second face of the surface layer (154); - etching the second conductive layer (160) and the second dielectric layer (126) such that the remaining portions (128) of the second conductive layer (160) and the second dielectric layer (126) form the second control gates (122).

15. A method of making according to any one of claims 12 to 14, further comprising making first electrical contact elements (136) coupled to the first control gates (114) through the first encapsulation layer (110), and making second electrical contact elements (138) coupled to the second control gates (122) through a second encapsulation layer (134) previously deposited and covering the second control gates (122).