Electronic device

Abstract

Electronic Device The present description relates to an electronic device comprising a pixel and a method for controlling the pixel (10), the pixel comprising: a photodiode (12); a charge transfer channel comprising a first semiconductor region (34) and a second semiconductor region (36), the second region (36) being separated from the photodiode by the first region (34); and a trench (32) surrounding the channel, the trench (32) comprising a first core (40), a second conductive core (42) and an insulating sheath (33), the first core (40) laterally surrounding the first region (34) and the second core (42) laterally surrounding at least partially the second region (36), the first core (40) and the second core (42). Figure for abstract: Fig. 1B

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and more particularly to electronic devices comprising photodiodes. Prior art

[0002] An electronic device, for example an image sensor, for example located in a digital device (digital camera, tablet, mobile phone, etc.), comprises for example a set of photodetectors for capturing and converting light from an exposure into electrical signals. In a CMOS (Complementary Metal Oxide Semiconductor) type image sensor, the electrical signal from each individual photodetector is amplified and transmitted to an integrated circuit for processing at the same time. Subsequently, the photodetectors are erased to capture the next exposure.

[0003] In an image sensor that uses backside illumination (BSI), light is exposed to a back surface of the image sensor.

[0004] The sensor circuit that converts light into a digital signal is preferably arranged on the front face, i.e., the face opposite the back face, of the image sensor. An image sensor may use a photoelectric effect to absorb and convert light into an electron-hole pair at each of the photodetectors. In an image sensor, which uses, for example, photodiodes, charge carriers (i.e., holes or electrons) are generated and stored in the depletion region of the photodiode during an integration period in the readout cycle of the photodetector. During a charge transfer period in the readout cycle of the photodetector, the charge carriers around the depletion region are transferred to a connection node and a corresponding digital representation of the level of light exposed at the photodetector is generated. Summary of the invention

[0005] One embodiment provides an electronic device comprising a pixel, the pixel comprising: - a photodiode located in a substrate; - a charge transfer channel comprising a first semiconductor region and a second semiconductor region, the second region being separated from the photodiode by the first region; and - a trench surrounding the channel, the trench comprising a first conductive core, a second conductive core and an insulating sheath, the first core laterally surrounding the first region and the second core laterally surrounding at least partially the second region, the first core and the second core being configured to be polarized in such a manner that: - in an integration step, the electrostatic potentials of the first region and the second region are substantially equal and are at a high value; - in a charge transfer step, the electrostatic potentials of the first region and the second region are respectively at a first low value and a second low value, the first low value being higher than the second low value; - in a first step of passing from the charge transfer step to a reading step, the electrostatic potential of the first region is at the high value and the electrostatic potential of the second region is at the second low value; and - in a second step of passing from the charge transfer step to the reading step, the electrostatic potentials of the first region and the second region are substantially equal and are equal to the high value.

[0006] One embodiment provides a method of controlling an electronic device comprising a pixel, the pixel comprising: - a photodiode located in a substrate; - a charge transfer channel comprising a first semiconductor region and a second semiconductor region, the second region being separated from the photodiode by the first region; and - a trench surrounding the channel, the trench comprising a first conductive core, a second conductive core and an insulating sheath, the first core laterally surrounding the first region and the second core laterally surrounding at least partially the second region, the method comprising: - an integration step, in which the first core and the second core are polarized in such a way that the electrostatic potentials of the first region and the second region are substantially equal and are at a high value; - a charge transfer step, in which the first core and the second core are polarized in such a way that the electrostatic potentials of the first region and the second region are respectively at a first low value and at a second low value, the first low value being higher than the second low value; - a first step of passing from the charge transfer step to a reading step, in which the first core and the second core are polarized in such a way such that the electrostatic potential of the first region is at the high value and the electrostatic potential of the second region is at the second low value; and - a second step of passing from the charge transfer step to the reading step, in which the first core and the second core are polarized in such a way that the electrostatic potentials of the first region and the second region are substantially equal and are equal to the high value.

[0007] According to one embodiment, the photodiode comprises third and fourth semiconductor regions in contact with each other and having opposite doping types, the fourth region being in contact with the first region.

[0008] According to one embodiment, the first region and the second region are doped with the same conductivity type.

[0009] According to one embodiment, the first region and the second region have a substantially equal dopant concentration.

[0010] According to one embodiment, the voltages applied to the first and second cores are different at least during one operating step of the pixel.

[0011] According to one embodiment, the thickness of the sheath separating the first region and the first core is different from the thickness of the sheath separating the second region and the second core.

[0012] According to one embodiment, the first core and the second core are separated by a portion of the cladding.

[0013] According to one embodiment, the first core and the second core are doped with the same conductivity type.

[0014] According to one embodiment, the first core and the second core are made of doped semiconductor materials of opposite types.

[0015] According to one embodiment, the second low value is substantially equal to the value of the electrostatic potential in an output node of the pixel.

[0016] According to one embodiment, the pixel is laterally surrounded by an insulated conductive wall.

[0017] According to one embodiment, the second core laterally completely surrounds the second region.

[0018] According to one embodiment, the first core comprises a first portion laterally surrounding the first region and a second portion, the second core being located between the second region and the second portion.

[0019] According to one embodiment, the first core comprises a first portion laterally surrounding the first region and a second portion, the second region being laterally surrounded partially by the second core and partially by the second portion. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.lA], [Fig.lB] and [Fig.lC] represent, partially and schematically, an embodiment of a pixel of an electronic device;

[0022] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] illustrate the operation of the embodiment of Figures 1A to 1C;

[0023] [Fig.3A] and [Fig.3B] represent, partially and schematically, another embodiment of a pixel of an image sensor;

[0024] [Fig.4] represents, partially and schematically, another embodiment of a pixel of an image sensor;

[0025] Figures 5A and 5B show, partially and schematically, another embodiment of a pixel of an image sensor;

[0026] [Fig. 6] represents a variant of the embodiment of Figures 5A and 5B; and

[0027] [Fig.7] represents another variant of the embodiment of figures 5A and 5B. Description of the embodiments

[0028] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0033] In order to allow better conservation of charges in the storage region of the pixel, i.e. the drain region of the pixel, the pixel comprises two successive transfer gates. The two gates are configured so that, during the integration period of the pixel, the electrostatic potential at the two gates is identical to a first value. The two gates are also configured so that, during the charge transfer period, the electrostatic potential at the gate closest to the charge storage region of the pixel is higher than that of the other gate. At the end of the charge transfer period, the gates are configured so that the electrostatic potential of the gate closest to the charge storage region of the pixel returns to the first value before that of the other gate.

[0034] [Fig.lA], [Fig.lB] and [Fig.lC] represent, partially and schematically, an embodiment of a pixel 10 c. More precisely, [Fig.lA] represents a top view of the pixel of figures 1B and 1C. [Fig.lB] represents a sectional view of the pixel of [Fig.lA] along a plane BB of [Fig.lA]. [Fig.lC] represents a sectional view of the pixel of [Fig.lA] along a plane CC of [Fig.lA].

[0035] The image sensor comprises a plurality of pixels 10, arranged in a matrix, i.e. in rows and columns. Each pixel 10 comprises at least one photodetector, for example a photodiode. In the example of figures 1A to 1C, the pixel 10 comprises a single photodiode.

[0036] The pixel 10 is formed in a substrate 12. The substrate 12 is for example a semiconductor substrate, for example made of silicon. The substrate 12 comprises a first face 12a, called the rear face, and a second face 12b, called the front face.

[0037] The pixel 10 of figures 1A to 1C is a back-illuminated pixel. In other words, the pixel is configured so that the photodiode receives the light rays via the back face, the charges being subsequently extracted via the opposite face, the front face. Thus, the back face 12a of the substrate 12 is for example covered, at least at the pixel level, by optical elements.

[0038] The rear face of the substrate is for example covered by one or more layers 14. In the example of figures 1A to 1C, the pixel comprises a single layer 14. The layer 14 is for example a layer having anti-reflective and / or passivation properties. The layer 14 for example directly covers the face 12a.

[0039] The pixel comprises for example one or more layers 16. In the example of figures 1A to 1C, the pixel comprises only a single layer 16. The layer 16 is for example a filter. The layer 16 is for example configured to filter one or more wavelengths. The layer 16 covers for example the layer 14, the layer 14 being located between the layer 16 and the substrate 12.

[0040] Furthermore, the pixel comprises for example a lens 18, for example configured to focus the light rays into the photodiode. The lens 18 covers for example the layer 16, the layer 16 being located between the layer 14 and the lens.

[0041] The pixel is surrounded by a wall 20. The wall 20 is preferably an insulating wall, for example a conductive insulating wall. More specifically, the wall 20 preferably comprises a conductive core 20a and an insulating sheath 20b. The conductive core 20a of the wall 20 is for example configured to be polarized so as to deplete the photodiode. The wall 20 preferably extends over at least the height of the photodiode of the pixel, preferably over the entire height of the substrate 12.

[0042] The photodiode of the pixel comprises regions 22, 24 and 26 of the substrate. Regions 22 and 24 are doped with opposite doping type. Similarly, regions 24 and 26 are doped with opposite doping type. For example, region 22 is doped with N type, region 24 is doped with P type and region 26 is doped with N type. Regions 22 and 24 are preferably in contact so as to form a PN junction. Regions 24 and 26 are preferably in contact so as to form a PN junction.

[0043] Region 22 is located at the rear face of substrate 12. More precisely, region 22 is flush with face 12a. Thus, one face of region 22 is coplanar with face 12a.

[0044] Region 24 is located in substrate 12. Thus, region 24 is separated from face 12a by region 22.

[0045] Region 26 is located at the front face of substrate 12. More precisely, region 26 is flush with face 12b. Thus, one face of region 26 is coplanar with face 12b. Region 26 forms a ring extending into the periphery of the pixel. More precisely, region 26 extends along the walls of wall 20. Region 26 is thus separated from region 22 by region 24.

[0046] Regions 22, 24 and 26 are surrounded by wall 20. Preferably, regions 22, 24 and 26 are in lateral contact with wall 20. Thus, regions 22 and 24 are preferably not separated from the wall by other semiconductor regions.

[0047] Region 26 comprises for example one or more transistors, for example one or more insulated gate field effect transistors (MOSFET - Metal Oxide Semiconductor Field Effect Transistor). In the example of Figures 1A to 1C, region 26 comprises two MOSFET transistors 28 and 30.

[0048] Each transistor 28, 30 is located in a part of the region 26 surrounded by an insulating wall, respectively 28a, 30a. The walls 28a, 30a are for example shallow trench insulation (STI - Shallow Trench Insulation). The walls 28a, 30a preferably extend over a height less than the height of the region 26. The walls 28a, 30a preferably extend from the front face 12b. Thus, the walls 28a and 30a preferably extend only in the region 26.

[0049] The transistor 28, respectively 30, comprises in the part of the region 26 surrounded by the wall 28a, source and drain regions 28b, respectively 30b. The transistor 28 further comprises a gate 28c, respectively 30c, shown schematically in Figures 1A to 1C.

[0050] The pixel further comprises a trench 32. The trench 32 comprises one or more conductive cores 40, 42 and an insulating sheath 33. The trench extends into the substrate 12 from the front face of the substrate 12. The trench 32 extends along the internal walls of the ring formed by the region 26. Thus, the region 26 is defined laterally by the wall 20 and the trench 32. The trench 32 has a height preferably at least equal to the height of the region 26, preferably greater than the height of the region 26.

[0051] The trench 32 forms a ring around a portion of the substrate 12. More specifically, the trench 32 forms a ring around regions 34, 36, 38 of the substrate 12. The regions 34, 36, 38 form a charge transfer channel. The regions 34, 36, 38 are preferably entirely laterally surrounded by the trench 32. The regions 34, 36, 38 are preferably made of a semiconductor material, preferably the material of the substrate. The regions 34 and 36 are preferably made of the same material. The regions 34 and 36 are preferably doped with the same dopant. The regions 34, 36, 38 are preferably doped with the same conductivity type, preferably with the conductivity type of region 24. In the example of Figures 1A to 1C, the regions 34, 36, 38 are, for example, P-doped. The concentration of dopants in the regions 34 and 36 is, for example, substantially identical. The region 34 is in contact with the front face of the region 24.Region 36 is in contact with the front face of region 34. Region 36 is thus separated from region 24 by region 34. Region 38 is in contact with the front face of region 36. Region 38 is thus separated from region 34 by region 36. Region 38 is, for example, flush with the front face 12b of the substrate 12.

[0052] In the example of figures 1A to 1C, the trench 32 comprises two conductive cores 40 and 42. The trench 32 thus corresponds to a double transfer gate, the charges generated in the photodiode being able to be extracted via the regions 34, 36, 38 by controlling the transfer gates.

[0053] The conductive cores 40 and 42 are for example made of the same material, for example a semiconductor material. The conductive cores 40 and 42 are for example made of polycrystalline silicon. Alternatively, the cores 40 and 42 may be made of different materials. Preferably, the cores 40 and 42 are doped with opposite types. For example, the core 42 is of the same conductivity type as the region 24, for example P-type. For example, the core 42 is of the same conductivity type as the region 36. For example, the core 40 is of the same conductivity type as the region 22, for example N-type. For example, the core 40 is of the opposite conductivity type. to that of region 34. The cladding 33 is for example made of a silicon oxide, for example a nitrided silicon oxide. The dopant concentration in the cores 40 and 42 is preferably different. For example, the dopant concentration in the core 40 is greater than the dopant concentration in the core 42.

[0054] The conductive core 40 comprises a lower portion 40a and an upper portion 40b. The portion 40a forms a ring laterally surrounding the region 34. The height of the portion 40a is preferably substantially equal to the height of the region 34. Preferably, the upper face of the portion 40 is substantially coplanar with the upper face of the region 34.

[0055] The portion 40a is configured to be biased by a first control voltage, for example via the upper portion 40b. The upper portion 40b is in contact with the lower portion 40a. The upper portion 40b extends for example from the lower portion 40a to the front face of the substrate 12. Thus, the core 40 can be biased by the front face of the substrate 12.

[0056] The conductive core 42 is located above the core 40. In other words, the core 42 is located between the core 40 and the front face 12b. The core 42 laterally surrounds at least a portion of the region 36, preferably a lower portion of the region 36. The core 42 is for example in contact with the upper face of the portion 40a and is for example in contact with a side wall of the portion 40b. The portion 40b is separated from the region 36 by the core 42. The core 42 is configured to be biased by a second control voltage, preferably by the front face of the substrate.

[0057] Preferably, the thickness of the cladding 33 is constant. In other words, the region 34 and the part 40a are preferably separated by a cladding thickness 33 substantially equal to the cladding thickness 33 separating the core 42 and the region 36.

[0058] The first control voltage and the second control voltage are preferably independent of each other.

[0059] The cores 40 and 42 are separated from the regions 24, 26, 34, 36, 38 by the insulating sheath 33 of the trench 32. The insulating sheath and the conductive cores form the transfer gates.

[0060] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] illustrate the operation of the embodiment of Figures 1A to 1C. More specifically, Figures 2A to 2D represent charge diagrams of the electrostatic potential (E) along the plane D-D'. Figures 2A to 2D thus comprise several zones A, B, C, D.

[0061] Area A corresponds to region 24. Area A is illustrated by a capacitor 44. Area A corresponds to the charge storage area.

[0062] Zones B and C correspond to the charge transfer transistor, and more precisely to the double charge transfer gates. Thus, zones B and C are illustrated by a transistor 46 comprising two gates. Zone B corresponds to the first grid, implemented by core 40 and cladding 33. Area C corresponds to the second grid, implemented by core 42 and cladding 33.

[0063] Zone D corresponds to the output node of the pixel, that is to say the node linked, preferably connected, to region 38.

[0064] [Fig.2A] corresponds to a step of integration of the photodiode. In other words, during the step of [Fig.2A], light rays reach the photodiode, via the rear face, and charges are generated in region 24.

[0065] During this step, region 24 is initially completely depleted, for example by applying a suitable voltage, for example a positive voltage, to the core 20a of the wall 20. Thus, the electrostatic potential in region 24 is lower than the electrostatic potential in region 22, the electrostatic potential of region 26, and the electrostatic potential of region 34. This forms a barrier against the movement of charges between regions 22 and 24, 26 and 24, and 34 and 24.

[0066] The first voltage and the second voltage, applied respectively to the first transfer gate and to the second transfer gate, that is to say respectively to the cores 40 and 42, are respectively equal to values ​​VIA and V2A. The values ​​VIA and V2A are for example different from each other. The values ​​VIA and V2A are such that the electrostatic potentials in the regions 34 and 36, that is to say in the zones B and C of [Fig. 2A], are substantially equal to each other and are greater than the electrostatic potential in the region 24. A barrier against the movement of charges is thus formed between the region 34 and the region 24. In other words, the transfer transistors are blocked.

[0067] Furthermore, the electrostatic potential at the output node, i.e. in area D, is lower than the electrostatic potentials of regions 24, 34, 36, for example is equal to zero.

[0068] The charges generated in region 24 by the reception of light rays are thus stored in region 24. The quantity of charges that can be stored in region 24 is represented by a dotted line and depends on the difference in electric potential between region 24 and region 34. The dotted line illustrates the value of the electrostatic potential which increases with the quantity of charges stored in region 24 (the solid line symbolizes the electrostatic potential when the area is completely deserted and the dotted line symbolizes the electrostatic potential in the presence of charges stored in region 24).

[0069] [Fig.2B] represents a charge transfer step. During this step, at least a portion, preferably all, of the charges stored in region 24 are transferred to the output node. In the case of a total transfer, the electrostatic potential of region 24 returns to its completely deserted area value (symbolized by a solid line).

[0070] During this step, the electrostatic potential of region 24 returns to its completely deserted zone value (solid line) which corresponds to the initial or reset value of region 24.

[0071] During this step, the first voltage and the second voltage, applied respectively to the first transfer gate and to the second transfer gate, that is to say respectively to the cores 40 and 42, are respectively equal to values ​​V1B and V2B. The values ​​V1B and V2B are for example different from each other. The values ​​V1B and V2B are for example respectively lower than the values ​​V1A and VIB. The values ​​V1B and V2B are such that the electrostatic potential in the region 34, corresponding to the zone B, is lower than the electrostatic potential of the depleted region 24 and that the electrostatic potential in the region 36, corresponding to the zone C, is lower than the electrostatic potential of the region 34. Preferably, the value V2B of the second voltage is such that the electrostatic potential of the region 36 is substantially equal to the electrostatic potential of the output node.In other words, the charge transfer transistors are on.

[0072] The barrier between region 24 and the output node is thus removed. The charges in region 24 are thus attracted to region 36 and the output node. The electrostatic potential corresponding to the amount of charges transferred is represented by a dotted line in area D.

[0073] [Fig.2C] represents a first step of transition from the charge transfer step to a step during which the transferred charges are read and converted into an output voltage, corresponding for example to the integration step.

[0074] During this step, the first voltage takes the value V1A and the second voltage retains the value V2B. Thus, the charge transfer transistor comprising the first gate is blocked and the charge transfer transistor comprising the second gate is conducting.

[0075] The barrier preventing charge transfer from region 24 is thus again present. The charges having been transferred are maintained in region 36 and in the output node.

[0076] [Fig. 2D] represents a second step of transition from the charge transfer step to a step during which the transferred charges are read and converted into an output voltage. The steps of FIGS. 2C and 2D are preferably successive.

[0077] During this step, the second voltage takes the value V2A and the first voltage retains the value VIA. Thus, all the charges located in region 36 during the previous step are transferred to the output node and the barrier preventing the return of charges to region 24 is again present.

[0078] The limit of charges that can be stored in the output node is determined by the electrostatic potential in region 36 and is represented by a dotted line in area D.

[0079] It could have been chosen to form only a single transfer gate surrounding regions 34 and 36 and receiving a single voltage, regions 34 and 36 having different dopant concentrations. Said dopant concentrations could have been chosen in such a way that the electrostatic potential in region 36 was lower than the electrostatic potential in region 34. However, the quantity of charges that could be stored in the output node would have been lower.

[0080] [Fig.3A] and [Fig.3B] represent, partially and schematically, another embodiment of a pixel 50 of an electronic device, for example an image sensor. More precisely, [Fig.3A] represents a top view of the pixel 50 of [Fig.3B]. [Fig.3B] represents a sectional view of the pixel of [Fig.3A] along a plane BB of [Fig.3A].

[0081] Pixel 50 comprises the elements of pixel 10. These elements are designated by the same references and will not be described again in detail.

[0082] Pixel 50 differs from pixel 10 of Figures 1A to 1C in that the cladding thickness 33 separating core 42 from region 36 is different from the cladding thickness 33 separating core 40 from region 34. Preferably, the difference between the cladding thicknesses is at least 20%. In the example of Figures 3A and 3B, the cladding thickness 33 separating core 42 from region 36 is greater than the cladding thickness 33 separating core 40 from region 34.

[0083] According to one embodiment, the doping concentrations of the cores 40 and 42 are substantially identical. According to one embodiment, the values ​​V1A and V2A are such that the electrostatic potential of the regions 34 and 36 are substantially equal during the integration steps. The values ​​V1B and V2B are for example substantially identical, the difference in electrostatic potential during the transfer step being generated by the difference in thickness of the cladding 33 at the regions 34 and 36.

[0084] [Fig. 4] represents, partially and schematically, another embodiment of a pixel 52 of an electronic device, for example an image sensor. More precisely, [Fig. 4] represents a sectional view of the pixel 52 along a plane BB located similarly to the plane BB of [Fig. 2A].

[0085] Pixel 52 comprises the elements of pixel 10. These elements are designated by the same references and will not be described again in detail.

[0086] Pixel 52 differs from pixel 10 of Figures 1A to 1C in that cores 40 and 42 are separated from each other by a portion of sheath 33. Thus, insulating sheath 33 extends around each core 40 and 42. Cores 40 and 42 are thus not in contact.

[0087] According to the embodiment of [Fig.4], the cores 40 and 42 may be of different doping types, as in the embodiment of figures 1A to 1C or of identical doping types.

[0088] Figures 5A and 5B show, partially and schematically, another embodiment of a pixel 54 of an electronic device, for example an image sensor. More specifically, [Fig.5A] shows a top view of the pixel 54 of [Fig.5B]. [Fig.5B] shows a sectional view of the pixel 54 of [Fig.5A] along a plane BB of [Fig.5A].

[0089] Pixel 54 comprises the elements of pixel 10. These elements are designated by the same references and will not be described again in detail.

[0090] Pixel 50 differs from pixel 10 of Figures 1A to 1C in that core 42, hatched in [Fig.5A], extends only over a portion of the outline of region 36. More specifically, in the embodiment of Figures 5A and 5B, core 42 extends over one side of the rectangular outline surrounding region 36.

[0091] The core 42 is in vertical alignment with the portion 40a of the core 40. Thus, the core 42 is not separated from the region 36 by the core 40. Similarly, the core 40, and in particular the portion 40b, is not separated from the regions 34 and 36 by the core 42.

[0092] The region 34 is surrounded laterally by the part 40a of the core 40. The region 34 is preferably not surrounded, even partially, by the core 42. The region 36 is surrounded by a contour comprising, on one side, the core 42, and on the other sides, for example the other three sides, the part 40b of the core 40.

[0093] In the embodiment of Figures 5A and 5B, the cores 40 and 42 are preferably, as in the embodiment of Figures 1A to 1C, doped with opposite conductivity types. The operation of the embodiment of Figures 5A and 5B is identical to the operation of the embodiment of Figures 1A to 1C, described in connection with Figures 2A to 2D.

[0094] [Fig.6] represents a variant of the embodiment of Figures 5A and 5B.

[0095] The embodiment of [Fig.6] differs from the embodiment of Figures 5A and 5B in that the core 42, hatched in [Fig.5A], extends on two sides of the rectangular outline surrounding the region 36.

[0096] The core 42 is, as in figures 5 A and 5B, in vertical alignment with the part 40a of the core 40. Thus, the core 42 is not separated from the region 36 by the core 40. Similarly, the core 40, and in particular the part 40b, is not separated from the regions 34 and 36 by the core 42.

[0097] The region 34 is surrounded laterally by the part 40a of the core 40. The region 34 is preferably not surrounded, even partially, by the core 42. The region 36 is surrounded by a contour comprising, on two sides, the core 42, and on the other sides, for example the other two sides, the part 40b of the core 40.

[0098] [Fig.7] represents another variant of the embodiment of Figures 5A and 5B.

[0099] The embodiment of [Fig.7] differs from the embodiment of Figures 5A and 5B in that the core 42, hatched in [Fig.5A], extends on three sides of the rectangular outline surrounding the region 36.

[0100] The core 42 is, as in FIGS. 5A and 5B, in vertical alignment with the part 40a of the core 40. Thus, the core 42 is not separated from the region 36 by the core 40. Similarly, the core 40, and in particular the part 40b, is not separated from the regions 34 and 36 by the core 42.

[0101] The region 34 is surrounded laterally by the part 40a of the core 40. The region 34 is preferably not surrounded, even partially, by the core 42. The region 36 is surrounded by a contour comprising, on three sides, the core 42, and on the other sides, for example the only other side, the part 40b of the core 40.

[0102] An advantage of the described embodiments is that they ensure that charges transferred into the output node cannot return to the storage region of the photodiode.

[0103] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the doping types may be reversed from the examples described in connection with the figures. In the embodiment of Figures 3A and 3B, the cladding thickness 33 separating the core 42 from the region 36 is less than the cladding thickness 33 separating the core 40 from the region 34.

[0104] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Electronic device comprising a pixel (10, 50, 52), the pixel comprising: - a photodiode located in a substrate (12); - a charge transfer channel comprising a first semiconductor region (34) and a second semiconductor region (36), the second region (36) being separated from the photodiode by the first region (34); and - a trench (32) surrounding the channel, the trench (32) comprising a first conductive core (40), a second conductive core (42) and an insulating sheath (33), the first core (40) laterally surrounding the first region (34) and the second core (42) laterally surrounding at least partially the second region (36), the first core (40) and the second core (42) being configured to be polarized in such a way that: - in an integration step, the electrostatic potentials of the first region (34) and the second region (36) are substantially equal and are at a high value;- in a charge transfer step, the electrostatic potentials of the first region (34) and the second region (36) are respectively at a first low value and a second low value, the first low value being higher than the second low value; - in a first step of passing from the charge transfer step to a reading step, the electrostatic potential of the first region (34) is at the high value and the electrostatic potential of the second region (36) is at the second low value; and - in a second step of passing from the charge transfer step to the reading step, the electrostatic potentials of the first region (34) and the second region (36) are substantially equal and are equal to the high value.;

2. The device of claim 1, wherein the photodiode comprises third (22) and fourth (24) semiconductor regions in contact with each other and having opposite doping types, the fourth region (24) being in contact with the first region (34).

3. A device according to claim 1 or, wherein the first region (34) and the second region (36) are doped with the same conductivity type.

4. A device according to any one of claims 1 to 3, wherein the first region (34) and the second region (36) have a substantially equal dopant concentration.

5. Device according to any one of claims 1 to 4, in which the voltages applied to the first core (40) and to the second core (42) are different at least during one operating step of the pixel.

6. Device according to any one of claims 1 to 5, wherein the thickness of the sheath (33) separating the first region (34) and the first core (40) is different from the thickness of the sheath (33) separating the second region (36) and the second core (42).

7. Device according to any one of claims 1 to 6, in which the first core (40) and the second core (42) are separated by a portion of the sheath (33).

8. The device of claim 7, wherein the first core (40) and the second core (42) are doped with the same conductivity type.

9. Device according to any one of claims 1 to 7, in which the first core (40) and the second core (42) are made of doped semiconductor materials of opposite types.

10. A device according to any one of claims 1 to 9, wherein the second low value is substantially equal to the value of the electrostatic potential in an output node of the pixel.

11. A device according to any one of claims 1, 3 to 10, wherein the pixel is laterally surrounded by an insulated conductive wall (20).

12. Device according to any one of claims 1, 3 to 11, in which the second core (42) laterally completely surrounds the second region (36).

13. Device according to claim 12, wherein the first core (40) comprises a first portion (40a) laterally surrounding the first region (34) and a second portion (40b), the second core (42) being located between the second region (36) and the second portion (40b).

14. A device according to any one of claims 1, 3 to 13, wherein the first core (40) comprises a first portion (40a) laterally surrounding the first region (34) and a second portion (40b), the second region (36) being laterally surrounded partially by the second core (42) and partially by the second portion (40b).

15. A method of controlling a device according to any one of claims 1 to 14.

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