Electronic device and method for manufacturing an electronic device

Abstract

Electronic device and method for manufacturing an electronic device This description relates to a method for manufacturing an electronic device comprising: - the provision of a structure comprising a semiconductor substrate (102), conductive elements (132) above the semiconductor substrate, a first intermetallic dielectric layer (131) between the conductive elements, cavities (150) in the first intermetallic dielectric layer between two adjacent conductive elements, and a second intermetallic dielectric layer (144) above the first intermetallic dielectric layer and the cavities, the cavities being connected to each other so as to form a continuous extended cavity between the two adjacent conductive elements; - the formation of first, respectively second, orifices through the second intermetallic dielectric layer, extending to the cavities, respectively to the conductive elements;- the filling of the first and second orifices with a conductive material (148), the filling of the first orifices filling the cavities, forming conductive regions (155) connected to each other, and thus a conductive track, and forming first conductive vias (149A) connected to the conductive track, and the filling of the second orifices forming second conductive vias (149B) connected to the conductive elements. Figure for the abstract: Fig. 10;

Description

Title of the invention: Electronic device and method for manufacturing an electronic device. Technical field

[0001] This description relates generally to semiconductor-based electronic devices and to the manufacturing processes of semiconductor-based electronic devices.

[0002] In particular, the present description relates to interconnection in an electronic device. Previous technique

[0003] Semiconductor-based electronic devices generally comprise electronic components on and / or within a semiconductor substrate layer. The substrate layer may, for example, be a bulk semiconductor substrate or a silicon-on-insulator (SOI) layer. The fabrication of the electronic components is generally carried out in a front-end-of-line (FEOL) process. Once the FEOL process is complete, the fabrication of the electronic device continues by forming an interconnection structure comprising a network of electrical conduction paths intended to be connected to the electronic components. This is called, in the technical field, a back-end-of-line (BEOL) process.

[0004] Routing the conduction paths in the BEOL process requires the formation of several metallization levels (or metallization layers) above the substrate layer that contains the electronic components formed during the FEOL process. The metallization includes metallic vias extending perpendicularly to a top face of the substrate layer and metallic lines extending parallel to the top face of the substrate layer, with a via connecting metallic lines from two different metallization levels. Copper (Cu) is commonly used as the metallic material for the vias and metallic lines, although other metallic materials are also known to be used, such as aluminum (Al) for the metallic lines and / or tungsten (W) for the vias, and possibly for barrier layers.The interconnection structure typically includes a dielectric material at and / or between each metallization level, with the vias and metallic lines being surrounded, and electrically insulated from each other, by the dielectric material.

[0005] As electronic components become smaller and electronic devices more complex, there is a corresponding increase in the complexity of BEOL metallization, particularly for connecting more and more electronic components, and this may in particular require an increase in the number of metallization levels. At the same time, it may be desirable to have increasingly smaller interconnection structures to reduce the size of the electronic device. Summary of the invention

[0006] There is a need to improve semiconductor-based electronic devices, in particular to improve the interconnection of electronic components in an electronic device.

[0007] An embodiment overcomes all or part of the drawbacks of known electronic devices.

[0008] One embodiment provides a method for manufacturing an electronic device, the method comprising: - the provision of a structure comprising a semiconductor substrate on and in which electronic components are formed, first conducting elements above the semiconductor substrate, a first intermetallic dielectric layer between the first conducting elements, cavities in the first intermetallic dielectric layer between two adjacent first conducting elements among the first conducting elements, and a second intermetallic dielectric layer above the first intermetallic dielectric layer and the cavities, the cavities being connected to each other so as to form a continuous extended cavity between the two adjacent first conducting elements; - the formation of first and second orifices through the second intermetallic dielectric layer, the first orifices each extending to one of the cavities and the second orifices each extending to one of the first conducting elements; - the filling of the first and second orifices with a conductive material, the filling of the first orifices being carried out in such a way as to fill the cavities, forming conductive regions connected to each other, and thus a conductive track, the filling of the first orifices also forming first conductive vias connected to the conductive track, and the filling of the second orifices forming second conductive vias connected to the first conductive elements.

[0009] According to one embodiment, the supply of the structure includes the formation of the cavities which comprises: - the formation of third holes through the first intermetallic dielectric layer between the first two adjacent conducting elements, the formation of the third holes including an etching, for example an anisotropic etching and / or a dry etching; - the enlargement of the third orifices so as to form open cavities connected to each other in the first intermetallic dielectric layer, the enlargement of the third orifices including an etching, for example an isotropic etching and / or a wet etching; - the formation of the second intermetallic dielectric layer above the open cavities and the first intermetallic dielectric layer, so as to close the open cavities.

[0010] According to one embodiment, the process comprises, before the formation of the third orifices, the deposition of a first protective layer over the first intermetallic dielectric layer and the first conductive elements, then the formation of first openings in the first protective layer, the third orifices being formed at the right of the first openings, the formation of the first openings comprising an etching, for example an anisotropic etching and / or a dry etching.

[0011] According to one embodiment, the formation of first and second orifices includes anisotropic etching and / or dry etching.

[0012] According to one embodiment, the structure provided comprises other cavities in the first intermetallic dielectric layer between two other first adjacent conducting elements among the first conducting elements, the second intermetallic dielectric layer also extending over said other cavities, said other cavities being connected to each other and not filled with the conducting material, so as to form a continuous extended cavity between the two other first adjacent conducting elements.

[0013] One embodiment provides an electronic device comprising: - a semiconductor substrate on and in which electronic components are arranged; - the first conductive elements above the semiconductor substrate; - a first intermetallic dielectric layer between the first conducting elements; - conductive regions extending at least into the thickness of the first intermetallic dielectric layer between two first adjacent conducting elements among the first conducting elements, the conductive regions being connected to each other in the form of a conductive track; - a second intermetallic dielectric layer above the first intermetallic dielectric layer, the first conducting elements and the conducting track; - the first conductive vias passing through the second intermetallic dielectric layer and connected to the conductive track; - second conducting vias passing through the second intermetallic dielectric layer and connected to the first conducting elements.

[0014] According to one embodiment, the electronic device further comprises other cavities in the first intermetallic dielectric layer between two other first adjacent conducting elements among the first conducting elements, the second intermetallic dielectric layer also extending over said other cavities, said other cavities being connected to each other so as to form a continuous extended cavity between the two other first adjacent conducting elements.

[0015] The following embodiments may be applied to the device or method.

[0016] According to one embodiment, the first conducting elements are isolated from each other by the first intermetallic dielectric layer in a first direction of a plane substantially parallel to the plane of the semiconductor substrate, and the conducting regions are connected to each other in a second direction of the plane perpendicular to the first direction.

[0017] According to one embodiment, the conducting regions are also connected to each other in the first direction of the plane.

[0018] According to one embodiment, the lateral edges of the first conductive elements are protected by a second protective layer.

[0019] According to one embodiment, the conductive regions also extend into a pre-metal dielectric layer located between the semiconductor substrate and the first intermetallic dielectric layer, for example between the electronic components and the first intermetallic dielectric layer.

[0020] According to one embodiment, contacts passing through the pre-metal dielectric layer are connected to the electronic components and the first conductive elements, the conductive regions also extending between said contacts.

[0021] According to one embodiment, the conductive material comprises tungsten and / or the first conductive elements comprise copper or aluminum.

[0022] According to one embodiment, the first conducting elements and the first intermetallic dielectric layer form a first level of an interconnection structure.

[0023] According to one embodiment, a second metallization level comprises second conductive elements connected to the first conductive elements by the second conductive vias, and other second conductive elements connected to the conductive track by the first conductive vias.

[0024] According to one embodiment, the conductive track and the first conductive vias are included in a circuit for controlling electrical continuity between the conductive regions. Brief description of the drawings

[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0026] [Fig.1] is a longitudinal sectional view schematically and partially representing an example of an electronic device;

[0027] [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7], [Fig.8], [Fig.9] and [Fig.10] are longitudinal section views schematically and partially representing structures obtained at the end of successive intermediate steps of an example of a manufacturing process for an electronic device according to an embodiment;

[0028] [Fig.1 1] is a top view schematically and partially representing a structure that can be obtained at the end of the step represented in [Fig.9];

[0029] [Fig. 12] is a top view schematically and partially representing an electronic device that can be obtained at the end of the step shown in [Fig. 10]; and

[0030] [Fig. 13A] and [Fig. 13B] are top and three-dimensional views schematically and partially representing an electronic device according to an embodiment, such as the electronic device of [Fig. 12], with an additional second level of metallization

[0031] Figure 14 is a longitudinal cross-sectional view schematically and partially representing an electronic device according to another embodiment. Description of embodiments

[0032] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the manufacturing steps and details of the electronic components, for example the drain, source, and gate regions for a MOS transistor, are not detailed, as they are feasible with conventional electronic component manufacturing processes. Furthermore, the manufacturing steps and details of the interconnection structures are not described, as they can be achieved with the usual manufacturing processes for interconnection structures.

[0034] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0035] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0036] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0037] In the following description, the terms "insulating" and "conducting" mean, unless otherwise specified, electrically insulating and electrically conductive respectively.

[0038] In the following description, references to a substrate, unless otherwise specified, referencing a semiconductor substrate. In the following description, references to a via, unless otherwise specified, referencing a conductive via, for example, a metallic via.

[0039] In the following description, unless otherwise specified, a length corresponds to a dimension in a first direction, which corresponds to the longitudinal direction X shown in the figures; a width corresponds to a dimension in a second direction, orthogonal to the first direction X, which corresponds to the transverse direction Y shown in the figures; and a thickness or depth corresponds to a dimension in a direction perpendicular to the first and second directions, which corresponds to the vertical direction Z shown in the figures. In the case of a MOSFET transistor, the longitudinal direction X corresponds to the direction of the channel length between a source region and a drain region of the transistor.

[0040] Fig. 1 is a longitudinal sectional view schematically and partially representing an example of an electronic device 100.

[0041] The electronic device 100 of [Fig.1] can form a starting structure of the process described in relation to Figures 2 to 10.

[0042] The electronic device 100 comprises several MOSFET transistors 110 formed on and in a semiconductor substrate 102. In some embodiments, the substrate 102 is made of silicon or is a silicon-on-insulator (SOI) layer. The substrate 102 extends along an XY plane, or principal plane.

[0043] Although two transistors are illustrated in [Fig.1], any number of transistors and / or other electronic components can be formed on and / or in the substrate 102. The transistors, and more broadly the electronic components, can be positioned next to each other in the X direction and / or in the Y direction.

[0044] Each transistor 110 includes a gate region 111 covering a channel-forming region 103, or channel region, formed in the substrate 102. The channel region 103 is located between two doped semiconductor regions of the substrate 102, forming respectively the drain region 104 and the source region 105 of the transistor 110, or the source region 104 and the drain region 105 of the transistor 110.

[0045] The grid region 111 may be made of polycrystalline silicon (polysilicon) and / or a conductive material such as a rare-earth silicide, for example titanium silicide, or cobalt silicide, or a combination of several of these materials. The grid region 111 may be multilayered, for example, with a polysilicon layer and one (or more) layer(s) of conductive material. The grid region 111 is isolated from the substrate 102 by a grid insulator 112. The grid insulator, or another insulating layer, may also cover the side walls of the grid region 111. The grid insulator 112 may be made of a silicon oxide, such as silicon dioxide (SiO2).

[0046] The sides of the grid region 111 are covered by grid spacers 113. The grid spacers 113 comprise one or more dielectric layers. In some embodiments, the grid spacers 113 comprise silicon oxide, silicon dioxide, silicon nitride (e.g., Si3N4), or a combination of several of these materials. For example, the grid spacers 113 may comprise a first layer of silicon nitride, a second layer of silicon dioxide on top of the first layer, and a third layer of silicon nitride on top of the second layer. As illustrated in [Fig. 1], the grid spacers 113 may comprise a first layer and a second layer, each with L-shaped profiles in longitudinal section.

[0047] In some embodiments, a cover layer 114 covers the upper surface of the grid region 111. The cover layer 114 comprises a suitable conductive material, such as, for example, titanium, titanium nitride, tantalum, tantalum nitride, cobalt silicide (CoSi2), or a combination of several of these materials.

[0048] In some embodiments, a metal silicide layer 108, or silicide layer, is formed on each of the drain and source regions 104, 105. Such a silicide layer makes it possible to greatly reduce the value of the electrical access resistance of the contacts 120 described later, i.e. the resistance between the drain and source regions and the contacts.

[0049] An etch-stop layer 106 is formed on the transistors 110, that is, at least on the gate regions 111, the source and drain regions 104, 105, and the gate spacers 113. The etch-stop layer 106 can be used to control subsequent etching steps, for example, to form contacts 120. The etch-stop layer 106 can comprise a nitride such as silicon nitride (e.g., Si3N4), carbon-silicon nitride, or any other suitable material.

[0050] A pre-metal dielectric layer 107, or PMD layer, is formed on the etching stop layer 106. In some embodiments, the PMD layer 107 comprises a silicon oxide, such as silicon dioxide (SiO2). In other embodiments, the PMD layer 107 comprises a silicon phosphide glass known by the English abbreviation "PSG" (phospho-silicon glass), or a silicon borophosphide glass known by the English abbreviation "BPSG" (borophospho-silicon glass). However, the PMD layer 107 may comprise a combination of several of these materials, or any other suitable material.

[0051] Contacts 120 are formed through the PMD layer 107 and the etching stop layer 106 to physically and electrically contact the source and drain regions 104, 105.

[0052] To form these contacts 120, openings are made through the PMD layer 107 and the etching stop layer 106 at least as far as the silicide layer 108 if it is present, or as far as the source and drain regions 104, 105 otherwise, typically by a suitable masking technique, such as photolithography, followed by a suitable etching technique. Next, a barrier layer 121 is conformally deposited on the inner walls and bottom of these openings. The barrier layer 121 comprises a suitable conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, or a combination of several of these materials.The barrier layer 121 is formed by a suitable process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or electrodeposition. Then, a material. Conductive filler 122 is formed on the barrier layer 121 to fill the openings. In some embodiments, the conductive filler 122 comprises tungsten, cobalt, copper, or a combination of several of these materials. The conductive filler 122 is formed by a suitable process such as CVD, PVD, ALD, or electrodeposition. The upper portions of the barrier layer 121 and the conductive filler 122 can be removed with a suitable planarization technique, such as chemical mechanical polishing (CMP).

[0053] Thus, the electrical contacts 120 pass through the PMD layer 107 so as to couple the drain and source regions 104, 105 to an interconnection structure of which a first level of metallization 130 can be seen in the [Fig. 1].

[0054] The first metallization level 130 comprises conductive elements 132, such as metallic lines (extended in the Y direction), insulated from each other by dielectric elements, or insulating elements 1310. All of these dielectric elements 1310 together form an intermetallic dielectric layer 131 (first intermetallic dielectric layer), or IMD layer 131. The conductive elements 132 are connected to the contacts 120, preferably positioned substantially directly above the contacts 120.

[0055] The first level of metallization 130 can be formed by a subtractive process, for example for aluminium lines, or by a Damascene type process, for example for copper lines.

[0056] An example of a subtractive process is described below. A conductive layer, for example made of aluminum, is deposited on the PMD layer 107 and the contacts 120. The conductive layer is deposited by a suitable process such as CVD, PVD, or ALD, or by electrodeposition. The conductive layer is then etched through an etching mask, obtained, for example, by photolithography, the etching forming openings through the conductive layer to the PMD layer 107. The etching mask is sized so that the remaining portions of the conductive layer, forming the conductive elements 132, are positioned substantially over the contacts 120. The etching mask is then removed.A protective layer 133 can then be deposited to cover the upper surfaces and side walls of the conductive elements 132, and it generally also covers the exposed surfaces of the PMD layer 107 at the bottom of the openings. The protective layer 133 can be made of a nitride, such as silicon nitride, or any other suitable material. The protective layer 133 can be deposited by CVD, or any other suitable technique. The portions of the protective layer located on the exposed surfaces of the PMD layer 107 at the bottom of the openings can then be removed. Then, a . The IMD layer 131 is formed at least to fill the gaps between the conductive elements 132, forming the insulating elements 1310. The IMD layer 131 comprises, for example, a silicon oxide, such as silicon dioxide (SiO2), or any other dielectric material. The IMD layer 131 is deposited by a suitable technique, such as CVD. Excess portions of the IMD layer 131 can be removed by means of planarization, such as CMP.

[0057] According to a variant of the subtractive process described, an initial protective layer can be formed on the conductive layer before etching it, in order to protect the underlying layers during etching, the etching of the conductive layer including the etching of the initial protective layer through the etching mask, so that the initial protective layer remains only on the conductive elements after etching.

[0058] An example of a Damascus process is described below. An IMD layer 131 is deposited on the PMD layer 107 and the contacts 120. The IMD layer 131 may be similar to the IMD layer described above, as may the IMD layer deposition technique. Next, the IMD layer 131 is etched through an etching mask, obtained, for example, by photolithography, forming openings through the IMD layer 131. The remaining portions of the IMD layer 131 form the insulating elements 1310. The etching mask is sized so that the openings in the IMD layer 131 are positioned substantially directly above the contacts 120. The etching mask is removed. A protective layer 133 may then be deposited in the openings, so as to cover the side walls of the openings, and it also generally covers the bottoms of the openings and the insulating elements 1310.The protective layer 133 may be similar to the protective layer described above, as may the protective layer deposition technique. The portions of the protective layer 133 located at the bottom of the openings and on the insulating elements 1310 may then be removed. Next, a barrier layer 134 is deposited in the openings so as to cover the side walls and bottoms of the openings, and it also generally covers the insulating elements 1310. The barrier layer 134 comprises a suitable conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, or a combination of several of these materials. The barrier layer 134 is formed by a suitable process such as CVD, PVD, ALD, or electrodeposition.Next, a conductive material, for example copper, is formed at least to fill the openings between the insulating elements 1310, forming with the barrier layer 134 the conductive elements 132. Excess parts of the conductive layer and the barrier layer 134 located above the insulating elements 1310 can be removed by means of a planarization such as a CMP.

[0059] According to a variant of the Damascus process described, an initial protective layer 135 can be formed on the PMD layer 107 and the contacts 120 before deposition of the IMD layer, in order to protect the underlying layers during the etching of the IMD layer 131, the etching of the IMD layer 131 including the etching of the initial protective layer 135 through the etching mask, the initial protective layer 135 remaining under the unetched portions of the IMD layer 131.

[0060] In both techniques, the protective layer 133 is found on the sides of the conductive elements 132, which can protect the conductive elements 132 during subsequent manufacturing steps, such as etching to form cavities as described later.

[0061] By way of illustration, [Fig. 1] shows conducting elements 132 made of copper obtained by the Damascus process. However, these could be conducting elements made of aluminum obtained by the subtractive process. The same numerical references have therefore been used for similar elements in the description of both processes.

[0062] As can be seen in [Fig.1], a protective layer 141 is formed on the first metallization level 130, i.e. on the conductive elements 132 and the IMD layer 131. The protective layer 141, as well as the technique for deposition of the protective layer 141, can be similar to the protective layer 133 described above in connection with [Fig.1].

[0063] The starting structure of the manufacturing process described in connection with Figures 2 to 10 may not include the protective layer 141, the deposition of this protective layer 141 being part of the manufacturing process.

[0064] Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 and Fig. 10 are longitudinal section views schematically and partially representing structures obtained at the end of successive intermediate steps of an example of a manufacturing process for an electronic device according to an embodiment.

[0065] Fig. 2 shows a structure obtained after the formation of an etching mask 142 on the protective layer 141. The etching mask 142 can be obtained by a photolithography technique.

[0066] The etching mask 142 is intended to be used to form cavities 150 in the IMD layer 131 and the PMD layer 107, between the conductive elements 132, and optionally between the contacts 120, as described below in connection with Figures 3 to 7. Openings 142A in the etching mask 142 can be formed at desirable locations to form these cavities, such as for example above the gate regions 111 of the transistors 110.

[0067] Fig. 3 shows a structure obtained after etching portions of the protective layer 141 through the openings 142A of the etching mask 142, the etched portions forming openings 141A (first openings) in the protective layer 141. This etching is for example a dry etching, of the plasma etching type.

[0068] Figure 4 shows a structure obtained after etching orifices 143 (third orifices) through the IMD layer 131 into the PMD layer 107, between two conductive elements 132. The etching is carried out through the openings 142A of the etching mask 142 and the openings 141A of the protective layer 141. The orifices 143 can be formed by means of a suitable anisotropic etching process, such as a dry etching, for example, of the plasma etching type. The diameter of the orifices 143 can correspond substantially to the diameter of the openings 141A in the protective layer 141.

[0069] The engravings in figures 3 and 4 can be produced in a single engraving step.

[0070] The engraving mask 142 is then removed.

[0071] Figure 5 shows a structure obtained by enlarging the orifices 143 by etching, so as to form open cavities 151 in the IMD layer 131 and the PMD layer 107 between two conductive elements 132, and optionally between two contacts 120. The openings of the open cavities 151 correspond to the openings 141A of the protective layer 141. The open cavities 151 can be formed by means of a suitable isotropic etching, advantageously selective of the material of the IMD layer 131 and the PMD layer 107 with respect to the material of the protective layer 141, to avoid etching the protective layer 141.In some embodiments, isotropic etching is wet etching, for example carried out with hydrofluoric acid (HF) which can be in vapor form, hydrochloric acid (HCl), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), sodium hydroxide (NaOH), nitric acid (HNO3), buffered oxide etch (BOE), or a mixture of several of these products.

[0072] The diameter of the orifices 143 can be used to define the dimensions of the open cavities 151. For example, the larger the diameter of the orifices 143, the larger the average diameter of the open cavities 151.

[0073] The protective layer 133 which is located on the side walls, or flanks, of the conductive elements 132 can advantageously protect the conductive elements 132 during anisotropic etching and / or isotropic etching.

[0074] The enlargement of the orifices 143 is advantageously carried out in such a way that all or part of the open cavities 151 can be connected to each other, forming a open cavity continuous in one or more directions of the XY plane between the conducting elements 132, for example at least in the Y direction.

[0075] The longitudinal section of Figures 5 and 6 shows a single orifice 143 between two adjacent conducting elements 132 in the X direction, then a single open cavity 151 by enlarging the orifice 143 between two adjacent conducting elements 132 in the X direction. This section corresponds to an example, and it is possible to form several orifices 143, then several adjacent open cavities 151 connected to each other in the X direction, and then several cavities 150 connected to each other, between two adjacent conducting elements in the X direction, as illustrated in [Fig. 11] described later.

[0076] Figure 6 shows a structure obtained after the formation of a layer The intermetallic dielectric 144 (second intermetallic dielectric layer), or IMD layer 144, is applied to the protective layer 141 and to the openings of the open cavities 151, so as to close these open cavities 151, forming closed cavities 150, which will be referred to as cavities (air gaps). The IMD layer 144 can be formed using materials and processes similar to those of the IMD layer 131 as described above. Passing through the openings 141A of the protective layer 141, the dielectric material of the IMD layer 144 can coat the internal surfaces of the cavities 150 before closing the open cavities 151, forming an internal coating 152 within the cavities 150.

[0077] In some embodiments, the cavities 150 are above the gate regions 111 of the transistors 110, and they may have a width greater than the combined width of the gate region 110 and the gate spacers 113.

[0078] Preferably, the cavities 150 located between two adjacent conducting elements 132 are connected to each other in one or more directions, forming one or more continuous extended cavities. In other words, cavities 150 positioned between the same pair of adjacent conducting elements 132 can form a continuous extended cavity, and other cavities 150 positioned between another pair of adjacent conducting elements 132 can form another continuous extended cavity. For example, the cavities can be connected to each other in the transverse direction Y, or even also in the longitudinal direction X, as illustrated in Figures 11 and 12 described below.

[0079] Figure 7 shows a structure obtained after the formation of a layer of Planarization 145, for example a layer of silicon oxide. This planarization layer is optional and can be omitted.

[0080] Alternatively, instead of the electronic device 100 of [Fig. 1], the manufacturing process may start from the structure shown in any one of the figures 2 to 7, for example of the structure represented in [Fig.6] (without planarization layer) or in [Fig.7] (with planarization layer).

[0081] Fig. 8 shows a structure obtained after the formation of an etching mask 146 on the planarization layer 145. The etching mask 146 can be obtained by a photolithography technique.

[0082] Openings 146A in the etching mask 146 can be formed at desirable locations to form in the IMD layer 144 orifices 147 connected to the cavities 150 and the conductive elements 132.

[0083] Figure 9 shows a structure obtained after etching the planarization layer 145, the IMD layer 144, and the protective layer 141 to form holes 147 through these layers. The etching is performed through the openings 146A of the etching mask 146. The holes 147 comprise first holes 147A, which are formed at the cavities 150, and second holes 147B, which are formed at the conductive elements 132. The first holes 147A allow the cavities 150 to be reopened and filled with conductive material, thus filling the continuous extended cavities, as described later. The first filled holes form first vias, as described later. For example, the first orifices 147A are centered with the openings 141A of the protective layer 141. The second orifices 147B, once filled with conductive material, form second vias, as described later.

[0084] Not all cavities 150 of the same continuous extended cavity are necessarily connected to a first orifice 147A. Indeed, since the cavities 150 of the same continuous extended cavity are interconnected, it may be sufficient to have only two first orifices 147A to fill the cavities 150 with conductive material, for example, a first inlet orifice of the conductive material and a first outlet orifice of the conductive material. However, depending, for example, on the length of the continuous extended cavity, more than two first orifices may be required to ensure that it can be properly filled.

[0085] Fig. 10 shows a structure obtained after filling the orifices 147 with a conductive material 148, which includes, for example, tungsten, forming conductive vias 149.

[0086] The filling is carried out using an appropriate deposition technique such as an ALD technique, or by a PVD or CVD technique, or by electrodeposition.

[0087] The first orifices 147A allow the cavities 150 to be filled with the conductive material 148, forming conductive regions 155, and the first orifices 147A form first vias 149A once filled, each first via 149A being connected to one of the conductive regions 155.

[0088] Insofar as the cavities 150 between the conductive elements 132 are connected to each other in one or more directions, forming continuous extended cavities, the conductive regions 155 are also connected to each other, forming continuous conductive tracks, or conductive traces (an example of a conductive trace is shown in Figures 12, 13A, and 13B). In other words, conductive regions 155 positioned between the same pair of adjacent conductive elements 132 can form a conductive trace, and other conductive regions 155 positioned between another pair of adjacent conductive elements 132 can form another conductive trace. Each first via 149A is connected to a conductive trace.

[0089] The vias 149 further include second vias 149B which are connected to the conductive elements 132 and which participate in the interconnection of the conductive elements 132 of the first level of metallization 130 with conductive elements of a second level of metallization (represented in Figures 13A and 13B).

[0090] In the manufacturing process described in relation to Figures 8 to 10, a planarization layer 145 was assumed to exist, but the manufacturing process can be easily adapted in the case where there is no planarization layer. For example, the etching mask 146 of [Fig. 8] is then formed on the IMD layer 144, and the holes 147 and vias 149 pass through the IMD layer 144 and the protective layer 141.

[0091] The top views of figures 11 and 12 described below are views taken along a horizontal section plane AA visible in figures 9 and 10, in the IMD 131 layer of the first metallization level 130.

[0092] Fig. 11 is a top view schematically and partially representing a structure that can be obtained at the end of the step shown in Fig. 9.

[0093] Figure 11 illustrates an embodiment in which several cavities 150 are formed in the IMD layer 131 between two conductive elements 132, and are connected to each other in both the longitudinal direction X and the transverse direction Y. A continuous extended cavity 1150 is obtained between the two conductive elements 132. For example, the continuous extended cavity 1150 extends substantially parallel to the conductive elements 132. The openings 141A of the protective layer 141 are shown inside each cavity 150.

[0094] Only two conducting elements 132 are shown in [Fig. 11], although there may be others, as shown in [Fig. 9]. Several continuous extended cavities 1150 may then be present. [Fig. 9] could correspond to a section along the section plane BB shown in [Fig. 11], which passes through only an opening 141A between the two conducting elements 132. Indeed, in the [Fig.9], as in [Fig.11], that each opening 141A is not necessarily centered with respect to the continuous extended cavity 1150 in the X direction. Thus, the cavity 150 of [Fig.9] may in fact correspond to a portion of the continuous extended cavity 1150 seen in the section plane BB.

[0095] In some embodiments, the IMD layer 131 has a length L1 between the conductive elements 132, measured in the X direction, of between 0.2 pm and 5 pm. The IMD layer 131 may have forbidden zones 1130 adjacent to each conductive element 132 which are preferably not etched to form the cavities 150, in order to avoid damaging the conductive elements 132. For example, the forbidden zones 1130 have a length L2, measured in the X direction, of between 0.01 pm and 1 pm.

[0096] The apertures 141A shown are square. In some embodiments, the apertures 141A have a dimension L3, measured in each of the X and Y directions, ranging from 50 nm to 300 nm. The shape shown is not limiting, and the apertures 141A may have any suitable shape, such as rectangular, circular, oval, triangular, hexagonal, octagonal, or similar shapes, and not all apertures 141A may have the same shape.

[0097] The openings 141A are shown arranged in a staggered pattern. Generally, the arrangement of the orifices 143 corresponds to the arrangement of the openings 141A, so the orifices 143 can also be arranged in a staggered pattern. This staggered shape of the orifices 143 can be advantageous for the cavities 150 formed during isotropic etching to be connected together and form the continuous extended cavity 1150. In the example shown, the openings 141A are arranged in two columns between the conducting elements 132, although they could be arranged in any suitable number of columns, for example, one to five columns. Furthermore, in the example shown, the openings 141A in one column are offset in the Y direction relative to the openings 141A in the other column. In some embodiments, the 141A apertures are arranged with a PI pitch between 50 nm and 300 nm, or between 50 nm and 200 nm.However, the 141A openings can be arranged in any suitable pattern. Thus, the configuration shown is not limiting and other configurations are possible, provided that this allows for the formation of a continuous extended cavity.

[0098] Each cavity 150 has been represented in a simplified manner with a circular cross-section centered with respect to the aperture 141A of the protective layer 141, the circles of the cavities overlapping. In some embodiments, the distance L4 between the aperture 141A and the wall of the cavity 150 is between 0 and 500 nm, this distance being, for example, induced by the isotropic etching time. In practice, the The cross-section of each cavity may have a different shape, which is not perfectly circular, and it may not be perfectly centered with respect to the opening 141A of the protective layer 141. More generally, the cavities 150 may have various shapes, with cross-sections that are not necessarily uniform according to the level of the cutting plane.

[0099] In some embodiments, the continuous extended cavity 1150 has a length L5, measured in the X direction, of between 0.1 pm and 5 pm.

[0100] Anisotropic etching to form the orifices 143 and isotropic etching to enlarge the orifices 143 and thus form the cavities 150, can be carried out so that the length L5 of the continuous extended cavity 1150 is less than or equal to the length L1 of the IMD layer 131 between the conducting elements 132 less the summed lengths L2 of the two forbidden zones 1130. In addition, the orifices 143 can be positioned so that the continuous extended cavity 1150 is substantially centered in the IMD layer 131 between the conducting elements 132.

[0101] The cavities 150 represented in [Fig.1 1] are thus distributed in a staggered manner in the two directions X and Y and overlap, but other configurations are conceivable, insofar as a continuous extended cavity is formed in the longitudinal direction X and / or in the transverse direction Y.

[0102] Fig. 12 is a top view schematically and partially representing an electronic device that can be obtained at the end of the step shown in Fig. 10.

[0103] The electronic device of [Fig.12] corresponds to the structure of [Fig.11], after the cavities 150 have been filled with conductive material, forming conductive regions 155, the whole of the conductive regions forming a conductive track 1155. The rest of the description of [Fig.11] can be applied to [Fig.12].

[0104] It can be seen that the conductive track 1155 extends substantially parallel to the conductive elements 132.

[0105] Only two conductive elements 132 are shown in [Fig. 12], although there may be others, as shown in [Fig. 10]. There may then be several conductive tracks 1155. [Fig. 10] could correspond to a section along the section plane BB shown in [Fig. 12], which passes through only one opening 141A between the two conductive elements 132. Indeed, it can be seen in [Fig. 10], as in [Fig. 12], that each opening 141A is not necessarily centered with respect to the conductive track 1155 in the X direction. Thus, the conductive region 155 of [Fig. 10] may in fact correspond to a portion of the conductive track 1155 seen in the section plane BB of [Fig. 12].

[0106] Fig. 13A and Fig. 13B are top and three-dimensional views schematically and partially representing an electronic device according to a embodiment, such as the electronic device of [Fig. 12], with in addition a second level of metallization.

[0107] More specifically, Figures 13A and 13B show the electronic device of [Fig. 12], with an additional second metallization level 230 (M2) comprising second metal lines 232 above the first metallization level 130 (M1) which comprises the first metal lines 132 in the IMD layer 131. The second vias 149B connect the first metal lines 132 with some of the second metal lines 232, while the first vias 149A can connect other second metal lines 232 with each other via the conductive track 1155, creating an interconnection circuit 300. Thus, the metallization of the cavities 150 makes it possible to create an additional interconnection level.

[0108] The [Fig. 14] is a longitudinal sectional view schematically and partially representing an electronic device according to another embodiment.

[0109] In this embodiment, the electronic device includes additional cavities 150' between two other adjacent conducting elements, that is, between a pair of conducting elements 132, 132' different from the pair of conducting elements 132 described in Figures 1 to 10. Only one additional cavity 150' is shown, but there are several, at least in the transverse Y direction. Two different pairs of conducting elements may include the same conducting element 132, as shown in [Fig. 14]. Alternatively, two different pairs of conducting elements may not include the same conducting element. The other cavities 150' are connected to each other, at least in the Y direction, but they are not filled with the conducting material 148.

[0110] In other words, in the process, no orifice 147 was formed up to these other cavities 150'. The etching mask 146 of [Fig.8] can be adapted so that it does not include openings 146A at the other cavities 150'.

[0111] Thus, an electronic device can include both conductive regions 155 connected together to form a conductive track between two conductive elements, and cavities 150' not filled with conductive material and connected together to form a continuous extended cavity between two other conductive elements.

[0112] It can thus be seen that the embodiments make it possible to form an additional interconnection level, using each conductive trace and the first vias connected to that trace, by adapting a standard electronic device manufacturing process. In particular, an air gap manufacturing process can be used by simply adjusting the etching parameters to obtain interconnected cavities, and thus a continuous extended cavity, and a BEOL process can be used by modifying the etching mask used to form the holes to create the conductive vias between two metallization levels, to that some of the openings are used to reopen the cavities to fill them with metal at the same time as the conductive vias are formed.

[0113] One application of the embodiments relates to the control of cavity formation. By metallizing the cavities and connecting them to conductive vias, an electrical circuit can be formed and the continuity of the metallized cavities can be controlled, for example by controlling the conductivity of the electrical circuit formed by the conductive track and the vias.

[0114] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will be apparent to those skilled in the art. In particular, in the embodiments, MOSFET transistors have been shown as electronic components in the electronic device. This is not limiting; the described embodiments can be applied to an electronic device comprising other electronic components, for example, other types of transistors and / or diodes. More generally, the described embodiments can be applied to any electronic device comprising electronic components and an interconnection structure.

[0115] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing an electronic device, the method comprising: - providing a structure comprising a semiconductor substrate (102) on and in which electronic components (110) are formed, first conducting elements (132) above the semiconductor substrate, a first intermetallic dielectric layer (131) between the first conducting elements, cavities (150) in the first intermetallic dielectric layer between two adjacent first conducting elements among the first conducting elements, and a second intermetallic dielectric layer (144) above the first intermetallic dielectric layer (131) and cavities (150), the cavities being connected to each other so as to form a continuous extended cavity (1150) between the two adjacent first conducting elements;- the formation of first orifices (147A) and second orifices (147B) through the second intermetallic dielectric layer (144), the first orifices (147A) each extending to one of the cavities (150) and the second orifices (147B) each extending to one of the first conducting elements (132); - the filling of the first and second orifices with a conductive material (148), the filling of the first orifices (147A) being carried out so as to fill the cavities (150), forming conductive regions (155) connected to each other, and thus a conductive track (1155), the filling of the first orifices (147A) also forming first conductive vias (149A) connected to the conductive track (1155), and the filling of the second orifices (147B) forming second conductive vias (149B) connected to the first conductive elements.;

2. A method according to claim 1, wherein the provision of the structure includes the formation of the cavities (150) which includes: - the formation of third orifices (143) through the first intermetallic dielectric layer (131) between the first two adjacent conducting elements (132), the formation of the third orifices including an etching, for example an anisotropic etching and / or a dry etching; - the enlargement of the third orifices (143) so as to form open cavities (151) connected together in the first intermetallic dielectric layer, the enlargement of the third orifices comprising an etching, for example an isotropic etching and / or a wet etching; - the formation of the second intermetallic dielectric layer (144) above the open cavities (151) and the first intermetallic dielectric layer (131), so as to close the open cavities.

3. A method according to claim 2, comprising, prior to the formation of the third orifices (143), the deposition of a first protective layer (141) over the first intermetallic dielectric layer (131) and the first conductive elements (132), then the formation of first openings (141A) in the first protective layer, the third orifices (143) being formed at the right of the first openings, the formation of the first openings comprising an etching, for example an anisotropic etching and / or a dry etching.

4. A method according to any one of claims 1 to 3, wherein the formation of first (147A) and second orifices (147B) comprises anisotropic etching and / or dry etching.

5. A method according to any one of claims 1 to 4, wherein the supplied structure comprises further cavities (150') in the first intermetallic dielectric layer (131) between two other first adjacent conducting elements (132, 132') among the first conducting elements, the second intermetallic dielectric layer (144) also extending over said further cavities, said further cavities being connected together and not filled with the conducting material, so as to form a continuous extended cavity between the two other first adjacent conducting elements.

6. Electronic device comprising: - a semiconductor substrate (102) on and in which electronic components (110) are arranged; - first conductive elements (132) above the semiconductor substrate; - a first intermetallic dielectric layer (131) between the first conductive elements; - conductive regions (155) extending at least through the thickness of the first intermetallic dielectric layer between two first adjacent conducting elements among the first conducting elements, the conductive regions being connected to each other in the form of a conductive track (1155); - a second intermetallic dielectric layer (144) above the first intermetallic dielectric layer, the first conducting elements and the conductive track; - first conducting vias (149A) passing through the second intermetallic dielectric layer and connected to the conductive track (1155); - second conducting vias (149B) passing through the second intermetallic dielectric layer and connected to the first conducting elements.

7. Device according to claim 6, further comprising other cavities (150') in the first intermetallic dielectric layer (131) between two other first adjacent conducting elements (132, 132') among the first conducting elements, the second intermetallic dielectric layer (144) also extending over said other cavities, said other cavities being connected together so as to form a continuous extended cavity between the two other first adjacent conducting elements.

8. Device according to claim 6 or 7, wherein the first conducting elements (132) are insulated from each other by the first intermetallic dielectric layer (131) in a first direction (X) of a plane substantially parallel to the plane of the semiconductor substrate (102), and the conducting regions (155) are connected to each other in a second direction (Y) of the plane perpendicular to the first direction.

9. Device according to claim 8, wherein the conducting regions (155) are also connected to each other in the first direction (X) of the plane.

10. Device according to any one of claims 6 to 9, wherein the lateral edges of the first conductive elements (132) are protected by a second protective layer (133).

11. A device according to any one of claims 6 to 10, wherein the conducting regions (155) also extend into a pre-metal dielectric layer (107) located between the semiconductor substrate (102) and the first intermetallic dielectric layer (131), for example between electronic components (110) and the first intermetallic dielectric layer (131).

12. Device according to claim 11, wherein contacts (120) passing through the pre-metal dielectric layer (107) are connected to the electronic components (110) and to the first conductive elements (132), the conductive regions (155) also extending between said contacts.

13. Device according to any one of claims 6 to 12, wherein the conductive material comprises tungsten and / or the first conductive elements comprise copper or aluminum.

14. Device according to any one of claims 6 to 13, wherein the first conducting elements (132) and the first intermetallic dielectric layer (131) form a first level (130) of an interconnection structure.

15. Device according to any one of claims 6 to 14, wherein a second metallization level (230) comprises second conductive elements (232) connected to the first conductive elements (132) by the second conductive vias (149B), and other second conductive elements (232) connected to the conductive track (1155) by the first conductive vias (149A).

16. Device according to any one of claims 6 to 15, wherein the conductive track (1155) and the first conductive vias (149A) are included in a circuit for controlling electrical continuity between the conductive regions (155).

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