Method for manufacturing vertical transistor gates and corresponding integrated circuit

Abstract

The integrated circuit fabrication process includes the formation of vertical gates (VG) of transistors, comprising, in a semiconductor substrate (SUB) having a front face (FA), the formation of gate trenches (TRG, TRTA) extending in a first direction (X) from the front face, and subsequently, the formation of shallow isolation trenches (STI) extending in a second direction (Y) from the front face perpendicular to the first direction, delimiting between them active regions (ACT) and the vertical gates (VG). Figure for the abbreviation: Fig 6C

Description

Title of the invention: Method for manufacturing vertical transistor gates and corresponding integrated circuit

[0001] Implementation and embodiment methods relate to integrated circuits, in particular the manufacture of vertical gate transistors.

[0002] Fig. 1 illustrates an example of classical formation of vertical gate transistors in a SUB semiconductor substrate, in a perspective view oriented by an orthogonal XYZ frame, and in a top view located in an XY plane.

[0003] The grid regions TRG are formed in trenches extending vertically Z into the semiconductor substrate SUB, and extending continuously in a first direction X through active regions ACT of the substrate extending in a second direction Y and delimited by shallow isolation regions STI.

[0004] Conduction regions of the transistor are typically formed in the active region on either side of the vertical gate TRG.

[0005] This type of conventional formation has the disadvantage of an "irreducible" pitch (PTx) in the first X direction between two vertical gate transistors. Indeed, a reduction in the X direction between two adjacent active regions (ACT) increases the risk and amount of current leakage (usually called "reachthrough") from the conduction regions of the neighboring transistors. The leakage travels via a conduction channel formed along the trench containing the gate regions in the substrate (SUB), below the depth of the shallow isolation regions (STI).Indeed, due to a greater trench etching dynamic in the STI dielectric material than in the SUB substrate semiconductor material, there is classically a region suitable for forming a conduction channel at the interface of the vertical grid trenches with the substrate below the shallow STI insulation trenches, even if the depth of the vertical grids in the SUB substrate and the ACT active regions is otherwise less than the depth of the shallow STI insulation regions.

[0006] Fig. 2 illustrates another example of classical formation of vertical gate transistors in a SUB semiconductor substrate, in a perspective view oriented by an orthogonal XYZ frame, and in a top view located in an XY plane.

[0007] The TRG gate regions are individually formed in local trenches, i.e., in wells, extending vertically Z into the semiconductor substrate SUB. Each trench or well formation is designed to constitute a single vertical transistor gate.

[0008] Conduction regions of the transistor are typically formed in the active regions on either side, in the second Y, of the vertical gate TRG.

[0009] This type of conventional formation also presents the disadvantage of an "irreducible" pitch PTx (usually referred to as "pitch" in English) in the first X direction between two vertical gate transistors. Indeed, the design rules for the individual vertical gates impose a minimum spacing Amin, in the first X direction, between the etchings of the individual "wells" containing the gates. A reduction in the distance in the X direction between two adjacent active regions ACT is thus limited by the precision of the etching processes for this type of trench or well.

[0010] However, there is a constant need to reduce the dimensions of semiconductor devices and integrated circuits, usually expressed according to the principle of Moore's Law.

[0011] Implementation and embodiment methods defined below propose solutions to the difficulties mentioned above, allowing the PTx step (usually "pitch" in English) to be reduced in the first direction X between two vertical gate transistors.

[0012] According to one aspect, a method for manufacturing an integrated circuit is proposed in this regard, comprising a formation of vertical transistor gates, comprising, in a semiconductor substrate having a front face, a formation of gate trenches extending in a first direction from the front face, and subsequently a formation of shallow isolation trenches extending in a second direction from the front face perpendicular to the first direction, delimiting between them active regions and the vertical gates.

[0013] Thus, because the formation of shallow isolation trenches occurs after the formation of the grid trenches, the delimitation of the active regions in the semiconductor substrate also delimits the vertical grids within the grid trenches. In other words, the vertical grids are thus individualized along the first direction, from each continuous grid trench in the first direction, in a manner that is said to be "self-aligned" with the delimitation of the active regions by the formation of the shallow isolation regions.

[0014] Indeed, the expression "self-aligned" usually means, in the field of semiconductor device manufacturing, that the aligned position of two entities comes from a common formation step, and, in particular, does not result from the positioning of a second formation aligned on an already formed element.

[0015] According to one embodiment, the formation of the grid trenches comprises engraving first trenches penetrating vertically into the substrate from the front face and extending longitudinally in the first direction, the sides of the first trenches having an oriented inclination such that the width of the first trenches, in the second direction, is larger at the front face than at the bottom of the first trenches.

[0016] The formation of the grid trenches may further include, for example in a conventional manner, the formation of a dielectric layer such as silicon dioxide, on the bottom and sides of the first trenches, and the filling of the first trenches with a conductive material such as polycrystalline silicon.

[0017] According to one embodiment, the formation of shallow isolation trenches includes an engraving of second trenches extending vertically into the substrate from the front face and extending longitudinally in the second direction, the sides of the second trenches having an oriented inclination such that the width of the active regions and the vertical grids delimited between them, in the first direction, is greater at the bottom of the first trenches than at the front face.

[0018] The formation of shallow insulation trenches may further include, for example in a conventional manner, filling the second trench with a dielectric material, typically silicon dioxide.

[0019] According to one embodiment, the method comprises a formation of metallic contacts linking the vertical grids aligned in the first direction to a metallic track in at least a first level of metal.

[0020] According to one embodiment, the formation of the grid trenches comprises at least one of the following: - the formation of initial grid trenches with an initial depth less than the depth of the shallow isolation regions, - a formation of second grid trenches having a second depth greater than the depth of the shallow isolation regions.

[0021] According to one embodiment, the process includes, prior to forming in the semiconductor substrate, a succession of P-type and N-type cells alternating in the first direction, positioned opposite the locations of the future active regions.

[0022] According to another aspect, an integrated circuit is also proposed, comprising vertical gate transistors in a semiconductor substrate having a front face, the vertical gates being laterally delimited by shallow isolation trenches located on either side of the vertical gates in a first direction of the plane of the front face, and by active regions of the semiconductor substrate located on either side of the vertical gates in a second direction of the plane of the front face perpendicular to the first direction; the width of the vertical gates in the first direction being strictly equal to the width of the active regions in the first direction.

[0023] The equality between the width of the vertical grids and the width of the active regions in the first direction is a direct consequence of the delimitation of the self-aligned vertical grids with the delimitation of the active regions, both made between the lateral isolation regions.

[0024] According to one embodiment, the sides of the vertical grids, located on either side of the vertical grids in the first direction, have an oriented inclination such that the width of the vertical grids in the first direction is greater at the bottom of the vertical grids than at the front face of the substrate.

[0025] The vertical grids may further comprise, for example in a conventional manner, a volume of conductive material such as polycrystalline silicon, wrapped by a dielectric layer such as silicon dioxide, on the bottom and the lateral sides on either side of the vertical grids in the second direction.

[0026] Shallow insulation trenches may also include, for example in a conventional manner, a filling of second trenches with a dielectric material, typically silicon dioxide.

[0027] According to one embodiment, the sides of the vertical grids, located on either side of the vertical grids in the second direction, have an oriented inclination such that the width of the vertical grids in the second direction is greater at the front face of the substrate than at the bottom of the vertical grids.

[0028] According to one embodiment, the integrated circuit further comprises metallic contacts connecting the vertical grids aligned in the first direction to a metallic track located in at least a first metal level.

[0029] According to one embodiment, the vertical gate transistors comprise at least one of the following: - a group of transistors having first vertical gates having a first depth less than the depth of the shallow isolation regions, - a group of transistors having second vertical gates having a second depth greater than the depth of the shallow isolation regions.

[0030] According to one embodiment, the active regions comprise a succession of P-type boxes and N-type boxes alternating in the first direction.

[0031] Other advantages and features of the invention will become apparent from an examination of the detailed description of implementations and embodiments, which are by no means limiting, and the accompanying drawings, in which the figures:

[0032] [Fig.l] ;

[0033] [Fig.2] previously described, illustrate examples of classic formations of vertical gate transistors;

[0034] [Fig.3A] ;

[0035] [Fig.3B];

[0036] [Fig.3C] ;

[0037] [Fig.4A] ;

[0038] [Fig.4B] ;

[0039] [Fig.4C] ;

[0040] [Fig.5A] ;

[0041] [Fig.5B] ;

[0042] [Fig.5C];

[0043] [Fig.6A] ;

[0044] [Fig.6B] ;

[0045] [Fig.6C] ;

[0046] [Fig.7A] ;

[0047] [Fig.7B] ;

[0048] [Fig.7C] ;

[0049] [Fig.8A] ;

[0050] [Fig.8B];

[0051] [Fig.8C] ;

[0052] [Fig.9A] ;

[0053] [Fig.9B];

[0054] [Fig.lOA] ;

[0055] [Fig.lOB] ;

[0056] [Fig. 11 A];

[0057] [Fig.llB] ;

[0058] [Fig. 1 IC] illustrate methods of implementation and realization of the invention.

[0059] Figures 3A to 3C, 4A to 4C, 5A to 5C, 6A to 6C, and 7A to 7C illustrate steps 300, 400, 500, 600, 700 of an integrated circuit manufacturing process, in particular of the formation of vertical gates TRG and active regions ACT of transistors in a semiconductor substrate SUB, in a first case where the vertical gates VG have a first depth less than the depth of shallow isolation regions STI.

[0060] In a common orthogonal XYZ frame, the X direction is called the first direction, the Y direction is called the second direction, and the Z direction is called the vertical direction.

[0061] The face of the semiconductor substrate SUB on which the manufacturing steps are carried out is called the front face FA, and is located in an XY plane, perpendicular to the vertical direction Z.

[0062] Fig. 3A illustrates step 300 in a top view of the substrate SUB, in the XY plane of the front face FA.

[0063] Fig. 3B illustrates step 300 in a cross-sectional view in a YZ plane positioned at a location containing the future ACT active regions (Fig. 6B).

[0064] Fig. 3C illustrates step 300 in a cross-sectional view, in the XZ plane, of the SUB semiconductor substrate.

[0065] Step 300 is part of a formation, in the SUB semiconductor substrate, of TRG gate trenches extending in the first direction X.

[0066] The formation of the grid trenches TRG thus includes in step 300 an engraving of first trenches TRI which penetrate vertically Z into the substrate SUB from the front face FA and extend longitudinally in the first direction X.

[0067] Laterally, in the second direction Y, the width wtl of the first TRI trenches at the level of the front face FA is greater than the width wbl of the first TRI trenches at the bottom BTL

[0068] Indeed, the engraving creates FL1 flanks of the first TRI trenches with an inclination oriented in the direction forming an opening from the bottom BT1 outwards. The inclination can be a few degrees, for example less than 10 degrees, typically between 1 and 6 degrees, with respect to the vertical Z, symmetrically on each flank FLL

[0069] The 300 etching technique for the first TRI trenches can, for example, be of the ion bombardment type, usually called "dry etching," such as reactive ion etching (usually "RIE" for "Reactive Ion Etching"). The 300 etching process may include, in particular, a photosensitive resin mask (not shown) to develop the etched pattern, as well as a hard mask (not shown), typically comprising a superposition of dielectric layers such as silicon oxide and silicon nitride.

[0070] Fig. 4A illustrates step 400 in the XY plane of Fig. 3A.

[0071] Fig. 4B illustrates step 400 in the YZ plane of Fig. 3B.

[0072] Fig. 4C illustrates step 400 in the XZ plane of Fig. 3C.

[0073] Step 400 concludes the formation, in the SUB semiconductor substrate, of the TRG grid trenches extending in the first X direction.

[0074] The formation of the TRG grid trenches may further include in step 400 the formation of a dielectric layer OX1, of the grid dielectric type, usually silicon dioxide, on the bottom BT1 and the sides FL1 of the first TRI trenches, and a filling of the first trenches with a grid conductor material PI, such typically as polycrystalline silicon.

[0075] The filling with the conductive material PI includes, for example, a deposit that excessively fills the trenches up to the top of the front face FA. The deposition technique may, for example, be of the chemical or physical vapor phase deposition type. (usually "CVD" or "PVD" for "Chemical Vapor Deposition" or "Physical Vapor Deposition" in English).

[0076] A chemical-mechanical polishing (usually "CMP" for "Chemical-Mechanical Planarization" in English) then allows the excess material to be removed, using for example a layer of the hard mask as a stop layer.

[0077] Fig. 5A illustrates step 500 in the XY plane of figures 3A and 4A.

[0078] Fig. 5B illustrates step 500 in the YZ plane of figures 3B and 4B.

[0079] Fig. 5C illustrates step 500 in the XZ plane of figures 3C and 4C.

[0080] Step 500 is part of a formation, in the SUB semiconductor substrate, of shallow isolation trenches STI extending in the second Y direction, after the formation of grid trenches TRG.

[0081] Shallow insulation trenches STI make it possible in particular to delimit between them active regions ACT of the semiconductor substrate SUB.

[0082] The formation of the shallow isolation trenches STI thus includes in step 500 an engraving of second trenches TR2 which penetrate vertically Z into the substrate SUB from the front face FA and extend longitudinally in the second direction Y.

[0083] Thus, the second TR2 trenches are also etched through the TRG grid trenches formed in steps 300 and 400 described above. The etching dynamics in the TRG grid trench structures are substantially the same as in the SUB substrate.

[0084] Laterally, in the first direction X, the width wt2 of the second trenches TR2 at the level of the front face FA is greater than the width wb2 of the second trenches TR2 at the level of the bottom BT1.

[0085] Indeed, the engraving creates flanks FL2 of the second trenches TR2 with an inclination oriented in the direction forming an opening from the bottom BT2 outwards. The inclination can be a few degrees, for example from 1 to 10 degrees, with respect to the vertical Z, symmetrically on each flank FL2.

[0086] The 500 engraving technique of the second TR2 trenches can, for example, be substantially of the same type, typically "RIE", as the 300 engraving of the first TRI trenches, and using in particular a second hard mask (not shown).

[0087] Fig. 6A illustrates step 600 in the XY plane of figures 3A, 4A, and 5A.

[0088] Fig. 6B illustrates step 600 in the YZ plane of figures 3B, 4B and 5B.

[0089] Fig. 6C illustrates step 600 in the XZ plane of figures 3C, 4C and 5C.

[0090] Step 600 concludes the formation, in the SUB semiconductor substrate, of the shallow STI isolation trenches extending in the second Y direction.

[0091] The formation of shallow insulation trenches STI includes in step 600 a filling of the second trenches TR2 with a dielectric material 0X2, typically silicon dioxide.

[0092] The filling with the dielectric material OX2 includes, for example, thermal oxidation of the sides FL2 and the bottom BT2 of the second trenches TR2, followed by overfilling of the trenches TR2, up to above the front face FA. The deposition technique may, for example, be of the chemical vapor deposition (CVD) or physical vapor deposition (PVD) type.

[0093] A chemical-mechanical polishing “CMP” then allows the excess dielectric material to be removed, using for example a layer of the hard mask used for the second etching (not shown) as a stop layer.

[0094] In summary, in relation to Figures 3A to 3C, 4A to 4C, 5A to 5C, and 6A to 6D, a grid trench formation TRG extending in the first X direction of the front face FA in steps 300, 400, and subsequently in steps 500, 600, a shallow isolation trench formation STI extending in the second Y direction of the front face FA, perpendicular to the first X direction, has been described.

[0095] Thus, because the formation of the shallow insulation trenches STI is done after the formation of the grid trenches TRG, the shallow insulation trenches STI delimit the active regions ACT of the semiconductor substrate SUB from each other, and also delimit the grid trenches TRG from each other in the first direction X.

[0096] In other words, vertical grids VG are thus individualized along the first direction X, from the continuous grid trenches TRG in the first direction X, in a manner said to be "self-aligned" with the delimitation of the active regions ACT.

[0097] It will be noted in particular that it results from this self-alignment that the width wtX, wbX of the vertical grids VG in the first direction X is strictly equal to the width waX of the active regions ACT in the first direction X, at any identical depth Z between the front face FA and the bottom (BT1) of the vertical grid VG.

[0098] On the other hand, because the sides FL2 of the second trenches TR2 have an inclination forming an opening from the bottom BT2 outwards, that is to say because the width wt2 of the second trenches TR2 at the front face FA is greater than the width wb2 of the second trenches TR2 at the bottom BT1; then the sides of the portions delimited between two shallow isolation trenches STI (that is to say the sides of the vertical grids VG and the active regions ACT) have the opposite inclination, closing in a bottleneck from bottom BT2 outwards.

[0099] Thus, in other words, the width wbX in the first direction X of the vertical grids VG at the bottom BT1 of the first trench TRI is greater than the width wtX in the first direction X of the vertical grids VG at the front face FA.

[0100] However, the sides of the vertical grids VG, located on either side of the vertical grids in the second direction Y, have an oriented inclination such that the width wtY of the vertical grids VG in the second direction Y at the level of a front face FA of the substrate is greater than the width wbY of the vertical grids in the second direction Y at the level of the bottom BT1 of the first trench TRI.

[0101] Fig. 7A illustrates step 700 in the XY plane of figures 3A, 4A, 5A and 6A.

[0102] Fig. 7B illustrates step 700 in the YZ plane of figures 3B, 4B, 5B and 6B.

[0103] Fig. 7C illustrates step 700 in the XZ plane of figures 3C, 4C, 5C and 6C.

[0104] Step 700 roughly corresponds to a finalization of the part semiconductor of the integrated circuit (usually called "FEOL" for "Front End Of Line" in English), especially up to the beginning of the formation phase of the interconnect part (usually called "BEOL" for "Back End Of Line" in English).

[0105] In step 700, conduction regions SD of vertical-gate transistors were formed, typically N-type (or P-type) doped regions within the P-type (or N-type) ACT active regions located on either side of the respective vertical gates VG (in the second Y direction). In practice, the P-type (or N-type) ACT active regions are located between adjacent vertical gates, since adjacent transistors typically have common drains and sources.

[0106] A channel region is thus able to form from one conduction region SD to the other, in the active region ACT located along one flank, the bottom and the other flank of the vertical grid VG.

[0107] In addition, step 700 advantageously includes a CNT metallic contact formation connecting the vertical grids VG aligned in the first direction X to a metallic track Ml of a first metal level.

[0108] This makes it possible in particular not to break the electrical continuity which classically exists via the non-individualized TRG grid trench, and thus to be able to adapt this manufacturing process to existing and characterized electrical circuits, without requiring (re)design of the complete circuit.

[0109] The transistors thus formed are for example suitable for implementing logic circuit functionalities, such as state machines.

[0110] In this regard, reference is made to figures 8A, 8B and 8C illustrating an example of application in a logic circuit of the complementary type “CMOS” (classic and well-known abbreviation for “Complementary Metal Oxide Semiconductor” in English).

[0111] Fig. 8A illustrates a cross-section in an XY plane of the CMOS logic circuit, comprising P-type “PMOS” logic transistors.

[0112] Fig. 8B illustrates a cross-section in an XY plane of the CMOS logic circuit, comprising N-type “NMOS” logic transistors.

[0113] Fig. 8C illustrates a cross-section in an XZ plane of the CMOS logic circuit, comprising P-type “PMOS” and N-type “NMOS” logic transistors.

[0114] PMOS transistors correspond for example to the vertical gate transistors described previously in relation to step 700, in the case where an N-type doped NW box has been implanted in the part corresponding to the active region ACT of these transistors.

[0115] The implantation of the NW box may, for example, have been carried out in the SUB semiconductor substrate, prior to the first TRI etchings of step 300.

[0116] The SD conduction regions of PMOS transistors are typically heavily P-type doped.

[0117] NMOS transistors correspond for example to the vertical gate transistors described previously in relation to step 700, in the case where a P-type doped PW box has been implanted in the part corresponding to the active region ACT of these transistors.

[0118] The implantation of the PW box may, for example, have been carried out in the SUB semiconductor substrate, prior to the first TRI etchings of step 300. In practice, the SUB semiconductor substrate may originally be P-type doped, in which case the implantation of the PW as such is not carried out.

[0119] The SD conduction regions of NMOS transistors are typically heavily N-type doped.

[0120] In the first direction X in the XZ plane, a succession of PW type P boxes and NW type N boxes will be noted alternately, respectively under each vertical grid.

[0121] Reference is now made to Figures 9A-9B, 10A-10B and 11A-1 IC, which illustrate steps 1400, 1600, 1700 of the formation of second vertical TRTA gates and active ACT regions of transistors, in a second case where the vertical VG gates have a second depth greater than the depth of shallow isolation regions STI.

[0122] The second vertical gates are particularly suited to selection transistors, typically coupled in series with floating-gate state transistors, in memory cells of a non-volatile memory, in particular a memory of the type Source side injection cells (usually "SSI" for "Source Side Injection" in English).

[0123] Fig. 9A illustrates step 1400 in the YZ plane of the same orthogonal XYZ frame.

[0124] Fig. 9B illustrates step 1400 in the XZ plane of the same orthogonal XYZ coordinate system.

[0125] Step 1400 corresponds substantially to the implementation of steps 300 and 400 described above, in which TRTA grid trenches were engraved vertically in the SUB substrate, deeper than the first TRI trench of step 300, down to a NISO source region previously implanted deep in the SUB substrate.

[0126] Thus, in particular, the TRTA grid trenches extend lengthwise in the first direction X, comprise a volume of grid conductive material PI wrapped by a dielectric layer OX1.

[0127] [Fig.1OA] illustrates step 1600 in the same YZ plane as [Fig.9A].

[0128] Fig. 1OB illustrates step 1600 in the same XZ plane as Fig. 9B.

[0129] Step 1600 corresponds substantially to the implementation of steps 500 and 600 described previously, in which shallow STI insulation trenches were formed at a shallower depth than the TRTA grid trenches. For example, step 1600 can correspond exactly to the implementation of steps 500 and 600 described previously, particularly with shallow STI insulation trenches having the same depth.

[0130] The [Fig. 11 A] illustrates step 1700 in the same YZ plane as figures 9A and 10A.

[0131] Fig. 11B illustrates step 1700 in the same XZ plane as Figures 9B and 10B.

[0132] [Fig. 1 IC] illustrates step 1700 in an XY plane of a top view of the face before FA.

[0133] Step 1700 corresponds to a floating gate state transistor (FGTE) formation, forming memory cells with the selection transistors obtained by the formation of TRTA gate trenches, the buried source region NISO and a conduction region (not shown) common to the selection transistor and the FGTE state transistor.

[0134] Thus, as previously described in relation to Figures 3A to 3C, 4A to 4C, 5A to 5C, and 6A to 6C, the shallow insulation trenches STI delimit the active regions ACT from each other, and also delimit the grid trenches TRG from each other in the first X direction in a self-aligned manner.

[0135] However, in this second case, the TRTA vertical grid trenches are not individualized in the first X direction, since the shallow STI insulation trenches do not reach the bottom.

[0136] Thus, electrical continuity along the TRTA vertical grids, in the first X direction, is maintained in a manner compatible with conventional circuits and characterizations of non-volatile memories.

[0137] It will be noted in particular that it results from self-alignment that the width wtX, wbX of the vertical grids VG in the first direction X is strictly equal to the width waX of the active regions ACT in the first direction X, at any identical depth Z between the front face FA and the bottom (BT2) of the shallow isolation trenches STI.

[0138] On the other hand, we also find the structure in which the width in the first X direction of the TRTA grid trenches is greater in depth than the width in the first X direction of the TRTA grid trenches at the front face FA ([Fig.1 IB]); while the width of the TRTA grid trenches in the second Y direction is greater at a front face FA of the substrate than in depth ([Fig.1 1 A]).

[0139] Finally, the "self-aligned" delimitation of the TRTA grid trench by the shallow STI isolation trenches also makes it possible to solve a static pressure loss problem in the floating grid (usually called "disturb" in English), classically caused by capacitive coupling between the floating grid and the TRTA grid trench in a ZDST zone located outside the alignment of the active ACT regions.

[0140] Indeed, given the subsequent formation of the shallow STI isolation trenches, in the ZDST zone the portions of the floating grid that extend over the shallow STI isolation trenches (called "wings") do not extend over the TRTA poly-silicon portion. Consequently, parasitic couplings between the TRTA grid trench and the "wings" of the floating grid are effectively minimized.

Claims

Demands

1. A method for manufacturing an integrated circuit, comprising a vertical gate (VG) formation of transistors, comprising, in a semiconductor substrate (SUB) having a front face (FA), a gate trench formation (TRG, TRT A) extending in a first direction (X) from the front face, and, subsequently, a shallow insulation trench (STI) formation extending in a second direction (Y) from the front face perpendicular to the first direction, delimiting between them active regions (ACT) and the vertical gates (VG).

2. A method according to claim 1, wherein the formation of the grid trenches (TRG, TRT A) comprises an engraving of first trenches (TRI) penetrating vertically (Z) into the substrate from the front face (FA) and extending longitudinally in the first direction (X), the sides (FL1) of the first trenches (TRI) having an oriented inclination such that the width of the first trenches, in the second direction (Y), is greater at the front face (wtl) than at the bottom of the first trenches (wbl).

3. A method according to any one of claims 1 or 2, wherein the formation of shallow isolation trenches (STI) comprises an engraving of second trenches (TR2) extending vertically (Z) into the substrate from the front face (FA) and extending longitudinally in the second direction (Y), the sides (FL2) of the second trenches (TR2) having an oriented inclination such that the width of the active regions (ACT) and the vertical grids (VG) delimited between them, in the first direction (X), is greater at the bottom of the first trenches (wbX) than at the front face (wtX).

4. A method according to any one of claims 1 to 3, further comprising a metallic contact formation (CNT) connecting the vertical grids (VG) aligned in the first direction (X) to a metallic track (Ml) in at least a first metal level.

5. A method according to any one of claims 1 to 4, wherein the formation of grid trenches (TRG, TRTA) comprises at least one of: - a formation of first grid trenches (TRG) having a first depth (BT1) less than the depth (BT2) of the shallow isolation regions (STI), - a formation of second grid trenches (TRTA) having a second depth (BT1) greater than the depth (BT2) of the shallow isolation regions (STI).

6. A method according to any one of claims 1 to 5, comprising prior to the semiconductor substrate (SUB) a formation of a succession of P-type (PW) and N-type (NW) cells alternating in the first direction (X), positioned opposite the locations of the future active regions (ACT).

7. Integrated circuit, comprising vertical gate transistors in a semiconductor substrate (SUB) having a front face (FA), the vertical gates (VG) being laterally delimited by shallow isolation trenches (STI) located on either side of the vertical gates (VG) in a first direction (X) of the plane of the front face (FA), and by active regions (STI) of the semiconductor substrate located on either side of the vertical gates (VG) in a second direction (Y) of the plane of the front face perpendicular to the first direction (X); the width (wtX) of the vertical gates in the first direction being strictly equal to the width of the active regions (waX) in the first direction.

8. Integrated circuit according to claim 7, wherein the sides of the vertical grids, located on either side of the vertical grids (VG) in the first direction (X), have an oriented inclination such that the width of the vertical grids in the first direction is greater at the bottom of the vertical grids (wbX) than at the front face (wtX).

9. Integrated circuit according to any one of claims 7 or 8, wherein the flanks of the vertical grids, located on either side of the vertical grids (VG) in the second direction (Y), have an oriented inclination such that the width of the vertical grids in the second direction is greater at the front face (wtY) than at the bottom of the vertical grids (wbY).

10. Integrated circuit according to any one of claims 7 to 9 further comprising metallic contacts (CNT) connecting vertical grids (VG) aligned in the first direction (X) to a metallic track (Ml) located in at least a first metal level.

11. Integrated circuit according to any one of claims 7 to 10, wherein the vertical gate transistors comprise at least one of: - a group of transistors comprising first vertical gates (TRG) having a first depth (BT1) less than the depth (BT2) of the shallow isolation regions (STI), - a group of transistors comprising second vertical gates (TRTA) having a second depth (BT1) greater than the depth (BT2) of the shallow isolation regions (STI).

12. Integrated circuit according to any one of claims 7 to 11, wherein active regions (ACT) comprise a succession of P-type (PW) and N-type (NW) boxes alternating in the first direction (X).

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