Integrated circuit package

Abstract

Integrated Circuit Package This description relates to a method for manufacturing an electronic device (1000) comprising the following steps: a) providing an assembly comprising a chip (100) mounted on an interconnect substrate (200), b) depositing a heat dissipation layer (500) of a thermal interface material onto the chip (100), c) attaching a cover (300) to the substrate (200), the cover (300) covering the chip (100), the heat dissipation layer (500) being in contact with the cover (300), the method further comprising a step d) in which an element (400) of an adhesive material or a solderable material is formed on the chip (100), before step b), or on the cover (300), before step c), such that, during step c), the element (400) is in contact with the cover (300) and with the chip (100) and positioned next to the layer of heat dissipation (400). Figure for the abbreviation: Fig. 7

Description

Title of the invention: Integrated circuit package technical field

[0001] This description relates generally to electronic components and, more particularly, to integrated circuit packages, for example ball matrix (or BGA for "Bail Grid Array") packages and the mounting of electronic chips in these packages. Previous technique

[0002] BGA type packages allow an electronic chip to be electrically integrated into an external element such as, for example, a printed circuit board (or PCB for "Printed Circuit Board").

[0003] With the miniaturization of electronic components, managing heat dissipation is becoming increasingly critical. To improve the thermal performance of electronic components, packages include a thermally conductive hood (or cover) positioned over the chip and attached to the substrate. The hood helps dissipate the heat produced by the chip.

[0004] The presence of a thermal interface material (TIM) positioned on the chip and in contact with the cover can facilitate heat dissipation. Summary of the invention

[0005] There is a need for improvement of packages for electronic chips, and in particular a need to improve the heat dissipation of these packages.

[0006] This goal is achieved by a method for manufacturing an electronic device comprising the following steps: a) provide an assembly comprising a chip and an interconnect substrate, the chip having a first face and a second face, the first face of the chip being assembled onto the interconnect substrate by contact pads, b) deposit a heat dissipation layer made of a thermal interface material on the second side of the chip, c) attach a cover to the substrate, the cover over the chip, with the heat dissipation layer in contact with the cover. the process further comprising a step d) in which an element of an adhesive material or of a solderable material is formed either on the chip, before step b), or on the hood, before step c), so that, during step c), the element is in contact with the hood and with the chip and is positioned next to the heat dissipation layer.

[0007] According to a particular embodiment, the element is made of a B-stage polymer material.

[0008] According to a particular embodiment, in step d), the B-stage polymer material is deposited and then pre-polymerized, and, in step c) or after step c), the B-stage material is polymerized.

[0009] According to a particular embodiment, the element is made of a thermal interface material, identical or different from the thermal interface material of the heat dissipation layer.

[0010] According to a particular embodiment, the element is made of a brazeable material, the element being ultrasonically welded to one of the cover or the second face of the chip during step d) and to the other of the cover or the second face of the chip during step c) or after step c).

[0011] This goal is also achieved by an electronic device comprising an electronic chip disposed between an interconnect substrate and a hood, a first face of the electronic chip comprising contact pads fixed to the interconnect substrate, a thermal dissipation layer and an element of an adhesive material or of a solderable material being positioned on a second face of the chip and in contact with the hood.

[0012] According to a particular embodiment, the element is made of a B-stage polymer material, preferably chosen from polyepoxides.

[0013] According to a particular embodiment, the element is made of a thermal interface material, identical or different from the thermal interface material of the heat dissipation layer.

[0014] According to a particular embodiment, the element forms bands or studs, positioned around the thermal dissipation layer.

[0015] According to a particular embodiment, the hood is a metal hood, preferably made of copper. Brief description of the drawings

[0016] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0017] Fig. 1, Fig. 2, Fig. 3 and Fig. 4 represent schematically different stages of a manufacturing process for an integrated circuit package, according to a particular embodiment;

[0018] [Fig.5] schematically represents a variant of a step in a manufacturing process for an integrated circuit package, according to another particular embodiment;

[0019] Figures 6A, 6B, 6C and 6D schematically represent, in top view, a chip on a substrate, locally covered by an adhesive element or by a solderable element, according to another particular embodiment; and

[0020] Fig. 7 represents, schematically and in cross-section, an integrated circuit package according to a particular embodiment.

[0021] In the various figures, the different elements and components are not necessarily represented at the same scale relative to each other. Description of embodiments

[0022] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0023] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0024] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0025] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0026] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0027] By between X and Y, we mean that the bounds X and Y are included, which is equivalent to at least X and up to Y.

[0028] By B-stage polymer material, we mean a multi-stage polymer material. The final polymer material is formed sequentially by a multi-stage polymerization process. A first polymerization stage leads to a pre-polymerized (i.e., partially polymerized) material. The pre-polymerized material exhibits a first degree of polymerization. It is at stage A of polymerization. This first stage allows the material to 'set' while retaining some adhesiveness. A second and final polymerization stage This leads to the production of a polymerized material, preferably fully polymerized (stage B of polymerization). The degree of polymerization in stage B is greater than the first degree of polymerization in stage A. The polymerized material is rigid and adheres to the elements with which it is in contact.

[0029] We will now describe the manufacturing process of a package for integrated circuits with reference to Figures 1 to 4.

[0030] The process comprises the following steps: a) provide an assembly comprising a chip 100 having a first face 101 and a second face 102, the first face 101 of the chip 100 being assembled to a substrate 200 via connection pads 110 ([Fig. 1]), b) deposit a thermal dissipation layer 500 of a thermal interface material on the second face 102 of the chip 100 ([Fig. 3]), c) fix a hood 300 to the substrate 200, the hood 300 covering the chip 100, the thermal dissipation layer 500 being in contact with the hood 300, the hood 300 and the interconnect substrate 200 forming the chip housing ([Fig. 4]).

[0031] The method further comprises, prior to step c), a step d) in which an element 400 made of an adhesive or solderable material is formed on the cover 300 or the second face 102 of the chip 100 ([Fig. 2]). The positioning of the element is chosen so that, during step c), the element 400 is positioned next to the dissipation layer 500 and they do not overlap. The dissipation layer 500 is positioned on a first part of the second face 102 of the chip 100. The element 400 is positioned on a second part of the second face 102 of the chip 100. The first part corresponds, preferably, to the central area of ​​the second face 102 and the second part corresponds, preferably, to the peripheral area of ​​the second face 102. The element 400 and the dissipation layer 500 can be arranged adjacently or separated by a space.

[0032] According to a first embodiment, the element 400 is formed on the second face 102 of the chip 100. Preferably, this step is carried out between step a) and step b). The element 400 allows the dissipation layer 500 to be contained, partially or totally, during its formation (step b)).

[0033] According to a second embodiment, the element 400 is formed on the hood 300 so that, during step c), the element 400 covers a second part of the second face 102 of the chip 100.

[0034] The implementation of step d) allows the element 400 to be positioned, which acts as a wedge between the hood 300 and the chip 100, and allows the hood 300 to be correctly positioned at the desired height relative to the chip 100.

[0035] Furthermore, with such a process, the uniformity (thickness and surface area covered) of the dissipation layer 500 is controlled. The electronic device 1000 obtained It offers very good heat dissipation. The bond line thickness (BLT) is easily controlled by adjusting the thickness of the 400 element.

[0036] Furthermore, excellent adhesion is achieved between the dissipation layer 500 and the cover 300. The device has improved mechanical strength, thus preventing delamination problems. The lifespan and performance of the component are enhanced.

[0037] We will now describe in more detail the different stages of this process and the different elements used to obtain the electronic device 1000.

[0038] The assembly provided in step a) includes a chip 100 assembled on an interconnect substrate 300 by means of contact pads 110.

[0039] The chip 100 comprises a first main face 101 (lower face) and a second main face 102 (upper face).

[0040] The first main face 101 is arranged opposite the interconnecting substrate 200.

[0041] The chip 100 may comprise a substrate, in and / or on which integrated circuits and / or discrete electronic elements, such as transistors, are formed, and an interconnect stack formed by a stack of insulating and conductive layers located on the side of the first face 101 of the chip 100. For example, the substrate is a semiconductor substrate, in particular silicon. These different elements / parts are not shown in the figures for clarity.

[0042] The chip 100 is a so-called flip-chip, that is to say that the active part of the chip 100 is arranged opposite the interconnection substrate 200.

[0043] The contact pads 110 are arranged on the lower face 101 of the chip 100, on the side of the interconnect stack.

[0044] The connection between the chip 100 and the interconnect substrate 200 is made via the contact pads 110 of the chip. The chip 100 may include several contact pads 110. The chip 100 may include at least ten contact pads 110, for example, at least one hundred contact pads 110. By way of example, the contact pads 110 are regularly distributed on the lower face 101 of the chip 100. They may be arranged in a matrix array.

[0045] The contact pads 110 are made of an electrically conductive material. For example, the contact pads 110 are made of a brazable material. The contact pads 110 are, for example, made of copper, silver or tin, or of an alloy, for example based on tin and silver (SnAg).

[0046] An electrically insulating polymer layer 120 ('underfill') is positioned under the chip 100, between the interconnect substrate 200 and the chip 100. The polymer layer 120 encapsulates the connection pads 110 of the chip. This layer 120 allows to protect the mechanical integrity of the pads 110 and protect them from oxidation. This coating layer 120 is, for example, an epoxy layer. It is injected after the chip 100 has been transferred to the substrate 200 by capillary action.

[0047] The interconnecting substrate 200 allows the chip 100 to be assembled to an external device using a technique known as surface mounting.

[0048] The substrate 200 may have, in top view, a substantially square or rectangular shape. For example, the substrate 200 is, in top view, larger than the chip 100. The substrate 200 may have dimensions in top view greater than 10 mm by 10 mm and less than 110 mm by 110 mm, for example, on the order of 25 mm by 25 mm.

[0049] The substrate 200 comprises, for example, a stack of different insulating layers 210 and different metallic layers 220 to form interconnections between the two main faces of the substrate 200. The substrate 200 may comprise, for example, horizontal metallic tracks in the orientation of [Fig.1] and / or vertical metallic vias in the orientation of [Fig.1].

[0050] In the various figures and in the different embodiments, only one chip 100 is shown between the substrate 200 and the hood 300. However, it is possible to have several chips between the substrate 200 and the hood 300.

[0051] Additional passive electronic devices not shown, such as, for example, resistors, inductors and capacitors, may be mounted on the substrate 200 around the chip 100.

[0052] During step b), a dissipation layer 500 of thermal interface material (or TIM for 'thermal interface material') is deposited on a first part of the second face 102 of the chip 100. Preferably, this is the central part of the second face 102 of the chip 100.

[0053] Layer 500, for example, has a thermal conductivity greater than that of air. Layer 500 is, for example, a layer of paste, grease, or thermal adhesive.

[0054] The TIM material is, for example, a composite comprising a polymer, such as a polysiloxane (or silicone), and thermally conductive fillers. The fillers are, for example, silver particles.

[0055] A TIM material is, for example, marketed by the company Wacker.

[0056] The material can also be deposited in the form of coils, in the form of an 'X' or in any other suitable form. When the cover 300 is positioned, the deposited material will spread out as a layer. The greater the contact area between the chip 100 and the TIM material, and between the cover 300 and the TIM material, the better the heat dissipation will be.

[0057] The thermal dissipation layer 500 allows the heat produced by the chip 100 during its operation to be dissipated towards the metal cover 300 and therefore towards the outside of the device 1000.

[0058] The method includes a step d) in which an element 400 made of an adhesive or brazable material is positioned either on the hood 300 or on the chip 100.

[0059] According to a first embodiment, the element 400 is positioned on the chip 100, and more particularly, on the second face 102 of the chip 100.

[0060] According to this first variant, step d) is preferably carried out before step b). The element 400 can act as a barrier during the formation of the dissipation layer 500 and prevent the TIM material from flowing / flushing out of the second face 102 of the chip 100.

[0061] According to a second embodiment, the element 400 is positioned on the cover 300. It is positioned so that, once the cover 300 is assembled onto the chip 100, it is positioned on a second part of the second face 102 of the chip. In other words, it will be positioned adjacent to the dissipation layer 500.

[0062] According to this second variant, step d) can be carried out before or after step b).

[0063] According to a particular embodiment, the element 400 is made of a brazeable material, particularly in metal or a metal alloy. It is preferably made of gold or copper. It will be soldered, for example, onto the cover 300 and / or onto the chip 100, preferably by ultrasonic soldering. An adhesion layer (not shown) may be pre-deposited on the cover 300 and / or on the second side 102 of the chip 100 to make the surface of the cover 300 and / or the chip 100 compatible with soldering and / or to improve the mechanical adhesion of the element to the cover 300 and / or the chip 100. The adhesion layer is, for example, a layer of gold.

[0064] According to another particular embodiment, element 400 is an adhesive material. It is a polymer or a composite comprising at least one polymer in which fillers can be dispersed.

[0065] The adhesive material is, for example, a B-stage polymer. The B-stage polymer is preferably an epoxy (also called a polyepoxide) or a (meth)acrylate. Once applied to the cover 300 or the chip 100, a first heat treatment and / or UV treatment step (optionally followed by annealing) pre-polymerizes the material. It thus acquires a certain rigidity and adhesion. It is therefore not only bonded to the cover 300 or the chip 100 but also rigid, and can serve as a spacer between the cover 300 and the chip 100. Once the cover 300 is positioned on the substrate 100, a second polymerization step by means of heat treatment and / or UV treatment (optionally followed by annealing) completes the polymerization of the B-stage material. This step can be carried out simultaneously with step c) or subsequently after step c). The 300 hood adheres thus to chip 100. For example, the first step is a heat treatment at a temperature between 100 and 125°C and the second step is a heat treatment at a temperature of 150°C.

[0066] The B-Stage material is, for example, marketed by the company Loctite, Delo, Henkel or Sumitomo.

[0067] Alternatively, the adhesive material is a TIM material. The TIM material may be the same as, or different from, the TIM material of the dissipation layer 500. Preferably, it is different. Once applied, a heat treatment or UV treatment step polymerizes the material. It thus acquires a certain rigidity and adhesion. It is therefore not only bonded to the cover 300 or the chip 100 but also rigid, and can serve as a shim.

[0068] The adhesive material (B-stage or TIM) can be deposited by jetting or by dispensing.

[0069] The element 400 (adhesive or brazeable) can be deposited in one or more steps. For example, in [Fig. 5], two layers are deposited to form the element 400. The number of layers deposited depends, in particular, on the desired thickness. In the case of a B-stage adhesive element, it is possible to perform UV curing or other treatment between each layer deposition, or after the deposition of the various layers, in order to pre-cure it.

[0070] The element 400 can be continuous or discontinuous. It can form a continuous bead that will surround the TIM layer 500 during step b) or c). Preferably, the element 400 is discontinuous (Figures 6A, 6B, 6C, and 6D) to facilitate the outgassing of the material from the dissipation layer 500. The element 400 can be in the form of studs (Figures 6A and 6D), beads, or strips, for example, linear ([Fig. 6B]) or L-shaped (Figures 6C). The different parts of the element 400 can be positioned on the edges and / or in the corners of the second face 102 of the chip 100.

[0071] In step c), the hood 300 (also called the cover) is attached to the substrate 200. The hood 300 comprises a flat upper portion and side portions. The lower portion of the hood forms a lip for attachment to the substrate 200. Once positioned on the substrate 200, the hood 300 forms a cavity for holding one or more chips 100. The inner face of the hood 300 partially delimits the cavity. The outer face of the hood is oriented outwards.

[0072] The hood 300 allows in particular to dissipate the heat accumulated in the electronic chip 100.

[0073] By way of example, the hood 300 has, in top view, a shape similar to the shape of the substrate 200. It may have a substantially square or rectangular shape. The lateral dimensions of the hood 300 are, for example, substantially identical to the lateral dimensions of the substrate 200. The hood 300 is, for example, attached to the substrate 200 using a layer of glue 310. Preferably, the hood 300 is fixed to the substrate 200 in a localized manner, i.e., the layer of glue 310 does not extend over the entire periphery of the hood 300 and the substrate 200. In particular, the hood 300 and the substrate 200 can be fixed to each other via the layer of glue 310 only at their four corners.

[0074] The hood 300 can be formed by stamping.

[0075] The hood 300 is made of a thermally conductive material. Preferably, the hood 300 is a metal cover. It is, for example, made of copper. A plating, for example, of nickel, can cover the 300 cover.

[0076] During step c), the hood 300 is fixed: - to the substrate 200 thanks to a layer of glue 310 positioned between the edges of the hood 300 and the substrate 200, and - to the chip thanks to the 500 dissipation layer and thanks to the 400 adhesive or solderable element.

[0077] In the case where the material is an adhesive material, step c) is carried out, for example, according to the following substeps: - Position the cover 300 on the assembly formed by the chip 100 and the interconnect substrate 200, - to carry out heat treatment and / or irradiation under ultraviolet radiation to polymerize the adhesive material.

[0078] Heat treatment and / or irradiation under ultraviolet radiation can simultaneously polymerize the glue layer 310 positioned between the hood 300 and the substrate 200.

[0079] In the case where the material is a brazeable material, step c) comprises the following substeps: - Position the cover 300 on the assembly formed by the chip 100 and the interconnect substrate 200, - perform a sub-step of welding, preferably ultrasonic welding, to weld the cover 300 to the chip 100, - to carry out a heat treatment and / or irradiation under ultraviolet radiation to polymerize the glue layer 310 positioned between the hood 300 and the substrate 200.

[0080] The order of these last two sub-steps can be reversed.

[0081] Once step c) is completed, an electronic component 1000 is obtained which can be assembled to an external element. Such a component 1000 is, for example, shown in [Fig.7].

[0082] The electronic component 1000 comprises a chip 100 having a first face 101 and a second face 102, the first face 101 of the chip 100 being assembled on a substrate 200 by connection pads 110. A cover 300 made of a thermally conductive material is fixed to the substrate 200, for example by a layer of glue 310, and covers the chip 100. A thermal dissipation layer 500 made of a thermal interface material covers a first part of the second face 102 of the chip 100 and is in contact with the cover 300.

[0083] The hood is, in addition, fixed to a second part of the second face 102 of the chip 100 by means of an element 400 made of adhesive material or of a brazable material.

[0084] The cover 300 and the interconnecting substrate 200 form a housing that protects the chip 100 and allows it to be electrically connected to an external element (not shown in the figures), for example, an external device or a PCB (printed circuit board) type substrate. The substrate 200 can be mounted and electrically connected to the external device, for example, by means of interconnecting pads 210 positioned on the second face of the substrate 200 ([Fig. 7]).

[0085] The interconnecting pads 210 can be spheres, pillars, or columns. The spheres 210 are, for example, regularly distributed on the underside of the substrate 200, for example, according to a matrix array. The lateral dimensions of the spheres 210 and the inter-sphere spacing 210 are, for example, greater than the lateral dimensions of the contact pads 110 of the chip and the inter-pad spacing 110 of the chip 100, respectively. The substrate 200 thus performs a spreading and redistribution function of the contacts of the chip 100 towards the contacts of the external device.

[0086] Such electronic components, also called TEFCBGA components (for 'thermally enhanced flip chip -bail grid array'), are particularly interesting for many applications.

[0087] They allow a large number of I / O operations to be performed, with good performance and good heat dissipation.

[0088] The device is, for example, intended for the automotive industry. In particular, the device can be used in a microcontroller or in an advanced driver assistance system (ADAS for 'Advanced Driver Assistance Systems').

[0089] It can be used in high-performance computing (HPC) devices, for example in central processing units (CPU) or graphics processing units (GPU).

[0090] The device can, for example, be used in the industrial sector. More specifically, the device is intended, for example, to be used for the development of green energy or for the electrification of infrastructure, for example for charging stations or for solar energy.

[0091] The device can also be used in the field of the Internet of Things and smart homes.

[0092] The device can also be used in the implementation of 5G networks, data centers and servers.

[0093] The device is, for example, intended for use in personal electronics, for example, to increase radio frequency content, in 5G connectivity devices, or more generally in connected devices. The device is used, for example, in mobile phones ('smartphones') or for Internet of Things networks. The device is connected, for example, via 5G or Wi-Fi. The device includes, for example, high-speed interfaces, for example, with advanced filtering and protection against electromagnetic discharge.

[0094] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0095] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing an electronic device (1000) comprising the following steps: a) providing an assembly comprising a chip (100) and an interconnect substrate (200), the chip having a first face (101) and a second face (102), the first face (101) of the chip (100) being assembled onto the interconnect substrate (200) by contact pads (110), b) depositing a heat dissipation layer (500) of a thermal interface material onto the second face (102) of the chip (100), c) attaching a cover (300) to the substrate (200), the cover (300) covering the chip (100), the heat dissipation layer (500) being in contact with the cover (300), the method further comprising a step d) in which an element (400) of an adhesive material or a solderable material is formed either on the chip (100), before step b), or on the hood (300), before step c), so that, during step c),the element (400) is in contact with the cover (300) and with the chip (100) and is positioned next to the heat dissipation layer (400).

2. Method according to claim 1, wherein the element (400) is made of a B-stage polymer material.

3. A method according to the preceding claim, wherein, in step d), the B-stage polymer material is deposited and then pre-polymerized, and wherein, in step c) or after step c), the B-stage material is polymerized.

4. Method according to claim 1, wherein the element (400) is made of a thermal interface material, identical or different from the thermal interface material of the heat dissipation layer (500).

5. A method according to claim 1, wherein the element (400) is made of a brazeable material, the element (400) being ultrasonically welded to one of the hood (300) or the second face (102) of the chip (100) during step d) and to the other of the hood (300) or the second face (102) of the chip (100) during step c) or after step c).

6. Electronic device comprising an electronic chip (1000) disposed between an interconnect substrate (200) and a cover (300), a first face (101) of the electronic chip (100) comprising contact pads (110) fixed to the interconnect substrate (200), in which a heat dissipation layer (500) and an element (400) of an adhesive material or of a solderable material are positioned on a second face (102) of the chip and in contact with the cover (300).

7. Device according to claim 6, wherein the element (400) is made of a B-stage polymer material, preferably selected from polyepoxides.

8. Device according to claim 6, wherein the element (400) is made of a thermal interface material, identical or different from the thermal interface material of the heat dissipation layer (500).

9. Device according to any one of claims 6 to 8, wherein the element (400) forms bands or studs, positioned around the heat dissipation layer (500).

10. Device according to any one of claims 6 to 9, wherein the hood (300) is a metallic hood, preferably made of copper.

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