Covalent bonding process by atomic diffusion to form a conductive bonding interface

Abstract

Covalent bonding process by atomic diffusion to form a conductive bonding interface. This description relates to a covalent bonding process by atomic diffusion comprising the following steps: a) providing a first substrate (100) and a second substrate (200) of semiconductor material, coated with a layer of native oxide (110, 210), b) removing the native oxide layers (110, 210) and passivating the substrates (100, 200) by forming hydrogen bonds on the surface, c) joining the first substrate (100) and the second substrate (200) by atomic diffusion bonding by: - ​​introducing the first substrate (100) and the second substrate (200) into a chamber (400), then placing the chamber (400) under ultra-high vacuum, - depositing an amorphous layer (120, 220), under ultra-high vacuum, so as to coat the first substrate (100) and / or the second substrate (200), - bringing the first substrate (100) and second substrate (200), under ultra-high vacuum,d) Preferably, perform thermal annealing to crystallize the amorphous layer (120, 220). Figure for the abstract: Fig. 1C,

Description

Title of the invention: Covalent bonding process by atomic diffusion to form a conductive bonding interface. Technical field

[0001] The present description relates generally to the field of microelectronics and, more particularly, to the field of covalent bonding by atomic diffusion. Previous technique

[0002] Covalent bonding of two semiconductor substrates by atomic diffusion bonding (ADB) differs from other types of bonding used in microelectronics in that it leads to very strong adhesion during bonding but also to very strong adhesion immediately after bonding, without the need to reinforce the bond interface by means of consolidation annealing. This type of bonding can be carried out at low temperatures, typically below 200°C or even at room temperature.

[0003] ADB covalent bonding generally takes place according to the following sub-steps: - placing the substrates under ultra-high vacuum (pressure less than 10⁸ mbar or less than 10⁶ Pa), - making, under ultra-high vacuum, a very thin deposit (typically a few nanometers thick, or even up to 10 nm) of an amorphous or metallic material on the surfaces of the substrates to be bonded, - transfer the substrates into a bonding module while keeping them under ultra-high vacuum in order to preserve the hanging bonds created during the deposition process, - bring the two surfaces to be bonded into contact.

[0004] An amorphous or metallic layer is thus trapped at the bonding interface.

[0005] In the case of the deposition of an amorphous layer of semiconductor material, the layer must have a minimum thickness of several nanometers. In the case of silicon, a 10 nm amorphous layer is deposited on each surface to be bonded (Uomoto et al. 'Room Temperature Bonding of Wafers Using Si and Ge Films with Extremely Low Electrical Conductivity', ECS Transactions 2018, 86 (5) 199-204) to ensure sufficient adhesion. The thickness of the amorphous layer trapped at the bonding interface can therefore reach 20 nm.

[0006] The deposition of this amorphous layer is carried out directly on the native oxide, naturally present on the surface of the substrates. However, in the case of a bond between two semiconductors, such as a Si / Si bond, this strongly limits electrical conduction at the bond interface (Uomoto et al. cited previously), which can be This is problematic for many applications. However, the ADB bonding process does not include a sub-step to remove the native oxide present on the surface of the substrates to be bonded. Summary of the invention

[0007] There is a need to propose a bonding process that allows for having a conductive bonding interface, even for substrates made of semiconductor materials, naturally covered by a layer of native oxide.

[0008] This goal is achieved by a covalent bonding process by atomic diffusion comprising the following steps: a) provide a first substrate of a first semiconductor material and a second substrate of a second semiconductor material, the first substrate and the second substrate each comprising a first surface covered by a layer of native oxide, b) remove the native oxide layers and passivate the initial surfaces by forming hydrogen bonds on the surface, c) assemble the first substrate and the second substrate by atomic diffusion bonding in: - introducing the first substrate and the second substrate into a chamber, then placing the chamber under ultra-high vacuum, - depositing, under ultra-high vacuum, a first amorphous layer on the first surface of the first substrate and, optionally, a second amorphous layer on the first surface of the second substrate, - bringing the first substrate and the second substrate into contact under ultra-high vacuum, thereby assembling the substrates, d) preferably, perform thermal annealing to recrystallize the amorphous layer.

[0009] According to a particular embodiment, during step c), the pressure under ultra-high vacuum is between 2.108 mbar and 5.108 mbar.

[0010] According to a particular embodiment, step b) is carried out chemically, using a succession of different solutions, one of the different solutions being a hydrofluoric acid solution.

[0011] According to a particular embodiment, the process includes, between step b) and step c), a step in which epitaxial layers are formed on the first surface of the first substrate and on the first surface of the second substrate.

[0012] According to a particular embodiment, the process includes, before step c), a step in which the epitaxial layers are subjected to heat treatment under hydrogen.

[0013] According to a particular embodiment, the process includes, between step b) and step c), an additional step in which doped amorphous layers are formed on the first surface of the first substrate and on the first surface of the second substrate.

[0014] According to a particular embodiment, after the formation of the doped amorphous layers, step b) is carried out again, before step c).

[0015] According to a particular embodiment, between step b) and step c), an epitaxial layer is formed on the first surface of the first substrate and a thermal oxide layer is formed on the first surface of the second substrate.

[0016] According to a particular embodiment, the first amorphous layer and, where applicable, the second amorphous layer deposited in step c) are made of amorphous silicon or amorphous germanium.

[0017] According to a particular embodiment, the first substrate and the second substrate are made of single-crystal silicon or single-crystal germanium or single-crystal gallium arsenide or single-crystal indium phosphide. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D] and [Fig.1E] schematically represent different stages of a covalent bonding process by atomic diffusion, according to a particular embodiment of the invention;

[0020] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E and Fig. 2F schematically represent different stages of a covalent bonding process by atomic diffusion, according to another particular embodiment of the invention;

[0021] Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E and Fig. 3F schematically represent different stages of a covalent bonding process by atomic diffusion, according to another particular embodiment of the invention;

[0022] Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, Fig. 4E and Fig. 4F schematically represent different stages of a covalent bonding process by atomic diffusion, according to another particular embodiment of the invention;

[0023] [Fig.5] is an image obtained by atomic force microscopy of the surface of a silicon substrate after epitaxy at 750°C and hydrogen passivation.

[0024] The different elements represented in the figures are not necessarily at a uniform scale for better readability. Description of the implementation methods

[0025] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0027] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0028] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0029] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean at 10%, preferably at 5%.

[0030] By between X and Y, we mean that the bounds X and Y are included.

[0031] By strong adhesion, we mean adhesion greater than IJ / m2, and preferably greater than 4J / m2. Adhesion can be measured, for example, by the double beam cantilever method, introduced by Maszara et al. ('Bonding of Silicon wafers for silicon-on-insulator', J Appl Phys. (1988), 64(10)).

[0032] By conductive interface, it is understood that the vertical resistivity of the interface is less than 1 ohm.cm. This resistivity can be evaluated by determining the I(V) curve of the bonding interface by the method described by Rouchier et al. ('150 mm SiC Engineered Substrates for High-Voltage Power Devices', Materials Science Forum (2022), 1062,131-135)).

[0033] By ultra-high vacuum, we mean a pressure less than 10⁷ mbar.

[0034] We will now describe in more detail the covalent bonding process by atomic diffusion with reference to the attached figures.

[0035] The bonding process comprises the following steps: a) provide a first substrate 100 made of a first semiconductor material and a second substrate 200 made of a second semiconductor material, the first substrate 100 and the second substrate 200 being coated with a layer of native oxide 110, 210 (Figures IA, 2A, 3A, 4A), b) remove the native oxide layers 110, 210 and passivate the first surfaces 101, 201 by forming surface hydrogen bonds on the surface of the substrates 100, 200 (Figures IB, 2B, 3B, 4B), c) assemble the first substrate 100 and the second substrate (200) by atomic diffusion bonding, under vacuum, in: - introducing the first substrate 100 and the second substrate 200 into a chamber 400, then placing the chamber 400 under ultra-high vacuum, - depositing, under ultra-high vacuum, a first amorphous layer 120, so as to cover the first surface 101 of the first substrate 100 and, possibly, a second layer 220 so as to cover the first surface 201 of the second substrate 200 (figures IC, 2D, 3D, 4D), - bringing the first substrate 100 and the second substrate 200 into contact under ultra-high vacuum (figures 1D, 2E, 3E, 4E), d) preferably, carry out a thermal annealing to recrystallize the amorphous layer (120) (figures 1E, 2F, 3F, 4F).

[0036] The substrates 100, 200 are continuously under ultra-high vacuum from the moment the chamber 400 is induced into ultra-high vacuum until the substrates 100, 200 are bonded. Therefore, no new native oxide can develop on the surface of the substrates before the bonding step. This process makes it possible to create a bonding interface free of native oxide, despite the use of semiconductor material substrates 100, 200. The bonding interface is conductive.

[0037] The first substrate 100 and the second substrate 200 provided in step a) are made of semiconductor material. They may be made of the same semiconductor material or of different conductive materials.

[0038] The first substrate 100 and the second substrate may be, for example, silicon or germanium. They could also be gallium arsenide or indium phosphide. Monocrystalline substrates are advantageously chosen.

[0039] Each substrate 100, 200 comprises a first surface 101, 201 and a second surface 102, 202. The first surface 101 of the first substrate 100 and the first surface 201 of the second substrate 200 will be arranged opposite each other during gluing.

[0040] The substrates 100, 200 are preferably in the form of a circular plate.

[0041] The first surface 101 of the first substrate 100 and the first surface 201 of the second substrate 200 are naturally covered by a layer of native oxide 110, 210. Such a layer has no particular function.

[0042] In step b), the native oxide layers 110, 210 are removed and the first surfaces 101, 201 of the substrates 100, 200 are passivated. Passivation consists of forming a monolayer of hydrogen atoms that saturates the dangling bonds of the atoms present on the surface, for example, silicon atoms in the case of a silicon substrate.

[0043] This results in first surfaces 101, 201 covered by surface hydrogen bonds. The nature of the bonds depends on the nature of the substrate. For a silicon substrate, Si-H bonds will be formed. For a germanium substrate, Ge-H bonds will be formed.

[0044] Thus, step b) allows both the elimination of the native oxide (deoxidation) and the leaving of a hydrogenated surface.

[0045] Step b) can be carried out chemically or gaseously. Preferably, it is carried out chemically. For example, hydrogen passivation (so-called 'HF last' passivation) may be used. This passivation consists in particular of cleaning the surfaces of the substrates 100, 200 by a succession of chemical baths. The substrates 100, 200 are, for example, cleaned with a bath of caro acid (a mixture of phosphoric acid H2SO4 and hydrogen peroxide H2O2), an APM treatment bath (a mixture of ammonia, hydrogen peroxide, and water), and a diluted HF bath (for example, a 1% mass concentration). After each bath, a water rinse can be carried out. Each cleaning in a particular bath lasts, for example, approximately 10 minutes.

[0046] Such hydrogen passivation is particularly effective for silicon. Those skilled in the art can adapt the chemical baths according to the nature of the substrate.

[0047] Once step b) has been carried out, the substrates 100, 200 can be introduced directly into the chamber (step c)), as shown in Figures IA to 1D. A native oxide layer does not have time to form between step b) and step c).

[0048] According to one embodiment (for example, shown in Figures 2A to 2F), after step b), the surfaces of the substrates 100, 200 are smoothed by performing an epitaxial step, i.e., by forming a layer of epitaxially grown semiconductor material 130, 230 on each of the first surfaces 101, 201 ([Fig. 2C]). This step reduces the surface roughness of the substrates to less than 0.1 nm RMS. The surface of the epitaxially grown layer 130, 230 is also passivated before introducing the substrates 100, 200 into the chamber 400. According to this embodiment, the passivation step (after the formation of the epitaxially grown layer 130) can be carried out by means of hydrogen annealing. According to this variant, step b), performed beforehand, allows the oxide layer to be removed and the surfaces of substrates 100 and 200 to be prepared for the deposition of a single-crystal epitaxial layer. Indeed, if the surface of the single-crystal substrate is covered with a thin layer of oxide, the atoms deposited during epitaxy will not be able to arrange themselves correctly and a polycrystalline layer will be formed.

[0049] According to another embodiment, for example shown in Figures 3A to 3F, after step b), the process includes a step in which a doped amorphous layer 140, 240 is formed on each of the first surfaces 101, 201 of the substrates 100, 200. The doped amorphous layer 140, 240 can be deposited by low-pressure chemical vapor deposition (LPCVD). Preferably, the deposited doped amorphous layer has a roughness of less than 0.2 nm RMS. After deposition of the doped amorphous layer 140, 240, chemical polishing (CMP) can be carried out to reduce the surface roughness below 0.2 nm RMS. Since it is an amorphous layer, there is no need to go below 0.1nm RMS.

[0050] After deposition of the doped amorphous layer 140, 240, step b) is carried out again to, if necessary, remove a layer of native oxide that could form again and to passivate the surfaces of the substrates 100, 200.

[0051] According to another embodiment, for example shown in Figures 4A to 4F, after step b) and before step c), the process comprises, on the one hand, a step in which a thermal oxide layer is formed on one of the substrates and, on the other hand, a step in which an epitaxial layer is formed on the other substrate. For example, the thermal oxide layer 130 is formed on the first substrate 100 and the epitaxial layer 250 is formed on the second substrate 200. As before, after the epitaxial step, a hydrogen annealing step is carried out to passivate the surface of the substrate.

[0052] A thermal oxide layer differs from a native oxide layer both in its thickness (the native oxide layer is much thinner than the thermal oxide layer) and in its stoichiometry. A thermal oxide layer can serve as an electrical insulation layer within the structure obtained by bonding the substrates. For example, the thermal oxide layer can form the buried oxide layer (BOX) in the case of a SOI substrate.

[0053] The substrates 100, 200 are then introduced into the chamber 400 (step c)). The DAB gluing equipment chamber is a chamber capable of being placed under vacuum

[0054] The bonding equipment chamber 400 may comprise one or more chambers. For example, the deposition of the amorphous layer(s) 120, 220 and the bonding may take place in identical or different chambers. The chamber 400 is configured so that the substrates 100, 200 remain under vacuum from the moment the chamber 400 is evacuated until the substrates 100, 200 are bonded.

[0055] The pressure in the enclosure 400 is between 108 mbar and 107 mbar. It is preferably less than 5108 mbar.

[0056] The different sub-steps of step c) can be carried out under the same ultra-high vacuum, that is to say without breaking the vacuum between these different steps.

[0057] During step c), a first amorphous layer 120 is deposited on the first surface 101 of the first substrate 100 and / or a second amorphous layer 220 is deposited on the first surface 201 of the second substrate 200. The amorphous layers 120, 220 are, for example, made of amorphous silicon or amorphous germanium.

[0058] The thickness of the deposited amorphous layers 120, 220 will depend on the different steps implemented before the introduction of the substrates into the enclosure 400.

[0059] For example, in the case of chemical passivation, the roughness of the substrates is greater than 0.1 nm RMS. This is comparable to the roughness that would be obtained in the case of an ADB bonding process with substrates coated by a native oxide layer. The amorphous layer 120, 220 deposited on each substrate 100, 200 has, for example, a thickness of 10 nm. Strong adhesion is thus obtained after bonding. After bonding, the amorphous portion between the substrates 100, 200 has a thickness of 20 nm.

[0060] It is also possible to deposit an amorphous layer 120 of 20 nm thickness on only one of the two substrates 100, 200.

[0061] In the case where the surfaces of the substrates 100, 200 are smoothed by performing an epitaxial step, the roughness can be less than 0.1 nm RMS. It is possible to deposit a thinner amorphous layer 120 (for example, less than or equal to one nanometer on each face to be bonded) during step c), while ensuring strong adhesion at the end of the bonding process. This very thin deposit makes it possible to generate just the number of dangling bonds necessary for covalent bonding, while minimizing the thickness of the trapped amorphous layer at the bonding interface. Minimizing the thickness of the amorphous zone at the bonding interface, while having previously removed the native oxide from the substrates, makes the bonding interface even more conductive.

[0062] In the case where a doped amorphous layer 140, 240 is formed on the substrates 100, 200 before step c), the amorphous layer 120, 220 is deposited on the doped amorphous layer 140, 240. The amorphous layer 120, 220 can then be very thin (less than one nanometer on each surface to be bonded). Having a doped amorphous layer allows for the deposition of a thin amorphous layer in the ADB while maintaining strong adhesion and good electrical conductivity.

[0063] The substrates 100, 200 are brought into contact with each other to be assembled. This substep can be carried out at a temperature below 200°C, preferably less than 100°C. This sub-step is, for example, carried out at room temperature (in other words between 20 and 25°C).

[0064] Once step c) has been completed, the pressure is increased back to ambient pressure, typically to Ibar (i.e., 105 Pa). Substrates 100, 200 are removed from the chamber.

[0065] At the end of the process, an assembly is obtained exhibiting good vertical conduction due to the removal of the native oxide.

[0066] An annealing step may be carried out (step d)). The annealing is a crystallization annealing to further improve vertical conductivity. During annealing, since the native oxide layer has been removed, the recrystallized amorphous layer is monocrystalline, which improves conductivity. If the native oxide had still been present, the amorphous layer would have crystallized in a polycrystalline form.

[0067] This embodiment is particularly advantageous for a silicon substrate on which an amorphous layer of silicon is deposited or for a germanium substrate on which an amorphous layer of germanium is deposited.

[0068] The annealing temperature is preferably above 400°C, or even above 500°C or 600°C (Sébastien Sollier's thesis, 'Study of the recrystallization of amorphous silicon by direct hydrophobic bonding', 2010). For silicon, a temperature below 1200°C will be chosen, for example, and for germanium, a temperature below 800°C will be chosen, for example.

[0069] The different embodiments can be used in combination with each other. By way of illustration and not limitation, the following combinations are possible for covalent bonding by atomic diffusion: - a substrate having an epitaxial surface to be bonded to a substrate having a surface covered by a deposit of doped amorphous silicon, - a substrate having an epitaxial surface with a substrate having a standard surface, - a substrate having a standard surface with a substrate having a surface covered with a layer of doped amorphous silicon, - a substrate having an epitaxial surface to be bonded with a substrate having a surface covered by a layer of thermal oxide.

[0070] At the end of the process, the substrates have good vertical conductivity. For example, silicon plates or layers doped with more than 19 atoms / cm3 of boron are obtained.

[0071] The process is particularly interesting for many applications, and in particular for obtaining conductive SOI ('Silicon on Insulator') type substrates or for assembling two substrates in semiconductor materials with different crystalline orientations (for example (110) and (100)).

[0072] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0073] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

[0074] Illustrative and non-limiting examples

[0075] In the following examples, the substrates and the amorphous layer deposited in the enclosure during step f), and, where applicable, the doped amorphous layer, are made of silicon. It is clear that the examples could be carried out with a substrate made of another semiconductor material, such as germanium, and / or with amorphous layers (doped or undoped) made of another semiconductor material, such as germanium.

[0076] In the following examples, the substrates are silicon wafers called monitor (or 'wafer monitor'). The wafers have a diameter of 200 mm. Other dimensions could be used.

[0077] Example 1: conductive Si / Si bonding, with an amorphous layer of 20 nm the collage interface

[0078] The silicon wafers undergo chemical passivation using a process known as "HF last," which includes chemical cleaning with Caro's acid (obtained by mixing phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120 °C), rinsing with deionized water, APM treatment (a mixture of ammonia, hydrogen peroxide, and water in a 1-1-5 ratio at 70 °C), deoxidation in a 1% HF bath by mass concentration, and then rinsing with deionized water. Each step lasts approximately 10 minutes, except for the final rinse, which lasts only 1 minute.

[0079] Immediately after chemical passivation, the substrates are introduced into the ADB bonding equipment chamber, operating at a pressure of 2 x 10⁸ mbar, which prevents the formation of a native surface oxide. A 10 nm amorphous silicon deposit is immediately made on the two surfaces to be bonded.

[0080] The two surfaces are then brought into contact to form covalent bonds. The bonding is carried out at room temperature. A 20 nm amorphous layer is thus generated between the substrates. The bond exhibits strong adhesion (greater than 4 J / m²) and the bond interface is conductive. The conductivity can be improved by thermal annealing above 400°C. The interface is electrically conductive. Even though vertical conduction is slightly disrupted by the presence of the 20 nm layer of undoped silicon, the removal of the native oxide is already a significant advantage.

[0081] Example 2: Conductive Si / Si bonding, with a 2 nm amorphous layer at the interface gluing

[0082] In this second example, silicon epitaxy using dichlorosilane (SiH2 Cl2) at 950°C is performed on the silicon wafers. For this, a preparation known as "HF last" is used: chemical cleaning with caro acid (obtained by mixing phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120°C) followed by rinsing with deionized water, an APM treatment (a mixture of ammonia, hydrogen peroxide, and water in a 1-1-5 ratio at 70°C), and deoxidation in a 0.1% HF bath followed by rinsing with deionized water. Each step lasts approximately 10 minutes.

[0083] Next, the substrate is heated to 950°C under 20 mbar of hydrogen for 2 minutes. An epitaxy of approximately 1 µm of silicon is carried out at 950°C under 20 mbar of SiH2Cl2 for approximately 10 s. And finally, a smoothing anneal is performed at 950°C under 20 mbar of H2 for 5 min.

[0084] Atomic terraces observed by AFM show the very low roughness of these surfaces ([Fig. 5]). Such roughness is perfectly compatible with direct bonding.

[0085] After epitaxy, the surfaces are naturally passivated by hydrogen through final hydrogen annealing.

[0086] Immediately after passivation, the surfaces are introduced into the ADB bonding equipment chamber, operating at a pressure of 2 x 10⁸ mbar. A 1 nm amorphous silicon deposit is immediately formed on the surfaces to be bonded. An amorphous layer of only 2 nm will therefore be generated at the bonding interface.

[0087] The two surfaces are then brought into contact to form covalent bonds at room temperature, thus creating a bond with strong adhesion (greater than 4 J / m²), as well as a conductive bonding interface. The conductivity can be improved by thermal annealing at a temperature above 400 °C.

[0088] Example 3: conductive Si / Si bonding, with an amorphous layer of doped Silicon at the bonding interface

[0089] The silicon wafers undergo an "HF last" preparation: chemical cleaning with caro acid (obtained by mixing phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120 °C) followed by rinsing with deionized water, an APM treatment (a mixture of ammonia, hydrogen peroxide, and water in a 1-1-5 ratio at 70 °C), and deoxidation in a 1% HF bath by mass concentration followed by rinsing with deionized water. Each step lasts approximately 10 minutes, except for the final rinse, which lasts only 1 minute.

[0090] Immediately after cleaning, the surfaces are introduced into a heat treatment unit to perform low-pressure chemical vapor deposition (LPCVD) of heavily phosphorus-doped amorphous silicon at 5E20 atm.cm2 and 40 nm thick. To carry out this process, the substrates are introduced into the heat treatment unit at 350°C, and then a temperature ramp is performed until a temperature of 475°C is reached.

[0091] After deposition, a chemical mechanical polishing (CMP) step is performed on the surfaces to obtain a surface roughness of less than 0.2 nm RMS. During this step, a portion of the doped amorphous silicon deposit is removed (approximately 10 nm).

[0092] The surfaces are then prepared again with a "HF last" chemical process, as described above.

[0093] Immediately after passivation, the surfaces are introduced into the ADB bonding equipment chamber, operating at a pressure of 2 x 10⁸ mbar, which prevents the formation of a native surface oxide. A 1 nm amorphous silicon deposit is immediately deposited on the surfaces to be bonded. An amorphous layer of only 2 nm is thus generated at the bonding interface.

[0094] The two surfaces are then brought into contact to form covalent bonds at room temperature, thus creating a bond with strong adhesion (greater than 4 J / m²) and a conductive bonding interface. The conductivity can be improved by thermal annealing above 400 °C.

[0095] Example 4: Si / SiO2 bonding with an electrically and thermally transparent bonding interface

[0096] In this example, the two silicon wafers are prepared differently before being introduced into the bonding chamber by ADB.

[0097] One of the silicon wafers undergoes silicon epitaxy using dichlorosilane (SiH2Cl2) at 950°C. Typically, it is first subjected to an "HF last" preparation: chemical cleaning with caro acid (obtained by mixing phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120°C) followed by rinsing with deionized water, an APM treatment (a mixture of ammonia, hydrogen peroxide, and water in a 1-1-5 ratio at 70°C), and deoxidation in a 0.1% HF bath followed by rinsing with deionized water. Each step lasts approximately 10 minutes.

[0098] After this cleaning and chemical preparation, the substrate is heated to 950°C under 20 mbar of hydrogen for 2 minutes. Epitaxy of approximately 1 µm of silicon is performed at 950°C under 20 mbar of SiH2Cl2 for approximately 10 s. A smoothing anneal is then performed. The process is then carried out at 950°C under 20 mbar of H2 for 5 min. Atomic terraces observed by AFM show the very low roughness of this surface, perfectly compatible with direct bonding. After epitaxy, the surface is naturally passivated by hydrogen through final hydrogen annealing.

[0099] The other silicon wafer undergoes the same chemical preparation known as "HF last" as the first wafer. Then, a thermal oxide layer is applied to the surface of this wafer in a furnace at 750 °C under oxygen. The resulting thermal oxide layer has a thickness of 1 µm.

[0100] Immediately after their respective preparation, the substrates are introduced into the ADB bonding equipment, operating at a pressure of 2 x 10⁸ mbar. A 1 nm amorphous silicon deposit is immediately made on the surfaces to be bonded. An amorphous layer of only 2 nm will therefore be generated at the bonding interface.

[0101] The two surfaces are then brought into contact to form covalent bonds at room temperature, thus creating a bond with strong adhesion (greater than 4 J / m²) and a conductive bonding interface. The conductivity can be improved by thermal annealing above 400 °C.

[0102] Here, the interface is electrically and thermally conductive in the sense that it is transparent to horizontal charge conduction in the silicon beneath the thermal oxide. This is particularly advantageous if the silicon beneath the bonding interface subsequently serves as a channel for a transistor. The charge flow will not be disrupted by the bonding interface. There is no difference between a channel coated with a thermal oxide without a bonding interface and the same channel coated with an oxide applied by direct bonding.

Claims

Demands

1. A covalent bonding process by atomic diffusion comprising the following steps: a) providing a first substrate (100) of a first semiconductor material and a second substrate (200) of a second semiconductor material, the first substrate (100) and the second substrate (200) each comprising a first surface (101, 201) covered by a layer of native oxide (110, 210), b) removing the native oxide layers (110, 210) and passivating the first surfaces (101, 201) by forming surface hydrogen bonds, c) joining the first substrate (100) and the second substrate (200) by atomic diffusion bonding by: - ​​introducing the first substrate (100) and the second substrate (200) into a chamber (400), then placing the chamber (400) under ultra-high vacuum, - depositing, under ultra-high vacuum, a first amorphous layer (120) onto the first surface (101) of the first substrate (100) and, preferably,a second amorphous layer (220) on the first surface (201) of the second substrate (200), bringing the first substrate (100) and the second substrate (200) into contact under ultra-high vacuum, thereby assembling the substrates (100, 200), d) preferably, performing thermal annealing to recrystallize the amorphous layer (120, 220).

2. A method according to claim 1, wherein in step c), the pressure under ultra-high vacuum is between 2.108 mbar and 5.108 mbar.

3. A method according to any one of the preceding claims, wherein step b) is carried out chemically, using a succession of different solutions, one of the different solutions being a hydrofluoric acid solution.

4. A method according to any one of claims 1 to 3, comprising, between step b) and step c), a step in which epitaxial layers (130, 230) are formed on the first surface (101) of the first substrate (100) and on the first surface (201) of the second substrate (200).

5. A method according to claim 4, comprising, before step c), a step in which the epitaxial layers (130, 230) are subjected to heat treatment under hydrogen.

6. A method according to any one of claims 1 to 3, comprising, between step b) and step c), an additional step in which doped amorphous layers (140, 240) are formed on the first surface (101) of the first substrate (100) and on the first surface (201) of the second substrate (200).

7. A method according to the preceding claim, wherein, after the formation of the doped amorphous layers (140, 240), step b) is again carried out, before step c).

8. A method according to any one of claims 1 to 3, wherein, between step b) and step c), an epitaxial layer (130) is formed on the first surface (101) of the first substrate (100) and a thermal oxide layer (250) is formed on the first surface (201) of the second substrate (200).

9. A method according to any one of the preceding claims, wherein the first amorphous layer (120) and, preferably, the second amorphous layer (220) deposited in step c) are made of amorphous silicon or amorphous germanium.

10. A method according to any one of the preceding claims, wherein the first substrate (100) and the second substrate (200) are made of single-crystal silicon or single-crystal germanium or single-crystal gallium arsenide or single-crystal indium phosphide.

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