Transistor, resonator and oscillator system comprising such a system

Abstract

Title: Transistor, Resonator and Oscillator System Comprising Such a System. Transistor electrical system, comprising a first transistor (T1) having control, input and output terminals (cd1, e1, s1) configured to be coupled to a biasing circuit (10), a second transistor (T2) having control, input and output terminals (cd2, e2, s2) configured to be coupled to the biasing circuit (10), an inductive device (2) coupled to the control terminals (cd1, cd2), a first capacitive component (C1) coupled in series between the input terminal (e1) of the first transistor (T1) and the output terminal (s2) of the second transistor (T2); and a second capacitive component (C2) coupled in series between the input terminal (e2) of the second transistor (T2) and the output terminal (s1) of the first transistor (T1). Figure for abstract: Fig. 1

Description

Title of the invention: Transistor, resonator and oscillator system comprising such a system. Technical field

[0001] The present invention relates to transistor systems, particularly suitable for the realization of resonators and oscillators. STATE OF THE ART

[0002] Generally speaking, an electrical system is understood to be a system comprising components, known as integrated components, fabricated on a semiconductor substrate, or components, known as discrete components, fabricated on other types of substrates such as composite substrates, for example. Currently, there are various electrical systems capable of resonance, such as piezoelectric resonators and inductance-capacitance resonators. When sufficient energy is supplied to these resonators to compensate for their inherent energy dissipation, they can function as oscillators. Resonators are configured to modify the signals they receive into corresponding output signals with altered characteristics. For example, resonators can be used as filters in the field of signal and image processing.Furthermore, oscillators are configured to generate signals, particularly signals used by electronic circuits in various technical fields such as telecommunications, sensors, radars, measuring devices, etc. Thus, for telecommunications systems, the oscillator's main role is to provide signals to drive external circuits, such as mixers, transmitters, receivers, etc.

[0003] Generally speaking, a resonator is an electrical circuit which, at a given frequency, called the resonant frequency or operating frequency, presents an impedance across its terminals, having a zero imaginary part and a non-zero real part, called the pure resistance. In the case of a passive resonator, the real part is positive and represents the inherent losses of the resonator. For an active resonator, that is, one comprising transistors, the transistors make it possible to reduce the value of the real part (and therefore the losses), or even to make the real part negative. In the case of active resonators with a negative real part, the resonator is said to be lossless and naturally generates a periodic signal across its terminals. In this case, the resonator is therefore considered an oscillator.An oscillator is understood to be a device equipped with a resonator electrically coupled to a transistor circuit, also called a loss compensation circuit, and a biasing circuit to operate the transistors, in order to produce a periodic electrical signal. that is to say a signal having a frequency denoted oscillation frequency. An oscillator can generate a signal at a fixed frequency or at a variable frequency; we then speak of a VCO (according to the English acronym for "Voltage Controlled Oscillator").

[0004] One can cite, for example, the publication: "77.3-GHz Standing-Wave Oscillator Based on an Asymmetrical Tunable Slow-Wave Coplanar Stripline Resonator," L. Gomes et al. in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 8, pp. 3158-3169, Aug. 2021, which discloses a loss-compensated oscillator using an active transistor crossover pair. However, such an oscillator experiences a drastic decrease in performance, and more specifically an increase in power consumption and a decrease in its oscillating capacity, when coupled to an external circuit with low impedance (typically less than one hundred ohms). To solve this problem, the authors use "buffers" (i.e., buffer amplifiers), designed to isolate the oscillator from an external circuit in order to limit the disturbances of the external circuit on the oscillator. But adding such buffer amplifiers loads the oscillator capacitively.This results in a reduced operating frequency range when used as a voltage-controlled oscillator, as well as a reduced maximum operating frequency. Furthermore, the buffers require a larger silicon area, increasing manufacturing costs. The structure of such an oscillator is more complex. Finally, the addition of buffers leads to increased power consumption. These buffers therefore impact the oscillator's performance by reducing the maximum operating frequency, increasing power consumption, narrowing the operating frequency range in the case of a voltage-controlled oscillator, and increasing the circuit size and cost.

[0005] For example, one can cite the publication: “A 64 GHz 5 mW Low Phase Noise gm-Boosted Colpitts CMOS VCO with Self-Switched Biasing Technique,” ​​TN Nguyen, PP Pande, and D. Heo, in IEEE MTT-S Int. Microw. Symp. Dig., May 2015, pp. 17-22, which discloses a voltage-controlled oscillator that uses a technique for improving the efficiency of active compensation by using a transconductance boosting effect on the transistors (the transconductance of a transistor is denoted gm, and the “gm-boost” effect, in English, corresponds to the transconductance boosting effect). The gm-boost effect is obtained by adding two additional transistors. However, this solution is only possible with Colpitts oscillators (that is, oscillators whose oscillation frequency is determined by two capacitors and an inductor). Furthermore, the addition transistors in series are constrained to a higher minimum supply voltage than if there were only one transistor.

[0006] An object of the present invention is therefore to propose a transistor system, hereinafter referred to as the active cell, to overcome the disadvantages mentioned above and whose performance is improved compared to prior art transistor systems.

[0007] Another object is to provide an active cell that can function as a resonator or oscillator.

[0008] Another object is to provide an active cell that operates with a lower power consumption than prior art transistor systems.

[0009] Another object is to provide an active cell whose maximum operating frequency is increased compared to prior art transistor systems.

[0010] Another object is to provide an active variable frequency cell whose operating frequency range is increased compared to prior art transistor systems.

[0011] Another object is to provide an active cell that operates with external circuits of lower impedance than that permitted by prior art systems.

[0012] Another object is to provide an oscillator based on an active cell, the size of which is reduced compared to prior art transistor systems. SUMMARY

[0013] To achieve these objectives, a transistorized system is proposed, comprising: - the first and second main boundary markers; and - an inductive device.

[0014] The system further comprises: - a first transistor comprising a first terminal, called the control terminal, coupled to the inductive device, a second terminal, called the input terminal, coupled to the first main terminal, and a third terminal, called the output terminal, the control, input and output terminals of the first transistor being configured to be coupled to a biasing circuit; and - a second transistor comprising a first terminal, called the control terminal, coupled to the inductive device, a second terminal, called the input terminal, coupled to the second main terminal, and a third terminal, called the output terminal, the control, input and output terminals of the second transistor being configured to be coupled to the biasing circuit; - a first capacitive component connected in series between the input terminal of the first transistor and the output terminal of the second transistor; and - a second capacitive component coupled in series between the input terminal of the second transistor and the output terminal of the first transistor.

[0015] Thus, a transistor system is provided that limits losses, increases the operating frequency, and consumes little power, while remaining simple, compact, and robust. Such a system is particularly well-suited for operation as a loss-compensated resonator or as an oscillator with improved compatibility with external circuits, capable of driving both low-impedance and high-impedance external circuits, as with prior art oscillators.

[0016] According to another aspect, a resonator is proposed, comprising a transistor system as defined above and a biasing circuit coupled to the input, output and control terminals of the first and second transistors of the transistor system, the transistor system being configured to present an impedance having a positive or zero real part so that the transistor system is configured to function as a resonator capable of modifying a current flowing between the first and second main terminals of the transistor system.

[0017] According to another aspect, an oscillator is proposed, comprising a transistor system as defined above and a biasing circuit coupled to the input, output and control terminals of the first and second transistors of the transistor system, the transistor system being configured to present an impedance having a negative real part so that the transistor system is configured to function as an oscillator capable of generating periodic signals on the first and second main terminals of the transistor system. BRIEF DESCRIPTION OF THE FIGURES

[0018] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0019] [Fig.1] [Fig.2] [Fig.3] [Fig.4] [Fig.5] [Fig.6] [Fig.7] [Fig.8] [Fig.9] [Fig.10] [Fig.11] [Fig.12] [Fig.13] [Fig.14] [Fig.15] [Fig.16] [Fig.17] [Fig.18] [Fig.19] [Fig.20] Figures 1 to 20 represent different embodiments of a transistor system, hereinafter referred to as the active cell; and

[0020] [Fig.21] [Fig.22] [Fig.23] Figures 21 to 23 represent different modes of realization of the active cell and a biasing circuit.

[0021] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. DETAILED DESCRIPTION

[0022] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in association or alternatively are stated below.

[0023] According to one example, the transistor system is configured so that, when the input terminals and output terminals receive respective biasing potentials supplied by the biasing circuit, the potential at the output terminal of the first transistor is strictly greater than the potential at the input terminal of the second transistor, and the potential at the output terminal of the second transistor is strictly greater than the potential at the input terminal of the second first transistor.

[0024] According to one example, the first and second transistors are of the field-effect type.

[0025] According to one example, the first and second transistors are of the bipolar type.

[0026] According to one example, the transistor system comprises first and second secondary terminals configured to be coupled to the biasing circuit, the inductive device comprising first and second inductive components each having first and second terminals, the first inductive component having its first terminal coupled to the control terminal of the first transistor and its second terminal coupled to the first secondary terminal, and the second inductive component having its first terminal coupled to the control terminal of the second transistor and its second terminal coupled to the second secondary terminal.

[0027] According to one example, each of the first and second inductive components is configured to have a variable inductance.

[0028] According to one example, the inductive device includes at least one inductive component coupled between the respective control terminals of the first and second transistors.

[0029] According to one example, said at least one inductive component is configured to have a variable inductance.

[0030] According to one example, the inductive device includes at least one piezoelectric component coupled between the respective control terminals of the first and second transistors.

[0031] According to one example, the inductive device includes at least one additional capacitive component coupled between the respective control terminals of the first and second transistors.

[0032] According to one example, said at least one additional capacitive component is configured to have a variable capacitance.

[0033] According to one example, the system comprises first and second reference terminals configured to receive a reference potential supplied by the biasing circuit, and wherein the inductive device comprises a third capacitive component coupled between the control terminal of the first transistor and the first terminal of reference, and a fourth capacitive component coupled between the control terminal of the second transistor and the second reference terminal.

[0034] According to one example, each of the third and fourth capacitive components is configured to have a variable capacitance.

[0035] It is specified that, within the framework of the present invention, the expressions "A coupled to B", "A electrically coupled to B", "A connected to B", or "A electrically connected to B" are synonymous with "A is electrically connected to B" and do not necessarily mean that there is no component between A and B. Thus, these expressions refer to an electrical connection between two elements, this connection being either direct or indirect. This means that it is possible for a current to flow between a first device A and a second device B that are electrically connected, linked, or coupled, at A, at B, and along the path connecting A to B, this path being either or not including other electrical equipment. Device A can be electrically coupled to B, either in series or in parallel.

[0036] Conversely, in the context of the present invention, the term "electrically connected directly" or "directly connected" refers to a direct electrical connection between two elements. This means that between a first device A and a second device B that are electrically connected directly, no other equipment is present, other than an electrical connection or several electrical connections.

[0037] Figures 1 to 23 show a transistor system 1, also referred to as the active cell. The active cell 1 is configured to operate as either a resonator or an oscillator. Generally, when the active cell is configured to operate as a resonator, it modifies the received signal into a corresponding output signal with altered characteristics. For example, in signal processing, the active cell 1 can be used to filter the received signal. Conversely, when the active cell is configured to operate as an oscillator, it generates periodic signals having a frequency, referred to as the oscillation frequency.

[0038] Generally, the active cell 1 comprises first and second main terminals N1, N2 and an inductive device 2. The inductive device 2 is configured to generate a magnetic field when a current flows through it. In particular, the inductive device 2 comprises at least one inductive component 3, L1, L2 configured to generate a magnetic field when a current flows through the inductive component 3, L1, L2.

[0039] More specifically, the active cell 1 comprises first and second transistors T1, T2 and first and second capacitive components Cl, C2. The first and second capacitive components Cl, C2 are also denoted components Main capacitive Cl, C2. In general, a capacitive Cl, C2 component can be a capacitor, for example a discrete chemical, ceramic, tantalum, electrolytic capacitor, etc. A capacitive component can also be an integrated capacitor of the MOM type (from the English acronym for "Metal-Oxide-Metal", i.e. metal-oxide-metal), MIM type (from the English acronym for "Metal-Insulator-Metal", i.e. metal-insulator-metal), or MOS type (from the English acronym for "Metal-Oxide-Semiconductor", i.e. metal-oxide-semiconductor).

[0040] Generally, the first transistor Tl comprises a first control terminal cdl, coupled to the inductive device 2. The first transistor Tl further comprises a second input terminal el, coupled to the first main terminal NI, and a third output terminal si. The input terminal el, output terminal si, and control terminal cdl of the first transistor Tl are configured to be coupled to a biasing circuit 10, as illustrated in Figures 21 to 23.

[0041] Furthermore, the second transistor T2 includes a first terminal cd2, called the control terminal, coupled to the inductive device 2. The second transistor T2 also includes a second terminal e2, called the input terminal, coupled to the second main terminal N2, and a third terminal s2, called the output terminal. The input terminal e2, the output terminal s2, and the control terminal cd2 of the second transistor T2 are configured to be coupled to the biasing circuit 10.

[0042] For example, the first and second transistors T1, T2 are of the field-effect type, denoted FET (Field-Effect Transistor), as illustrated in Figures 1 to 23. In this case, the input terminal e1, e2 of a FET is called the source; the output terminal s1, s2 of a FET is called the drain; and the control terminal cd1, cd2 of a FET is called the gate. For example, the first and second transistors T1, T2 may be of the MOSFET type (Metal-Oxide-Semiconductor Field-Effect Transistor). Depletion mode MOSFETs (or "Depletion mode" in English) or inversion mode MOSFETs (or "Enhancement mode" in English) can be used.

[0043] Other transistors may be used. For example, JFETs (Junction Field-Effect Transistors); MESFETs (Metal-Semiconductor Field-Effect Transistors); DMOS transistors (Double-Diffused Metal-Oxide-Semiconductor (i.e., metal-oxide-semiconductor by double diffusion); GaN FETs (or gallium nitride field-effect transistors); InP FETs (or indium phosphide field-effect transistors); SiC FETs (or silicon carbide field-effect transistors); HEMTs (High Electron Mobility Transistors); HFETs (Heterostructure Field-Effect Transistors); MODFETs (Modulation-Doped Field-Effect Transistors); FinFET transistors (according to the English acronym for "Fin Field-Effect Transistor", i.e., finned field-effect transistor);or Dual-Gate FET transistors (or double-gate field-effect transistors); OFET transistors (Organic Field-Effect Transistors, i.e., field-effect transistors using an organic semiconductor); TFET transistors (Tunnel Field-Effect Transistors, i.e., Tunnel field-effect transistors); or any type of component classified as a field-effect transistor.

[0044] Alternatively, the first and second transistors T1, T2 are of the bipolar type. In this case, the input terminal e1, e2 of a bipolar transistor is called the emitter; the output terminal s1, s2 of a bipolar transistor is called the collector; and the control terminal cd1, cd2 of a bipolar transistor is called the base.

[0045] For example, B JT transistors (according to the English acronym for "Bipolar Junction transistors", i.e., junction bipolar transistor) can be used; HBT transistors (according to the English acronym for "Heterojunction Bipolar Transistor", i.e., heterojunction bipolar transistor); or any type of component classified in the category of bipolar transistors.

[0046] According to another variant, hybrid transistors can be used, having a MOSFET-type input and a bipolar-type output. For example, IGBT transistors (Insulated-Gate Bipolar Transistor) can be used.

[0047] In addition, the first capacitive component Cl is coupled in series, preferably directly, between the input terminal el of the first transistor T1 and the output terminal s2 of the second transistor T2.

[0048] The second capacitive component C2 is coupled in series, and preferably directly, between the input terminal e2 of the second transistor T2 and the output terminal si of the first transistor T1.

[0049] Generally, a cross connection is established between the output terminals si, s2 and the input terminals el, e2 of the first and second transistors Tl, T2.

[0050] Generally, the inductive device 2 is coupled to the respective control terminals cdl, cd2 of the first and second transistors Tl, T2 of the active cell 1. The active cell 1 has an impedance whose real part Rin is adjustable via the characteristics of the first and second transistors Tl, T2, which makes it active. Furthermore, the first and second transistors Tl, T2 are supplied by supply voltages VI, V2 applied respectively to the input terminals e1, e2 and output terminals si, s2 of the first and second transistors Tl, T2, by the biasing circuit 10.

[0051] In particular, the biasing circuit 10 is intended to bias the first and second transistors T1, T2. It is also said that the biasing circuit 10 supplies the transistors T1, T2 of the active cell 1 so that the transistors T1, T2 operate. More specifically, the biasing circuit 10 is configured to bias the transistors T1, T2, so that the transistors T1, T2 operate in active, or linear, mode.

[0052] Thus, when the transistors Tl, T2 operate in linear mode, the transistors Tl, T2 function as AC signal amplifiers.

[0053] In other words, the biasing circuit 10 is configured to provide biasing potentials Vsl, Vs2 respectively at the output terminals si, s2 of transistors Tl, T2 and to provide biasing potentials Vel, Ve2 respectively at the input terminals el, e2 of transistors Tl, T2. Furthermore, the biasing circuit 10 is configured to provide biasing potentials Vcdl, Vcd2 respectively at the control terminals cdl, cd2 of transistors Tl, T2. For example, the active cell 1 may include first and second secondary terminals 01, 02 configured to be coupled to the biasing circuit 10. The secondary terminals 01, 02 are configured to provide biasing potentials Vcdl, Vcd2 respectively at the control terminals cdl, cd2 of transistors Tl, T2.For example, the secondary terminals 01, 02 can be coupled either directly to the respective control terminals cdl, cd2 of transistors T1, T2, as illustrated in Figures 7 to 20, or indirectly, as illustrated in Figures 1 to 6, and 21 to 23. It should also be noted that, for each transistor, the supply voltage VI, V2 is equal to the difference between the bias potential Vsl, Vs2 and the bias potential Vel, Ve2. In general, it is also said that when the biasing circuit 10 supplies, or applies, a bias potential to the input terminals e1, e2, output terminals si, s2, and control terminals cdl, cd2 of transistors T1, T2, the transistors T1, T2 are biased. More specifically, the supply voltages VI, V2, the bias potentials Vsl, Vs2, Vel, Ve2, Vcdl, Vcd2 are DC values. .

[0054] More specifically, the active cell 1 is configured such that when the input terminals e1, e2; the output terminals s1, s2; and the control terminals cd1, cd2 receive the respective DC bias potentials Vel, Ve2, Vs1, Vs2 and Vcd1, Vcd2 supplied by the biasing circuit 10, the potential Vs1 at the output terminal s1 of the first transistor T1 is strictly greater than the potential Ve2 at the input terminal e2 of the second transistor T2, and the potential Vs2 at the output terminal s2 of the second transistor T2 is strictly greater than the potential Vel at the input terminal e1 of the first transistor T1. For example, the DC bias potentials can be applied respectively to the terminals of transistors T1 and T2 via a generator.

[0055] In other words, the main capacitive components Cl, C2 allow the output terminals si, s2 of the transistors Tl, T2 to be biased at a potential level higher than the potential level applied to the input terminals e1, e2 of the transistors Tl, T2. The main capacitive components Cl, C2 behave as a short circuit for alternating current, that is, they allow alternating current to flow, or rather, they allow radio frequency signals to pass. More specifically, the main capacitive components Cl, C2 behave as a short circuit by electrically coupling, and preferably directly, the input terminal e1, e2 of one transistor Tl, T2 with the output terminal s2, si of the other transistor Tl, T2. The main capacitive components Cl, C2 allow the radio frequency signals to flow unimpeded.Furthermore, the main capacitive components Cl, C2 ensure that the transistors Tl, T2 of system 1 function as amplifiers.

[0056] Thus, the active cell 1 equipped with the first and second transistors T1, T2 is said to be active, and one of its main properties is to compensate for the losses of the inductive device 2. Indeed, the inductive device 2 allows the active cell 1 to function as a resonator or an oscillator. In both cases, the inductive device 2 induces losses that can be compensated by the active cell 1.

[0057] In order to specify the advantages of the invention, equations relating characteristic physical parameters of the components of the active cell 1, as defined according to a preferred embodiment illustrated in [Fig. 3], will be presented. According to the preferred embodiment, the inductive device 2 comprises first and second inductive components L1, L2. Other embodiments of the inductive device 2 are envisaged and will be described later. According to the preferred embodiment, the inductive components L1, L2 each have first and second terminals, the first inductive component L1 having its first terminal coupled to the control terminal cd1 of the first transistor T1 and its second terminal coupled to the first secondary terminal O1. The second inductive component L2 has its first terminal coupled to the control terminal cd2 of the second transistor T2 and its second terminal coupled to the second secondary terminal 02. Optionally, the active cell 1 includes first and second reference terminals RI, R2 configured to receive a reference potential Vref supplied by the biasing circuit 10, as illustrated in Figures 3 to 5, 15, 20, and 23. Furthermore, the inductive device 2 may include additional third and fourth capacitive components C3, C4. The third capacitive component C3 is coupled between the first reference terminal RI and the first secondary terminal 01, and the fourth capacitive component C4 is coupled between the second reference terminal R2 and the second secondary terminal 02. Such additional capacitive components C3, C4 allow control of the operating frequency of the active cell 1.

[0058] To simplify the following equations, the elements of active cell 1 will be chosen such that the inductive components L1, L2 have the same inductance L, and the additional capacitive components C3, C4 have the same capacitance C. Furthermore, transistors T1, T2 with the same characteristics will be chosen. More specifically, the first and second transistors T1, T2 will be chosen to have the same transconductance, denoted gm. The capacitance values ​​of the main capacitive components C1, C2 do not appear in the equation because, as indicated above, the main capacitive components C1, C2 act as a short circuit for the alternating currents.

[0059] According to the embodiment illustrated in [Fig.3], the inductive device 2 has a complex impedance Z, which can be determined by the following equation 1:

[0060] [Math.l] Z = j(œL - ) (Equation 1).

[0061] The impedance Z of the inductive device 2 is said to be complex because it has an imaginary part, with j representing the imaginary unit.

[0062] In equation 1, the impedance Z corresponds to the complex impedance of the inductive device 2 (whose unit is in Ohms), j is a complex number whose square is -1; co corresponds to the angular frequency of the active cell 1 (whose unit is in radians per second); L corresponds to the inductance of the inductive components L1, L2 (whose unit is in Henrys); and C corresponds to the capacitance of the additional capacitive components C3, C4 (whose unit is in Farads). It is also noted that the angular frequency co of the active cell 1 is a function of the operating frequency f of the active cell 1 such that co = 2 * ji * f.

[0063]

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070]

[0071] By applying Kirchhoff's circuit law, we can determine the complex admittance Yin, at a principal terminal NI, N2 of the active cell 1, according to the following equation 2: [Math.2] (Equation 2) with : - Yin: the complex admittance at the main terminal NI, N2 of the active cell 1 (whose unit is in Ohm'); - Io: the current flowing at the main terminal NI, N2 of the active cell 1 (expressed in Amperes); - Vo: the bias potential at the main terminal NI, N2 of the active cell 1 (expressed in Volts); - Cgd: the intrinsic capacitance between the control terminal cdl, cd2 and the output terminal si, s2 of a transistor Tl, T2 (whose unit is in Farad); - Cgs: the intrinsic capacitance between the control terminal cdl, cd2 and the input terminal el, e2 of a transistor Tl, T2 (whose unit is in Farads); and - gm: corresponds to the transconductance of a transistor T1, T2 (whose unit is in Ohm'). A specific Gin term can be expressed by the following equation 3: [Math.3] G* — s tn om (equation 3). Gin (whose unit is in Ohm') corresponds to the conductance value of the complex admittance Yin. Thus, we can deduce from equation 3 that the value of conductance Gin of the complex admittance Yin can be positive or negative. Furthermore, it is noted that the active cell 1 provides a resistance Rin, called input resistance, between its main terminals NI, N2 which can be expressed by the following equation 4: [Math.4] i / r in ) (equation 4).

[0072] That is to say that the input resistance Rin is equal to the real part of 1 / Yin, that is to say that Rin is equal to the real part of the complex impedance Zin= 1 / Yin at the main terminal NI, N2 of the active cell 1 (whose unit is in Ohm).

[0073] In other words, the input resistance Rin of the active cell 1 corresponds to the real part of the complex impedance Zin at the main terminal NI, N2 of the active cell 1.

[0074] Thus, the active cell 1 is configured to provide an input resistance Rin between its main terminals NI, N2 which can be either positive or zero, or negative.

[0075] We can also note the following equation 5:

[0076] [Math.5] f 1 “0 yl \ gscg^ ycj (equation 5).

[0077] The frequency f0 corresponds to the operating frequency of interest of the active cell 1 (whose unit is in Hertz). The operating frequency of interest f0 can be either the resonance frequency, when the active cell 1 functions as a resonator, or the oscillation frequency, when the active cell 1 functions as an oscillator.

[0078] It is also noted that the operating frequency of interest cüo of the active cell 1 is a function of the operating frequency of interest f0 of the active cell 1 such that (o0 = 2 * jt * f0.

[0079] It can be noted that the operating frequency of interest f0 is defined by equation 5 when the imaginary part of the complex admittance Yin is zero. Thus, according to equations 2 and 5, it can be noted that for a first frequency range, the input resistance Rin is negative, and for a second frequency range, the input resistance Rin is positive or zero. The upper limit of the first frequency range is less than or equal to the lower limit of the second frequency range. The frequency ranges depend on the value of the inductance L, the characteristics of the first and second transistors T1, T2, and the value of the capacitance C.

[0080] According to equation 5, it can be noted that the operating frequency of interest f0 , is a function of the characteristics of the transistors Tl, T2 of the active cell 1, and in particular of the intrinsic capacitances Cgs, Cgd of said transistors Tl, T2.

[0081] Moreover, at the operating frequency of interest f0, the input resistance Rin can be expressed by the following equation 6:

[0082] [Math.6] (Equation 6).

[0083] According to equation 6, it can be noted that, according to the invention, the active cell 1 has, at the operating frequency of interest f0, an input resistance Rin whose term is a function of the intrinsic capacitances Cgs, Cgd of the transistors T1, T2, thus increasing the capacity of the active cell 1 to compensate for higher dissipative loads. In other words, the active cell 1 has an input resistance Rin that can have different values ​​depending on the characteristics of the first and second transistors T1, T2, and in particular depending on the intrinsic capacitances Cgs, Cgd of the transistors T1, T2. Because the transistors T1, T2 of the system are active, the active cell 1 according to the invention is called an active system. In particular, when the system operates as an oscillator, a differential active oscillator 1 is provided because it has two main terminals N1, N2 to generate two periodic signals.Furthermore, oscillator 1 is configured to generate signals in opposite phase. Generally, transistors T1 and T2 compensate for the losses of the inductive device 2, and the active cell 1 is called a self-compensating system. Active cell 1 is also said to function as an autonomous system.

[0084] Thus, when the input resistance Rin is positive or zero, at the operating frequency of interest f0, the active cell 1 is configured to function as a resonator. A resonator is a device described as a receiver (such as a resistor, etc.). That is to say, a resonator dissipates energy. It should also be noted that the intrinsic capacitances Cgs, Cgd can be chosen so that Rin is positive and strictly less than (2 / gm). In this case, the active cell 1 compensates for the losses due to the inductive device in a better way compared to a conventional system which has an equivalent internal resistance equal to (2 / gm). Thus, according to the invention, the proposed resonator is said to be low-loss, because it has a lower input resistance Rin than a conventional resonator and therefore minimizes losses.

[0085] Furthermore, when the active cell 1 is configured to operate as a resonator, the active cell 1 can be connected in series or in parallel with an alternating signal generator, not shown for the sake of simplicity. In particular, when the active cell 1 is connected in series, the active cell 1 receives signals on one of its main terminals NI, N2, referred to as the input terminal, and it outputs signals with modified characteristics on the other main terminal N2, NI, referred to as the output terminal.

[0086] Furthermore, when the active cell 1 is coupled in parallel, the active cell 1 receives signals at both the two main terminals NI and N2, and the active cell 1 emits from these two main terminals NI and N2 signals with modified aspects.

[0087] Generally, when the active cell 1 is configured to function as a resonator, the active cell 1 is capable of modifying a current flowing between the first and second main terminals NI, N2 of the active cell 1.

[0088] Furthermore, when the input resistance Rin is negative, at the operating frequency of interest f0, the active cell 1 is configured to function as an oscillator. An oscillator is a device classified as a generator. That is to say, an oscillator provides energy. In addition, an oscillator generates periodic signals at its terminals, called output terminals. In particular, when the active cell 1 functions as an oscillator, the active cell 1 is configured to deliver two periodic signals at the main terminals N1 and N2, respectively. Advantageously, the oscillator, according to the invention, can compensate for the losses of an external circuit having a lower impedance (typically less than one hundred ohms) than that which a conventional oscillator can compensate.Furthermore, the oscillator according to the invention allows an external circuit to be directly coupled to the input terminals NI, N2 of system 1, without necessarily having to use additional buffers. Moreover, if buffers coupled to the main terminals NI, N2 of the active cell 1 were used, the energy required to start the oscillations would be very low (for example, an energy reduction of up to 50%), and could provide a very low-power system.

[0089] There are different embodiments of the active cell 1. Generally, when the inductive device 2 comprises two inductive components L1, L2 directly coupled in series, as illustrated in Figures 7, 9, 10, and 20, the two inductive components L1, L2 can be replaced by a single inductive component L1. Similarly, when the inductive device 2 comprises two additional capacitive components C3, C4 directly coupled in series, as illustrated in Figures 6, 8, and 10, the two additional capacitive components C3, C4 can be replaced by a single additional capacitive component C3.

[0090] For example, the additional capacitive components C3, C4 may have a constant capacitance, as illustrated in Figures 3, 5, 6, 8 to 13, 20 and 23, so that the signals emitted by the active cell 1 have a constant frequency depending on the capacitance of the third and fourth capacitive components C3, C4.

[0091] Alternatively, each of the additional capacitive components C3, C4 may have a variable capacitance, as illustrated in Figures 4, 15 and 17, so that the signals emitted by the active cell 1 have a frequency that varies according to the capacitance The third and fourth capacitive components C3 and C4. A capacitive component with variable capacitance is defined as a capacitance component whose capacitance can be configured to have different values. In other words, each additional capacitive component C3 and C4 can be configured to have a variable capacitance. For example, the additional capacitive components C3 and C4 could be variable capacitance diodes (also called varactors or varactor diodes).

[0092] By analogy, the inductive components L1, L2 can have a constant inductance, and the signals emitted by the active cell 1 then have a constant frequency. Alternatively, the inductive components L1, L2 can have a variable inductance, that is, an inductance configured to have different values. In this case, the signals emitted by the active cell 1 then have a variable frequency, that is, a frequency configured to have different values.

[0093] Advantageously, when the active cell 1 functions as an oscillator, the system can be configured so that the two output signals have the same determined frequency, whether constant or variable. For example, when the inductive device 2 includes first and second inductive components L1, L2, these components have inductances of the same value. Furthermore, when the inductive device 2 includes additional capacitive components C3, C4, these components have capacitances of the same value.

[0094] According to embodiments illustrated in Figures 1 to 6, the inductive device 2 comprises first and second inductive components L1, L2, each having first and second terminals. The first inductive component L1 has its first terminal coupled to the control terminal cd1 of the first transistor T1 and its second terminal coupled to the first secondary terminal 01 of the active cell 1. Furthermore, the second inductive component L2 has its first terminal coupled to the control terminal cd2 of the second transistor T2 and its second terminal coupled to the second secondary terminal 02 of the active cell 1.

[0095] According to the embodiment illustrated in [Fig.2], the first and second inductive components L1, L2 each have a variable inductance so that the signals emitted by the active cell 1 have a variable frequency depending on the inductance of the first and second inductive components L1, L2.

[0096] Advantageously, as illustrated in Figures 3 to 5, the active cell 1 comprises the first and second reference terminals RI, R2 configured to receive the reference potential Vref supplied by the biasing circuit 10. In addition, the inductive device 2 comprises a third additional capacitive component C3 coupled between the control terminal cdl of the first transistor Tl and the first reference terminal Ride of the active cell 1, and a fourth capacitive component additional C4 coupled between the control terminal cd2 of the second transistor T2 and the second reference terminal R2 of the Active cell 1.

[0097] According to the embodiments illustrated in Figures 3 and 4, the additional capacitive components C3, C4 are coupled, preferably directly, in series with respectively the first and second inductive components L1, L2, between respectively the control terminal cd1, cd2, of a transistor T1, T2 and the first and second reference terminals RI, R2

[0098] According to the embodiment illustrated in [Fig. 5], the capacitive components Additional components C3, C4 are coupled, preferably directly, in parallel with respectively the first and second inductive components L1, L2. For example, the additional capacitive components C3, C4 are coupled directly to the respective control terminals cd1, cd2 of the transistors T1, T2.

[0099] According to the embodiment illustrated in [Fig. 6], the inductive device 2 comprises at least one additional capacitive component C3, C4 coupled between the respective control terminals cdl, cd2 of the first and second transistors Tl, T2.

[0100] According to other embodiments, illustrated in Figures 7 to 13, the inductive device 2 comprises at least one inductive component L1, L2 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2. Furthermore, the first and second secondary terminals 01, 02 are coupled, preferably directly, respectively to the control terminals cd1, cd2 of the transistors T1, T2.

[0101] Advantageously, according to the embodiments illustrated in figures 8 to 13, the inductive device 2 comprises at least one additional capacitive component C3, C4 coupled between the respective control terminals cdl, cd2 of the first and second transistors Tl, T2.

[0102] For example, according to the embodiment illustrated in [Fig.8], the inductive device 2 comprises two inductive components L1, L2 coupled respectively to the control terminals cd1, cd2 of the first and second transistors T1, T2, and two additional capacitive components C3, C4 coupled in series between the two inductive components L1, L2.

[0103] According to the embodiment illustrated in [Fig.9], the inductive device 2 comprises two additional capacitive components C3, C4 coupled respectively to the control terminals cdl, cd2 of the first and second transistors Tl, T2, and two inductive components Ll, ​​L2 coupled in series between the two additional capacitive components C3, C4.

[0104] According to the embodiment illustrated in [Fig. 10], the inductive device 2 comprises two additional capacitive components C3, C4 coupled in parallel with the respective control terminals cdl, cd2 of the first and second transistors Tl, T2, and two inductive components L1, L2 coupled in parallel to the control terminals cdl, cd2 respective of the first and second transistors T1, T2.

[0105] According to the embodiment illustrated in [Fig. 11], the inductive device 2 comprises a first group G1 including a first additional capacitive component C3 coupled in parallel with a first inductive component L1, and a second group G2 including a second additional capacitive component C4 coupled in parallel with a second inductive component L2. The first group G1 and the second group G2 are connected in series between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0106] According to the embodiment illustrated in [Fig. 12], the inductive device 2 comprises a first group G1 including a first additional capacitive component C3 coupled in parallel with a first inductive component LL. The first group G1 and a second inductive component L2 are coupled in series between the respective control terminals cdl, cd2 of the first and second transistors Tl, T2.

[0107] According to the embodiment illustrated in [Fig. 13], the inductive device 2 comprises a first group G1 including a first additional capacitive component C3 coupled in parallel with a first inductive component LL. The first group G1 and a second additional capacitive component C4 are coupled in series between the respective control terminals cdl, cd2 of the first and second transistors Tl, T2.

[0108] According to other embodiments, illustrated in Figures 14 to 19, the inductive device 2 comprises at least one piezoelectric component 3 coupled between the respective control terminals cdl, cd2 of the first and second transistors Tl, T2. Furthermore, the first and second secondary terminals 01, 02 are coupled, preferably directly, respectively to the control terminals cdl, cd2 of the transistors Tl, T2.

[0109] Advantageously, according to the embodiment illustrated in [Fig.15], the inductive device 2 comprises a third additional capacitive component C3 coupled between the control terminal cdl of the first transistor T1 and the first reference terminal RI, and a fourth additional capacitive component C4 coupled between the control terminal cd2 of the second transistor T2 and the second reference terminal R2.

[0110] According to the embodiments illustrated in figures 16 to 19, the inductive device 2 comprises at least one inductive component L1, L2 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0111] For example, according to the embodiment illustrated in [Fig. 16], the inductive device 2 comprises two inductive components L1, L2 coupled respectively to the control terminals cd1, cd2 of the first and second transistors T1, T2, and a piezoelectric component 3 coupled in series between the two inductive components L1, L2.

[0112] According to the embodiment illustrated in [Fig. 17], the inductive device 2 comprises two inductive components L1, L2 coupled respectively to the control terminals cd1, cd2 of the first and second transistors T1, T2, two additional capacitive components C3, C4 coupled respectively in series with the first inductive component L1 and a piezoelectric component 3, and with the second inductive component L2 and the piezoelectric component 3.

[0113] According to the embodiment illustrated in [Fig. 18], the inductive device 2 comprises an additional capacitive component C3, preferably with variable capacitance, coupled in parallel with the respective control terminals cdl, cd2 of the first and second transistors Tl, T2, an inductive component Ll coupled in parallel with the respective control terminals cdl, cd2 of the first and second transistors Tl, T2, and a piezoelectric component 3 coupled in parallel with the respective control terminals cdl, cd2 of the first and second transistors Tl, T2.

[0114] According to the embodiment illustrated in [Fig. 19], the inductive device 2 comprises a group G1 including an additional capacitive component C3, preferably with variable capacitance, coupled in series with a piezoelectric component 3. The group G1 and an inductive component L1 are coupled in parallel between the respective control terminals cd1, cd2 of the first and second transistors T1, T2.

[0115] According to another embodiment, illustrated in [Fig. 20], the inductive device 2 comprises at least one inductive component L1, L2 coupled between the respective control terminals cd1, cd2 of the first and second transistors T1, T2. Furthermore, the first and second secondary terminals 01, 02 are coupled, preferably directly, respectively to the control terminals cd1, cd2 of the transistors T1, T2. In addition, the active cell 1 comprises the first and second reference terminals RI, R2 configured to receive the reference potential Vref supplied by the biasing circuit 10.

[0116] Furthermore, the inductive device 2 includes a third capacitive component C3 coupled between the control terminal cdl of the first transistor Tl and the first reference terminal RI, and a fourth capacitive component C4 coupled between the control terminal cd2 of the second transistor T2 and the second reference terminal R2.

[0117] Figures 21 to 23 show a biasing circuit 10. Generally, the biasing circuit 10 is coupled to the input terminals e1, e2, output terminal si, s2, and control terminal cdl, cd2 of each of the first and second transistors T1, T2. Generally, the biasing circuit 10 is configured to apply, for each of the first and second transistors T1, T2, the supply voltage V1, V2 between the output terminal si, s2 and the input terminal e1, e2 of transistor T1, T2, and a current to the output terminal si, s2 of transistor T1, T2. In addition, the biasing circuit 10 can be configured to provide the potentials biasing Vcdl, Vcd2 on the respective control terminals cdl, cd2 of transistors Tl, T2, via the first and second secondary terminals 01,02.

[0118] There are different embodiments of the biasing circuit 10.

[0119] Figure 21 shows a biasing circuit 10 comprising a first voltage source 11 coupled to the output terminals ε1, ε2 of transistors T1, T2, for example via dissipative components 12. The dissipative components 12 may be resistors or inductors. Furthermore, the biasing circuit 10 includes a second voltage source 13 coupled to the input terminals ε1, ε2 of transistors T1, T2, for example via additional dissipative components 14. The additional dissipative components 14 may be resistors or inductors. The biasing circuit 10 also includes a third voltage source 15 coupled to the first and second inductive components L1, L2 via the first and second secondary terminals 01, 02.For example, the third voltage source 15 can supply the bias potentials Vcdl, Vcd2 on the respective control terminals cdl, cd2 of transistors Tl, T2, via the first and second secondary terminals 01, 02.

[0120] In [Fig.22], a biasing circuit 10 is shown comprising a first current source 16 coupled to the output terminals si, s2 of the transistors Tl, T2, for example via dissipative components 12. Furthermore, the biasing circuit 10 includes a current-consuming element 17 coupled to the input terminals el, e2 of the transistors Tl, T2, for example via additional dissipative components 14. The biasing circuit 10 further includes the third voltage source 15 coupled to the inductive components Ll, ​​L2, via the first and second secondary terminals 01, 02.

[0121] In general, the active cell 1 is particularly suitable for being coupled to an external circuit 20 having a low impedance, that is to say typically an impedance of less than one hundred Ohms, for example about 50 Ohms, which corresponds to most of the circuits used in the field of telecommunications, such as transmitter and / or transmitter circuits, and for radio frequency applications.

[0122] The biasing circuit 10 is configured to allow continuous currents and signals to pass while blocking alternating currents and signals.

[0123] Figure 23 shows a preferred embodiment of an active cell 1 coupled to a biasing circuit 10 and an external circuit 20. According to the preferred embodiment, the external circuit 20 is electrically coupled to the input terminals e1, e2 of the transistors T1, T2, via the main terminals N1, N2 of the active cell 1. Thus, the external circuit 20 can be electrically coupled to the terminals The output of transistors T1 and T2 is s2. This is possible because nodes N1, e1, and s2 are electrically coupled to each other. Similarly, nodes N2, e2, and s1 are electrically coupled to each other.

[0124] Furthermore, the third voltage source 15 can supply the bias potentials Vcdl, Vcd2 on the respective control terminals cdl, cd2 of the transistors Tl, T2, via the first and second secondary terminals 01,02.

[0125] Advantageously, when the additional capacitive components C3, C4 each have a constant capacitance, the system 1 can output signals at a predetermined frequency, and a fixed-frequency oscillator can be provided. Conversely, when the additional capacitive components C3, C4 each have a variable capacitance, the active cell 1 can output signals at an adjustable frequency, and a VCO-type oscillator can be provided. The frequency of the output signals is determined by equation 5. More specifically, the active cell 1 has an operating frequency of interest f0 when the inductive device 2 resonates or oscillates in conjunction with the intrinsic capacitances of the transistors T1, T2.

Claims

Demands

1. Transistor system, comprising: • first and second main terminals (NI, N2); and • an inductive device (2), characterized in that the system further comprises: • a first transistor (Tl) comprising a first terminal (cdl), called the control terminal, coupled to the inductive device (2), a second terminal (el), called the input terminal, coupled to the first main terminal (NI), and a third terminal (si), called the output terminal, the control, input and output terminals (cdl, el, si) of the first transistor (Tl) being configured to be coupled to a biasing circuit (10);• a second transistor (T2) comprising a first terminal (cd2), called the control terminal, coupled to the inductive device (2), a second terminal (e2), called the input terminal, coupled to the second main terminal (N2), and a third terminal (s2), called the output terminal, the control, input and output terminals (cd2, e2, s2) of the second transistor (T2) being configured to be coupled to the biasing circuit (10); • a first capacitive component (Cl) coupled in series between the input terminal (el) of the first transistor (Tl) and the output terminal (s2) of the second transistor (T2); and • a second capacitive component (C2) coupled in series between the input terminal (e2) of the second transistor (T2) and the output terminal (si) of the first transistor (Tl).

2. System according to the preceding claim, configured such that, when the input terminals (el, e2) and the output terminals (si, s2) receive respective biasing potentials supplied by the biasing circuit (10), the potential (Vsl) at the output terminal (si) of the first transistor (Tl) is strictly greater than the potential (Ve2) at the input terminal (e2) of the second transistor (T2), and the potential (Vs2) at the output terminal (s2) of the second transistor (T2) is strictly greater than the potential (Vel) at the input terminal (el) of the second first transistor (Tl).

3. System according to any one of the preceding claims, wherein the first and second transistors (T1, T2) are of the field-effect type.

4. System according to any one of claims 1 to 2, wherein the first and second transistors (T1, T2) are of the bipolar type.

5. System according to any one of the preceding claims, comprising first and second secondary terminals (01, 02) configured to be coupled to the biasing circuit (10), the inductive device (2) comprising first and second inductive components (L1, L2) each having first and second terminals, the first inductive component (L1) having its first terminal coupled to the control terminal (cd1) of the first transistor (T1) and its second terminal coupled to the first secondary terminal (01), and the second inductive component (L2) having its first terminal coupled to the control terminal (cd2) of the second transistor (T2) and its second terminal coupled to the second secondary terminal (02).

6. System according to the preceding claim, wherein each of the first and second inductive components (L1, L2) is configured to have a variable inductance.

7. System according to any one of claims 1 to 4, wherein the inductive device (2) comprises at least one inductive component (L1, L2) coupled between the respective control terminals (cd1, cd2) of the first and second transistors (T1, T2).

8. System according to the preceding claim, wherein said at least one inductive component (L1, L2) is configured to have a variable inductance.

9. System according to any one of claims 1 to 8, wherein the inductive device (2) comprises at least one piezoelectric component (3) coupled between the respective control terminals (cdl, cd2) of the first and second transistors (Tl, T2).

10. System according to any one of the preceding claims, wherein the inductive device (2) comprises at least one additional capacitive component (C3, C4) coupled between the respective control terminals (cdl, cd2) of the first and second transistors (Tl, T2).

11. System according to the preceding claim, wherein said at least one additional capacitive component (C3, C4) is configured to have a variable capacitance.

12. System according to any one of claims 1 to 9, comprising first and second reference terminals (RI, R2) configured to receive a reference potential (Vref) supplied by the biasing circuit (10), and wherein the inductive device (2) comprises a third capacitive component (C3) coupled between the control terminal (cdl) of the first transistor (Tl) and the first reference terminal (RI), and a fourth capacitive component (C4) coupled between the control terminal (cd2) of the second transistor (T2) and the second reference terminal (R2).

13. System according to the preceding claim, wherein each of the third and fourth capacitive components (C3, C4) is configured to have a variable capacitance.

14. Resonator, comprising a transistor system according to any one of the preceding claims and a biasing circuit (10) coupled to the control (cdl, cd2), input (el, e2) and output (si, s2) terminals of the first and second transistors (Tl, T2) of the transistor system, the transistor system being configured to exhibit an impedance having a positive or zero real part (Rin) such that the transistor system is configured to function as a resonator capable of modifying a current flowing between the first and second main terminals (NI, N2) of the transistor system.

15. Oscillator, comprising a transistor system according to any one of claims 1 to 13, and a biasing circuit (10) coupled to the control terminals (cdl, cd2), input (el, e2) and output (si, s2) of the first and second transistors (Tl, T2) of the transistor system, the transistor system being configured to exhibit an impedance having a negative real part (Rin) so that the transistor system is configured to function as an oscillator capable of generating periodic signals on the first and second main terminals (NI, N2) of the transistor system.

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