Magnetoresistive torque memory with enhanced readout

Abstract

The invention relates to a memory circuit (D1) comprising a read circuit (CL) and a memory matrix (M1, M2) comprising at least one magnetoresistive memory cell (CM); the memory cell (CM) comprising: a pillar (MTJ), a write track (SOT) in a spin Hall effect material or an orbital Hall effect material; a first selector (S1) and a second selector (S2) each selector (S1,S2) being configured to switch from a blocking state to a conducting state when the amplitude of the voltage across said selector is greater than a predetermined threshold voltage Vth; the read circuit (CL) comprising: a current source (GC) configured to inject a read current (Iread) through the first selector (S1); a detection circuit (CD) configured to detect the switching of the second selector (S2) from a blocking state to a conducting state in response to the injection of the read current (Iread) according to the resistive state of the magnetic tunnel junction.Figure for the summary: Fig. 3.

Description

Title of the invention: Magnetoresistive torque memory with enhanced readout. Scope of application

[0001] The present invention relates to the field of non-volatile memory circuit design and more particularly to enhanced read performance of spin-orbit torque or orbital Hall effect magnetoresistive memory cells. Technical problem

[0002] Spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) is an advanced non-volatile memory that uses magnetic mechanisms to store data. It is based on a magnetic tunnel junction, in the form of a pillar, whose resistance varies according to the orientation of the magnetic layers. Unlike conventional MRAM, SOT MRAM uses spin-orbit transfer, where currents through a track formed by materials with strong spin-orbit coupling induce the switching of the magnetic state in a tunnel junction structure in contact with said track. This allows for faster switching, better endurance, and increased energy efficiency. SOT MRAM technology is ideal for applications requiring fast, non-volatile, and durable memory.This durability is achieved because writing does not require the writing current to pass through the magnetic tunnel junction pillar.

[0003] Two states are defined for a non-volatile memory: a low resistive state (LRS) and a high resistive state (HRS). To perform a read operation, the current through the magnetic tunnel junction pillar is measured by applying a read voltage (Vread) across the pillar. When the pillar is in a high resistive state, a current (Iread HRs) is measured, corresponding to a resistance denoted Rap (Anti-Parallel configuration) in the case of an MRAM memory cell. When it is in a low resistive state, a current (Iread l RS) greater than Iread h RS is measured, corresponding to a resistance denoted RP (Parallel configuration) in the case of an MRAM memory cell. For non-volatile memory, a first criterion called "read margin" MW is defined which depends on the ratio Iread LRs / Iread - greater than 1. The "read error rate" RDM (acronym for Read Disturb Margin) depends on the stability of this ratio.This means that Iread_LRs and Iread_HRs must remain significantly different and as stable as possible over time, even after many write and read cycles. Drift in the Iread_LRs and Iread_HRs read currents can be caused by heating in the... materials composing the magnetic tunnel junction pillar induced by read currents. Repeated heating induces a loss of spin stability in the magnetic tunnel junction and thus a drift in the values ​​of Iread I RS and Iread _HRS, thereby increasing the risk of read errors.

[0004] Furthermore, in spin-orbit transfer magnetoresistive memories, the difference between the high and low resistance states is very small compared to that between other memory technologies. This drawback leads to a limitation of the dynamic range (also called the memory window) of the memory locations constituting the data storage circuit. The limitation of the dynamic range of the memory locations considerably reduces the ability of the read circuits to differentiate resistance levels and leads to an increase in read errors.

[0005] Thus, there is a need to design new magnetoresistive memory cell architectures in which the read margin (MW) is stabilized, the read error rate (RDM) is reduced, and the difference between the currents Iread, LRset, and kead (hrs) is increased. These three criteria make it possible to considerably increase the read reliability of a memory circuit based on MRAM memory cells.

[0006] The same need exists with the concept of MRAM-OTT (Orbital Transfer Torque) memory, which uses the injection of orbital moment currents instead of spin currents by replacing the tungsten SOT write track with an OTT track, for example, made of titanium. The invention is described for MRAM-SOT memory cells with a write track made of a spin-orbit torque material but remains valid also for MRAM-OTT (Orbital Transfer Torque) memories. The advantages and characteristics described for MRAM-SOT memory cells remain valid for MRAM-OTT memories. Answer to the problem and provision of a solution

[0007] To overcome the limitations of existing solutions, the invention proposes a memory circuit based on MRAM-SOT memory cells with two selectors and several embodiments of adapted read circuits. The read circuit according to the invention implements a read operation based on the injection of a read current rather than a read voltage. Reading a low resistive state is achieved by reading a leakage current rather than an injected read current. This makes it possible to widen the difference between Iread_LRS and Iread_hrs and thus improve the reliability of the read circuit according to the invention. Furthermore, the read circuit according to the invention minimizes the current flowing through the MTJ tunnel junction when reading a high resistive state (HRS). This reduces the heating effects in the tunnel junction and thus stabilizes the memory's read margin (MW) for several read / write cycles.

[0008] Furthermore, the invention presents a plurality of memory matrix architectures made by MRAM-SOT memory cells and compatible with the different reading modes proposed by the invention.

[0009] Summary / Claims

[0010] The invention relates to a memory circuit comprising a read circuit and a memory matrix comprising at least one magnetoresistive memory cell; the memory cell comprising: - a pillar forming a magnetic tunnel junction having an upper end and a lower end; said upper end forming a first node intended to receive a first control voltage; - a writing track made of a spin Hall effect material or an orbital Hall effect material; the pillar being disposed on said writing track on the side of its lower end to configure the resistance of the magnetic tunnel junction between a high resistive state Rap and a low resistive state RP; - a second node intended to receive a second control voltage and a third node; - a first selector mounted between the third node and a first end of the write track and a second selector mounted between the second node and a second end of the write track opposite to the first end; Each selector switch is configured to switch from a blocking state to a conducting state when the voltage across the selector exceeds a predetermined threshold voltage V*. The readout circuit includes: - a current source connected to the third node and configured to inject a read current through the first selector; - a detection circuit configured to detect the switching of the second selector from a blocking state to a conducting state in response to the injection of the reading current according to the resistive state of the magnetic tunnel junction.

[0011] According to a particular aspect of the invention, the detection circuit comprises a current comparator having a first input connected to the second node and having a second input receiving a reference current lower than the reading current and higher than the leakage current of the second selector when it is in a blocking state.

[0012] According to a particular aspect of the invention, the detection circuit comprises a current comparator having a first input connected to the first node and having a second input receiving a reference current lower than the reading current and higher than the leakage current of the magnetic tunnel junction when it is in a high resistive state R^.

[0013] According to a particular aspect of the invention, the detection circuit comprises a current comparator having a first input connected to the first node and having a second input connected to the second node.

[0014] According to a particular aspect of the invention, the current source is configured to inject a readout current having an amplitude greater than and RAP ROFF,S2 ih less than rp+roffs2 ; R0FF S2 being the resistance of the second selector when it is Rp R()FFS2 th in a blocking state.

[0015] According to a particular aspect of the invention, the current source is configured to inject a readout current having an amplitude greater than [R0FF S1]; R0FF S1 being the R0FFS] resistance of the first selector when it is in the blocking state.

[0016] According to a particular aspect of the invention, the current source is configured to inject a reading current having an amplitude greater than vti> then R(>FFSl Increase the amplitude of the read current until it reaches a value greater than rap+roffsi; Roff S1 being the resistance of the first selector when it is in the Rap state Roffs2 Ri blocking; ROff,s2 being the resistance of the second selector when it is in the blocking state.

[0017] According to a particular aspect of the invention: - the first nodes of the memory cells belonging to the same column of the memory matrix are interconnected via a first conductive line intended to propagate the first associated control voltage; - the second nodes of the memory cells belonging to the same row of the memory matrix are interconnected via a second conductive line intended to propagate the second associated control voltage; - the third nodes of the memory cells belonging to the same row of the memory matrix are interconnected via a third conductive line intended to propagate the read current.

[0018] According to a particular aspect of the invention, the memory circuit further comprises control means configured to perform a read operation of a selected memory cell of the matrix by connecting its first node and its second node to electrical ground; and by applying to the unselected memory cells a first non-zero control voltage lower than the predetermined threshold voltage Vth.

[0019] According to a particular aspect of the invention: - the first nodes of the memory cells belonging to the same column of the memory matrix are interconnected via a first conductive line intended to propagate the first associated control voltage; - the second nodes of the memory cells belonging to the same column of the memory matrix are interconnected via a second conductive line intended to propagate the second associated control voltage; - the third nodes of the memory cells belonging to the same row of the memory matrix are interconnected via a third conductive line intended to propagate the read current.

[0020] According to a particular aspect of the invention, the memory circuit further comprises control means configured to perform a read operation of a selected memory cell of the matrix by connecting its first node and its second node to the electrical ground; and by applying to the unselected memory cells a first non-zero control voltage lower than the predetermined threshold voltage V* and a second non-zero control voltage lower than the predetermined threshold voltage V*. Detailed description

[0021] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0022] Fig. 1 illustrates a cross-sectional view of a spin-orbit torque magnetoresistive memory cell used in the memory circuit according to the invention.

[0023] Figure [Fig. 2] illustrates a functional diagram of the memory circuit according to the invention.

[0024] Figure 3 illustrates a functional diagram of a reading circuit according to a first embodiment of the invention associated with a spin-orbit torque magnetoresistive memory cell.

[0025] Figure 4a illustrates the reading circuit according to the first embodiment of the invention during the reading of a low resistive state LRS.

[0026] Figure 4b illustrates a timing diagram of the currents and voltages of a cell magnetoresistive memory with spin-orbit couple when reading a low resistive state LRS by the reading circuit according to the first embodiment of the invention.

[0027] Figure 5a illustrates the reading circuit according to the first embodiment of the invention during the reading of a high resistive state HRS.

[0028] Figure 5b illustrates a timing diagram of the currents and voltages of a cell magnetoresistive memory with spin-orbit couple when reading a high resistive state HRS by the reading circuit according to the first embodiment of the invention.

[0029] Figure 6a illustrates a functional diagram of a reading circuit according to a second embodiment of the invention associated with a spin-orbit torque magnetoresistive memory cell.

[0030] Figure 6b illustrates a functional diagram of a reading circuit according to a third embodiment of the invention associated with a spin-orbit torque magnetoresistive memory cell.

[0031] Fig. 7a illustrates an electrical diagram of a first memory matrix used in the memory circuit according to the invention.

[0032] Figure 7b illustrates an electrical diagram of a second memory matrix used in the memory circuit according to the invention.

[0033] The invention relates to a memory circuit comprising an array formed by MRAM-SOT memory cells. By way of illustration and not limitation, we will begin by describing an example of an MRAM-SOT memory cell used to implement a memory circuit according to the invention.

[0034] Figure 1 illustrates a cross-sectional view of a spin-orbit coupled magnetoresistive CM memory cell used in the memory circuit according to the invention. The CM memory cell comprises a magnetic tunnel junction MTJ, a write track SOT, a support layer 14, a first electrode ELI, and a second electrode EL2.

[0035] The magnetic tunnel junction MTJ is a magnetoresistive pillar comprising a stack of layers 11, 12, 13 that work together to enable data storage and retrieval through the manipulation of magnetic properties. The stack includes a first reference ferromagnetic layer 11 in which the direction of magnetic polarization is fixed and uniform. The stack further includes a second ferromagnetic layer 13 in which the direction of magnetic polarization is variable. The stack also includes a tunnel barrier layer 12 of oxide, such as MgO (magnesium oxide), confined between the first and second ferromagnetic layers 11, 13. This layer plays a crucial role in the magnetoresistive tunneling effect, allowing electrons to pass through by quantum tunneling. The first ferromagnetic layer 11 serves as a reference for detecting changes in magnetization in the free ferromagnetic layer 13.For example, the first and second layers 11,13 are composed of materials such as CoFeB. The operating principle of the magnetoresistive MTJ pillar relies on the change in electrical resistance depending on the magnetic polarization orientation of the free ferromagnetic layer 13 relative to that of the reference ferromagnetic layer 11. When the magnetizations of the free and reference layers 11,13 are parallel, the electrical resistance is low across the MTJ magnetic tunnel junction pillar. When the magnetizations are antiparallel, the electrical resistance is high. This change in resistance is detected to read a memory state (bit 0 or 1). This change in resistance is triggered to write a memory state (bit 0 or 1).

[0036] The MTJ magnetic tunnel junction is arranged on the SOT write track. The interface between the MTJ magnetic tunnel junction and the SOT write track is on the side of the free ferromagnetic layer 13. The direction of the stack forming the MTJ magnetic tunnel junction is orthogonal to the plane formed by the layer forming the SOT write track. The SOT write track is made of a spin Hall effect material (also called a spin-orbit couple effect material), for example, beta-phase tungsten, bismuth antimonide, a BiSbTe alloy, or a stack of two layers, one tantalum and the other tungsten. When a write current flows through the SOT write track in a given direction, spin currents are generated and interact with the free ferromagnetic layer 13.This interaction allows control of the magnetic polarization direction in the free ferromagnetic layer 13 according to the direction of the write current in the SOT write track. Controlling the magnetic polarization direction in the free ferromagnetic layer 13 allows modification of the electrical resistance of the MTJ magnetic tunnel junction without injecting a write current, which considerably increases the robustness of the CM memory cell.

[0037] The SOT writing track is disposed on a first face 141 of the support layer 14. The support layer 14 is made of a material having a metal-insulator transition, more particularly a Mott oxide. This type of material exhibits the possibility of a volatile resistive transition between a high resistive state and a low resistive state. This transition is activated thermally and / or electrically and / or optically. It consists of a non-permanent (volatile) phase change between a stable, high-resistance, orthoclinic semiconducting phase and a metastable, low-resistance, conductive, rutile tetragonal phase. The low resistive state is maintained only under thermal, electrical, or optical stimulation. The invention exploits electrical stimulation by applying an electric field.

[0038] The first ELI electrode is disposed on a second face 142 of the support layer 14 opposite the first face 141. The first ELI electrode is positioned below a first end of the SOT write track. The second EL2 electrode is disposed on the second face 142. The second EL2 electrode is positioned below a second end of the SOT write track opposite the first end. The pillar forming the magnetic tunnel junction MTJ is located between the first end and the second end. The first ELI electrode and the second EL2 electrode are each made of an electrically conductive metal layer, for example, preferably tungsten, copper, or titanium nitride.

[0039] From an electrical point of view, a first VRBL control voltage is applied to the upper end of the pillar forming the MTJ magnetic tunnel junction, which forms a first RBL input / output node. A second voltage of A VBLB control voltage is applied to the second electrode EL2, which forms a second input / output node BLB. A third VBL control voltage is applied to the first electrode ELI, which forms a third input / output node BL.

[0040] The stack formed by the first electrode ELI, area 143 of the support layer 14 made of a metal-insulating transition material, and the write track SOT locally forms a small selector SI. The selector SI is configurable between a high resistive state R0FF >Si and a low resistive state R0N,si by applying a voltage between the first electrode ELI and the write track SOT, i.e., the first and third voltages VRBL, VBL. Similarly, the stack formed by the second electrode EL2, area 144 of the support layer 14 made of a metal-insulating transition material, and the write track SOT locally forms a second small selector S2. The second selector S2 is configurable between a high resistive state R0FF,S2 and a low resistive state R0N,S2 via the application of a voltage between the second electrode EL2 and the write track SOT, i.e. the first and second voltage VRBL, VBLB.For each selector between SI and S2, activation (transition from R0FF to R0N) is triggered when the voltage amplitude across the selector exceeds a predetermined threshold voltage V*. For example, for a vanadium oxide support layer 14, the threshold voltage is 0.6V, which is compatible with the voltage operating ranges of a magnetoresistive memory cell.

[0041] Alternatively, the support layer 14 comprises a low-voltage (< 1 V) topological insulator, for example molybdenum disulfide. A topological insulator is a material that has the desirable property of behaving as an insulator internally (it does not conduct electricity through its volume), while having conductive surfaces or edges. This type of material is called "topological" because its surface conductive properties are protected by topological features of the material's electronic structure, meaning that they are robust against disturbances such as impurities or structural defects.

[0042] Selectors SI and S2 can be activated simultaneously by means of the same control voltage (same amplitude and same sign) or independently by means of two separate control voltages (same amplitude and opposite signs). Therefore, the direction of current flow through the selectors can be controlled according to the sign of the applied voltage, either upwards (from the associated electrode to the SOT write track) or downwards (from the SOT write track to the electrode). Thus, a bipolar current can flow through the entire SOT track for writing with commands of opposite signs, and a unipolar current can flow through the MTJ pillar after traversing half of the SOT track for reading with commands of the same sign.

[0043] In the embodiment of [Fig. 1], the stacking direction is as follows, starting from the substrate along the Z-axis: electrodes E1 and EL2, then support layer 14, then write track SOT, then pillar MTJ. Alternatively, the memory cell 10 can be implemented in the reverse direction with respect to the cell illustrated in [Fig. 1], starting from the substrate as the origin of the Z-axis. The pillar is oriented downwards. The stacking direction is as follows, starting from the substrate along the Z-axis: pillar MTJ oriented downwards, then write track SOT, then support layer 14, then electrodes EL1 and EL2 on the upper surface. The downward-oriented pillar MTJ is encapsulated in a dielectric layer.

[0044] Alternatively, the memory cell 10 according to the invention is a magnetoresistive memory cell exploiting the Orbital Hall effect. This embodiment differs from the embodiment of [Fig. 1] in that the write track is configured to generate an orbital momenta current from a charge current and not a spin current. The advantage of a write path separate from the read path is retained. Writing is performed by converting the charge current into an orbital momenta current, which has a similar ability to spin current to exert a torque on the magnetization of a magnetic layer. This is the orbital Hall effect (OHE), which differs from the spin Hall effect. Writing by orbital Hall effect improves the characteristics of magnetic memories.The structure of an orbital Hall effect device is similar to that of a spin-orbit device, except that the writing track, also called the "OT" track for "Orbital Torque," is configured to generate an orbital momenta current from a charge current. Orbital moments cannot directly apply torque to the magnetization of the MTJ pillar junction. One of two mechanisms may be required. The action of orbital moments on the magnetization can be due to spin-orbital entanglement, and / or a portion of the orbital momenta current is converted into spin current at the MTJ pillar junction, with the spin current applying torque to the magnetization of the MTJ pillar junction.In the case of an orbital Hall effect memory cell, the OT write track is made of chromium or zirconium or titanium or vanadium or copper or manganese or molybdenum or ruthenium or aluminium or niobium or tungsten in alpha phase. .

[0045] Figure 2 illustrates a functional diagram of a DI memory circuit according to the invention, comprising a memory matrix Mx formed by a plurality of CM memory cells according to the invention, a CONT control circuit, and at least one CL read circuit. The CONT control circuit is configured to generate the first control voltage VRBL, the second control voltage VBLB, and the third voltage VBL control for each CM memory cell. The CL read circuit is configured to read the logic state stored in a CM memory cell of the Mx matrix.

[0046] Figure 3 illustrates a functional diagram of the CL read circuit according to a first embodiment of the invention. The CL read circuit is associated with a CM spin-orbit couple magnetoresistive memory cell to illustrate the operation of a read operation according to the invention.

[0047] In the CM memory cell, the first selector SI behaves like a switch controlled by the potential difference VS1. When the first selector SI is in a conducting state, it is modeled as a resistance R0N,Si, and when it is in a blocking state, as a resistance R0FF,Si. The second selector S2 behaves like a switch controlled by the potential difference VS2. When the second selector S2 is in a conducting state, it is modeled as a resistance R0N >S2, and when it is in a blocking state, as a resistance R0FF,S2. The portion of the write track SOT located between the first selector SI and the base of the MTJ pillar is modeled by a resistance Rsot / 2, where Rsmki is the equivalent electrical resistance of the write track. Symmetrically, the portion of the SOT write track located between the second selector S2 and the base of the MTJ pillar is modeled by a resistance RSOt / 2.The two resistors Rsot / 2 are connected in series, and their common node NC is a central node located at the base of the MTJ pillar. The MTJ pillar is modeled by a variable resistor RMTJ according to the binary data "1" or "0" stored in the CM memory cell. To simplify the description of the invention, it is assumed that the two selectors SI and S2 are identical and therefore R0FF jSi=R20ff ,S2 and that R0N ,si=Ron ,s2- .

[0048] The read circuit CL includes a current source GC connected to the third node BL and configured to inject a read current Iread through the first selector S1 to trigger a read operation. The direction of the read current Iread is from the third node BL to the write track SOT. The amplitude of the read current Iread is greater than ^th to switch the first Roffm SI selector in a state passing under the action of the read current Iread.

[0049] The reading circuit CL further comprises a detection circuit CD configured to detect the switching of the second selector S2 from a blocking state to a conducting state in response to the injection of the reading current Iread. According to a particular aspect of the invention, the detection circuit CD is a DC current comparator having a first input e1 connected to the second node BLB and a second input e2 receiving a reference current Iref. The first input e1 receives the current Is2 which flows through the second selector S2. If the second selector S2 is in the blocking state, it carries a leakage current IS2 = Ieak,S2 less than 5 pA. If the second selector S2 is in the state When passing through, it carries a current almost equal to the reading current IS2 ~ Iread. A current close to the reading current Iread is defined as one with an amplitude greater than 80% of the reading current Iread. The DC current comparator is configured to generate a high logic state at its output when the current received at its first input is the leakage current IS2 = Iieak, S2. Conversely, the DC current comparator is configured to generate a low logic state at its output when the current received at its first input el is close to the reading current Iread (or vice versa, depending on the chosen convention). To perform this function, the reference current Iref has an amplitude lower than the reading current Iread and greater than the leakage current Iieak > S2 of the second selector S2 when it is in a blocking state.

[0050] Figure 4a illustrates the operation of the CL readout circuit according to the first embodiment of the invention during the readout of a low resistive state LRS. As a reminder, the low resistive state LRS corresponds to a parallel distribution of spins in the MTJ pillar, resulting in a low resistance RP. Initially, both selectors SI and S2 are in a blocking state. The CONT control circuit is configured to apply a first control voltage VRBL = 0 and a second control voltage VBLB = 0. To trigger a readout operation, the current source GC is configured to inject a readout current Iread greater than vth into the first selector SI, which induces the switching of the first selector SI to an ROFF.S1 passing state. At the central node NC, the reading current is distributed between the branch corresponding to the MTJ pillar and the branch corresponding to the second selector S2 such that Iread= Is2 + Imtj- The MTJ pillar presents the least resistive current path among the two branches because RP< R0PP ,S2- The ratio Ïmtj depends on the ratio rqffs2; RMTJ When Rmtj = Rp the jmtj ratio is high and when Rmtj = Rap the Imtj ratio is Isi Is2 minimum. The amplitude of the read current Iread is less than rp+roffsi. of Rp roffs> In this configuration, the IS2 current is used to maintain the second selector S2 in a blocking state. In conclusion, when the MTJ pillar is in the low resistive state LRS, injecting the read current Iread according to the invention switches the first selector SI to a conducting state while keeping the second selector S2 in a blocking state. The second selector S2 thus carries its leakage current IS2 = Ieak,S2, while the magnetic tunnel junction MTJ carries a current IMTJ * Iread. The current comparator CC receives a current lower than the reference current Iref at its first input and generates a high logic state (or vice versa, depending on the chosen convention) corresponding to the logic state stored in the CM memory cell.

[0051] Figure 4b illustrates a timing diagram of the currents and voltage of a memory cell CM during the reading of a low resistive state LRS by the read circuit according to the first embodiment of the invention. The read current Iread gradually increases until it reaches a value greater than vth to switch roffjh The first selector S1 is in a conducting state. The switching of the first selector corresponds to the pulse observed for the voltage VS1. Subsequently, a steady state is established in which the voltage VS2 has a constant value less than Vth, which induces the second selector S2 to remain in a blocking state. For this configuration, the current through selector S2 stabilizes at a value less than 5pA (3.4pA in the illustrated example) and the current through the MTJ pillar stabilizes at a value close to the read current Iread.

[0052] Figure 5a illustrates the operation of the CL readout circuit according to the first embodiment of the invention during the readout of a high resistive state HRS. As a reminder, the high resistive state HRS corresponds to an antiparallel spin distribution in the MTJ pillar, resulting in a high resistance RA P. Initially, both selectors SI and S2 are in a blocking state. The CONT control circuit is configured to apply a first control voltage VRBL = 0 and a second control voltage VBLB = 0. To trigger a readout operation, the current source GC is configured to inject a readout current Iread greater than vtk into the first selector SI, which induces the switching of the first selector SI to a KoFFSl In the current state, at the central node NC, the read current is distributed between the branch corresponding to the MTJ pillar and the branch corresponding to the second selector S2 such that Iread = L2 + Imtj. The amplitude of the read current Iread is greater than Rap + roff² so that in this configuration there is a current IS2 which allows RAP roff² > th to switch the second selector S2 to a conducting state. Thus, a short circuit is created between the second node BLB and the third node BL when the MTJ pillar is in the high resistive state HRS. The injection of the read current Iread according to the invention allows the first selector SI and the second selector S2 to be successively switched to a conducting state. The second selector S2 is thus traversed by a current almost equal to the read current IS2 ~ Iread, while the magnetic tunnel junction MTJ is traversed by a leakage current IMTJ = Iieak, mtj-. The current comparator CC receives at its first input el a current greater than the reference current Iref and generates a low logic state "0" (or vice versa depending on the chosen convention) corresponding to the logic state stored in the memory cell CM.

[0053] Figure 5b illustrates a timing diagram of the currents and voltages in a memory cell CM during the reading of a high resistive state HRS by the read circuit CL according to The first embodiment of the invention. The read current Iread gradually increases until it reaches a value greater than to switch RqFFSI The first selector S1 is in a conducting state. The switching of the first selector corresponds to the pulse observed for the voltage VS1. In response to this, the current IS2 through the second selector S2 gradually increases until it reaches a value greater than the threshold at which the second selector S2 switches to a conducting state. ^OFFS2 The switching of the second selector corresponds to the pulse observed for the voltage VS2. Then, a steady state is established in which the current through the selector S2 stabilizes at a value almost equal to the amplitude of the reading current Ireadet the current through the pillar MT J stabilizes at a residual value corresponding to the leakage current through the pillar Iieak , MTJ.

[0054] A first advantage resulting from the reading operation according to the invention is the minimization of the current intensity required to read a low resistive state LRS, which corresponds to the leakage current of selector S2. Thus, the invention makes it possible to broaden the dynamic range of the memory cell CM. This leads to an improvement in the ability of the reading circuit CL according to the invention to differentiate resistance levels and results in a considerable reduction of read errors.

[0055] An additional advantage lies in minimizing the current intensity through the MTJ pillar during the reading of a high resistive state HRS, which corresponds to the leakage current of the tunnel junction. Thus, the invention makes it possible to reduce the heating effects in the tunnel junction and therefore to stabilize the MW read margin of the CM memory cell according to the invention.

[0056] Advantageously, the injection of the read current is carried out sequentially according to a succession of phases. Thus, the current source GC is configured to inject, in a first phase, a read current Iread having an amplitude greater than vth to switch the first selector SI first. ^OFFS^ Next, the GC current source is configured to increase the amplitude of the read current Iread until it reaches a value greater than RAP+RoFFÿ2 to potentially switch the second selector S2 but less than rp+roffs2 The two-phase operation prevents the risk of memory cell failure due to a sudden application of high current. Alternatively, the GC current source is configured to inject the read current Iread in progressively increasing steps.

[0057] Alternatively, the GC current source is configured to inject the read current Iread, which increases progressively to its final value, while maintaining a sufficiently long rise time to prevent memory cell failure. By sufficiently long time, we mean a rise time between the current value vth (to switch the SI selector) and the final current value (RFFS\ Rap^Roi^ but <rp+rqffs2 ) plus long que le temps de commutation des — rap ropps2   th       rp roffsi & selectors, for example greater than or equal to 5ns.

[0058] Figure 6a illustrates a functional diagram of a readout circuit CL according to a second embodiment of the invention associated with a memory cell CM. The second embodiment differs from the first embodiment by the arrangement of the DC current comparator. In the second embodiment, the first input el of the DC current comparator is connected to the first input / output node RBL to compare the current flowing through the tunnel junction pillar MTJ with the reference current Iref. In the second embodiment, the reference current Iref has an amplitude lower than the readout current Iread and higher than the leakage current Iieak, mtj of the pillar MTJ when it is in a high resistive state HRS. The operation and advantages described for the first embodiment remain valid for the second embodiment.

[0059] Figure 6b illustrates a functional diagram of a readout circuit CL according to a third embodiment of the invention associated with a memory cell CM. The third embodiment differs from the first embodiment by the arrangement of the DC current comparator. In the third embodiment, the first input e1 of the DC current comparator is connected to the first input / output node RBL, and the second input e2 is connected to the second node BLB to compare the current flowing through the tunnel junction pillar MTJ with the current through the second selector S2. The operation and advantages described for the first embodiment remain valid for the second embodiment.

[0060] Fig. 7a illustrates an electrical diagram of a memory matrix M1 used in the DI memory circuit according to a first embodiment of the invention.

[0061] The memory matrix Ml is formed by a plurality of memory cells CM according to the invention arranged in rows L and columns Ck, i=0 to N and k=0 to M. By way of illustration and not limitation, the matrix Ml is formed by two rows Lo, Li and two columns Co and Cb

[0062] The first RBL input / output nodes of the CM memory cells belonging to the same column Ck of the memory matrix Ml are interconnected via a first conductive line Ll,k intended to propagate the first control voltage VRBLk is associated with said column Ck. The second input / output nodes BLB of the memory cells CM belonging to the same row L of the memory matrix Ml are interconnected via a second conductive line L2,i intended to propagate the second control voltage VBLB; associated with said line. The third input / output nodes BL of the memory cells 10 belonging to the same row of the memory matrix Ml are interconnected via a third conductive line L3,i intended to propagate the third control voltage VBL; associated.

[0063] This matrix architecture is compatible with the read mode according to the invention described above. Table 1 illustrates the control voltages applied by control means to perform the selection and read of a CM memory cell in the context of the ML matrix Selected cell Unselected cells Ibl Iread 0A VblB ov OV Vrbl ov 0 <vrbl<vth Advantageously, for unselected cells, the CONT control means are configured to apply 0.2x Vth <vrbl<0,8xvthpour éviter la sélection accidentelle de cellules mémoire non ciblées.

[0064] Figure 7b illustrates an electrical diagram of a memory matrix M2 used in the DI memory circuit according to a second embodiment of the invention.

[0065] The memory matrix M2 is formed by a plurality of memory cells CM according to the invention arranged in rows L and columns Ck, i=0 to N and k=0 to M. By way of illustration and not limitation, the matrix M1 is formed by two rows Lo, Li and two columns Co and Cb

[0066] The first RBL input / output nodes of the CM memory cells belonging to the same column Ck of the memory matrix M2 are interconnected via a first conductive line L1,k intended to propagate the first control voltage VRBLk associated with said column Ck. The second BLB input / output nodes of the CM memory cells belonging to the same column Ck of the memory matrix M2 are interconnected via a second conductive line L2,k intended to propagate the second control voltage VBLBk associated with said column. The third BL input / output nodes of the memory cells 10 belonging to the same row of the memory matrix M1 are interconnected via a third conductive line L3,i intended to propagate the third associated control voltage VBL.

[0067] This matrix architecture is compatible with the reading mode according to the invention described above. Table 2 illustrates the control voltages applied to perform the selection and reading of a CM memory cell in the context of the M2 matrix. Selected cell Unselected cells Ibl J rend OA VblB ov 0 <vblb<vth vrbl ov ocvrblcvth Advantageously, for unselected cells, the CONT control means are configured to apply 0.2xVth< / vblb<vth>

Claims

1. Demands Memory circuit (D1) comprising a read circuit (CL) and a memory matrix (M1, M2) comprising at least one magnetoresistive memory cell (CM); the memory cell (CM) comprising: - a pillar (MTJ) forming a magnetic tunnel junction (MTJ) having an upper end and a lower end; said upper end forming a first node (RBL) intended to receive a first control voltage (VRBL); - a writing track (SOT) made of a spin Hall effect material or an orbital Hall effect material; the pillar (MTJ) being disposed on said writing track (SOT) on the side of its lower end to configure the resistance (RMtj) of the magnetic tunnel junction (MTJ) between a high resistive state Rap and a low resistive state RP; - a second node (BLB) intended to receive a second control voltage (VBLB) and a third node (BL); - a first selector (SI) mounted between the third node (BL) and a first end of the write track (SOT) and a second selector (S2) mounted between the second node (BLB) and a second end of the write track (SOT) opposite the first end; each selector (S1, S2) being configured to switch from a blocking state to a conducting state when the amplitude of the voltage across said selector is greater than a predetermined threshold voltage V*; the reading circuit (LC) comprising: - a current source (GC) connected to the third node (BL) and configured to inject a read current (Iread) through the first selector (SI); - a detection circuit (CD) configured to detect the switching of the second selector (S2) from a blocking state to a conducting state in response to the injection of the read current (Iread) according to the resistive state of the magnetic tunnel junction.

2. Memory circuit (Dl) according to claim 1 wherein the detection circuit (CD) comprises a current comparator (CC) having a first input (el) connected to the second node (BLB) and having a second input (e2) receiving a reference current (Iref) lower than the read current (Iread) and higher than the leakage current (Iieak,S2) of the second selector (S2) when it is in a blocking state.

3. Memory circuit (Dl) according to claim 1 wherein the sensing circuit (CD) comprises a current comparator (CC) having a first input (el) connected to the first node (RBL) and having a second input (e2) receiving a reference current (Iref) lower than the read current (Iread) and higher than the leakage current (Iieak, mtj) of the magnetic tunnel junction (MTJ) when it is in a high resistive state Rap.

4. Memory circuit (Dl) according to claim 1 in which the detection circuit (CD) comprises a current comparator (CC) having a first input (el) connected to the first node (RBL) and having a second input (e2) connected to the second node (BLB).

5. Memory circuit (Dl) according to any one of claims 1 to 4 wherein the current source (GC) is configured to inject a read current (Iread) having an amplitude greater than rap+rqffs2 and less than rp*rqffs2; R0FF S2 being the resistance of the second selector (S2) when it is in the blocking state.

6. Memory circuit (Dl) according to any one of claims 1 to 5 wherein the current source (GC) is configured to inject a read current (Iread) having an amplitude greater than vtk; ROFFSi Roff siting the resistance of the first selector (SI) when it is in the blocking state.

7. Memory circuit (Dl) according to any one of claims 1 to 6 wherein the current source (GC) is configured to inject a read current (Iread) having an amplitude greater than vtk and then increase the amplitude of the read current (Iread) Roffsi until it reaches a value greater than v; R0FFSi R AP ROFFS2 th being the resistance of the first selector (SI) when it is in the blocking state; ROff,s2 being the resistance of the second selector (S2) when it is in the blocking state.

8. Memory circuit (Dl) according to any one of claims 1 to 7 wherein: - the first nodes (RBL) of the memory cells (CM) belonging to the same column of the memory matrix (Ml) are interconnected via a first conductive line (Li >0 ; Lu) intended to propagate the first associated control voltage (VRBL0, VRBLi); - the second nodes (BLB) of the memory cells (CM) belonging to the same row of the memory matrix (Ml) are interconnected via a second conductive line (L2 ,0 ; L2 3) intended to propagate the second associated control voltage (VBLBo, VBLBi); ​​- the third nodes (BL) of the memory cells (CM) belonging to the same row of the memory matrix (Ml) are interconnected via a third conductive line (L3 o ; L3 i) intended to propagate the read current (Iread).

9. Memory circuit (Dl) according to claim 8 further comprising control means (CONT) configured to perform a read operation of a selected memory cell (CM) of the matrix (Ml) by connecting its first node (RBL) and its second node (BLB) to electrical ground (GND); and by applying to the unselected memory cells a first non-zero control voltage (VRBL) lower than the predetermined threshold voltage V*.

10. Memory circuit (Dl) according to any one of claims 1 to 7 wherein: - the first nodes (RBL) of the memory cells (CM) belonging to the same column of the memory matrix (M2) are interconnected via a first conductive line (Li >0 ; Lu) intended to propagate the first associated control voltage (VRBL0, VRBLi); - the second nodes (BLB) of the memory cells (CM) belonging to the same column of the memory matrix (Ml) are interconnected via a second conductive line (L20 ; L24) intended to propagate the second associated control voltage (VBLBo, VBLBi);

11. - the third nodes (BL) of the memory cells (CM) belonging to the same row of the memory matrix (Ml) are interconnected via a third conductive line (L3 >0 ; L3,i) intended to propagate the read current (Iread). Memory circuit (Dl) according to claim 10 further comprising control means (CONT) configured to perform a read operation of a selected memory cell (CM) of the matrix (M2) by connecting its first node (RBL) and its second node (BLB) to electrical ground; and by applying to the unselected memory cells a first non-zero control voltage (VRBL) less than the predetermined threshold voltage Vth and a second non-zero control voltage (VRBL) less than the predetermined threshold voltage V*.

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