Method for manufacturing an electronic device

Abstract

Method for manufacturing an electronic device. This description relates to a method comprising at least the following steps: - providing a support substrate (310) covered by a separation layer (320), a primer layer (330), and a resin layer (400) having openings (401), - forming, through the openings (401), interconnecting elements (350) by depositing a solder layer (351), a copper post (352), and optionally a gold layer (353), - removing the resin (400) and etching the uncovered portion of the primer layer (330), - assembling the interconnecting elements (350) into an assembly comprising a substrate (100) in which first chips are formed, second chips (200) being assembled to the first chips, and the interconnecting elements (350) being assembled by thermal compression onto conductive pads (110) positioned on the substrate. (100) connected to the first chips,- remove the temporary support (310) and the separation layer (320). Figure for the abbreviation: Fig. 1F,

Description

Title of the invention: Method for manufacturing an electronic device technical field

[0001] This description relates generally to the field of electronic devices and, more particularly, to electronic devices comprising chips assembled by direct bonding onto substrates ('Die to Wafer' or D2W) and their integration onto external devices by a technique of reverse transfer ('Flip-Chip'). Previous technique

[0002] In a heterogeneous D2W ('Die-to-Wafer') integration, the active face of an upper chip is assembled by hybrid bonding to the active face of a lower chip formed in a substrate. In order to assemble these devices onto an external element, such as a printed circuit board, using a flip-chip technique, it is necessary to be able to form interconnecting elements (solder bumps or 'solder bumps') on connection pads arranged on the substrate and connected to the lower chip.

[0003] To have the highest possible density of interconnecting elements, pillars are preferred to weld balls formed by projection ('bail jetting').

[0004] The copper pillars are traditionally formed by implementing a photolithography process followed by an electrodeposition process. For example, the process for forming the pillars may include the steps of: - to provide an assembly including the substrate in which the lower chips are formed and assembled by hybrid bonding to the upper chips, - form a Ti or TiCu primer layer on the connection pads positioned on the substrate, - to form a photosensitive resin having openings opposite the connection points, - Electrodeposit copper pillars onto the primer layer through the openings in the photosensitive resin, then deposit an alloy, for example SnAgCu (SAC), - remove the resin.

[0005] Instead of resin, it is also possible to deposit a layer of polyimide which will then be stored.

[0006] However, the presence of the hybridized upper chips creates a topography (typically 20 to 30 pm) that prevents the formation of pillars less than 500 pm the edges of the upper chips, which severely limits the interconnection density that can be achieved on an external element. The topography is also a problem for the formation of solder bumps. Summary of the invention

[0007] There is a need for electronic components comprising a substrate in which a chip is formed and on which another chip is mounted, for example by means of a die-to-wafer (D2W) bonding process, the electronic components being able to be assembled with high density to external elements, typically printed circuits, by a flip chip technique.

[0008] This object is achieved by a process for manufacturing electronic devices comprising the following steps: a) on a temporary substrate comprising a support substrate successively covered by a separation layer and a primer layer, form a resin layer having openings, b) successively deposit through the openings in the resin layer: a layer of solder, a copper pillar, and possibly a gold layer, thereby forming interconnecting elements, c) remove the resin, and etch the portion of the primer layer not covered by the interconnecting elements, d) assemble the interconnecting elements into an assembly comprising a substrate in which first chips are formed, second chips being assembled to the first chips, for example by hybrid bonding, the interconnecting elements being assembled by thermocompression onto conductive pads positioned on the substrate and connected to the first chips, e) remove the temporary support and the separation layer, f) preferably, implement a heat treatment to melt the brazing layer and the primer layer and form brazing pads.

[0009] According to one embodiment, the temporary support is made of glass or metal and / or the separating layer is made of an adhesive material sensitive to temperature or ultraviolet radiation.

[0010] According to one embodiment, the interconnecting elements are positioned less than 250pm, preferably less than 100pm, from the edge of the second chips.

[0011] According to one embodiment, the thermocompression step is carried out in the presence of ultrasound.

[0012] According to one embodiment, after step f), the process includes a step in which the substrate is cut to form individual electronic devices.

[0013] This object is achieved by an assembly comprising a substrate in which first chips are formed, second chips being assembled to the first chips, for example by hybrid bonding, interconnecting elements being assembled on conductive areas positioned on the substrate and connected to the first chips, by means of a thermo-compressed bond, for example a copper-copper bond or a copper-gold bond, the interconnecting elements comprising successively from the thermo-compressed bond: optionally a gold layer, a copper pillar and a solder pad, the interconnecting elements being positioned at less than 250 pm, preferably at less than 100 pm, and even more preferably at less than 50 pm, from the edge of the second chips.

[0014] This object is also reached by an electronic device comprising a substrate in which a first chip is formed, a second chip being assembled to the first chip, for example by hybrid bonding, interconnecting elements being assembled on conductive pads positioned on the substrate and connected to the first chip, by means of a thermo-compressed bond, for example a copper-copper bond or a copper-gold bond, the interconnecting elements comprising successively from the thermo-compressed bond: optionally a gold layer, a copper pillar and a solder pad, the interconnecting elements being positioned at less than 250 pm, preferably at less than 100 pm, and even more preferably at less than 50 pm, from the edge of the second chips.

[0015] According to a particular embodiment, the height of the interconnecting elements is between 60 and 80 pm and the diameter of the interconnecting elements is between 30 and 50 pm, preferably between 40 and 50 pm.

[0016] This object is also reached by an assembly comprising a device as defined above and an external device, such as a printed circuit board or a laminated substrate, comprising connection areas, the interconnecting elements being assembled on the connection areas.

[0017] This object is also achieved by a manufacturing process for an assembly as defined above, the process comprising a step in which the interconnecting elements are assembled on the connection pads of the external device, for example during a soldering step. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D], [Fig.1E], [Fig.1F], [Fig.1G], [Fig.1H] and [Fig.II] schematically represent different stages of a process for D2W type electronic devices on a substrate scale according to a particular embodiment;

[0020] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H and Fig. 2I schematically represent different stages of a manufacturing process for D2W type electronic devices on a substrate scale according to a particular embodiment;

[0021] [Fig.3] and [Fig.4] are schematic representations, in side view and in cutting, of different assemblies comprising an electronic device and a printed circuit board, according to different particular embodiments.

[0022] The different elements in the figures are not necessarily represented at a uniform scale to make them more legible. Description of the implementation methods

[0023] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0024] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0025] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0026] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures in a normal position of use.

[0027] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean at 10%, preferably at 5%.

[0028] We will now describe in detail the manufacturing process for interconnecting electronic devices, with reference to Figures IA to II and 2A to 21.

[0029] The process is described for the fabrication of electronic devices on the scale of a substrate ('wafer'). However, it could be implemented on the scale of individual electronic devices.

[0030] The process for manufacturing electronic devices 1000 comprises the following steps: a) on a temporary substrate 300 comprising a support substrate 310 successively covered by a separation layer 320, preferably of an adhesive material, and by a primer layer 330, form a resin layer 400 having openings 401 (Figures IA, IB and 2A, 2B), b) form, on the primer layer 330, interconnecting elements 350, by successively depositing through the openings 401 of the resin layer 400, a brazing alloy layer 351, a copper pillar 352, and optionally a gold layer 353 (Figures IC and 2C), c) remove the resin 400, and etch the part of the primer layer 330 not covered by the interconnecting elements 350 (figures 1D, 1E and 1D, 1E), d) assemble the interconnecting elements 350 into an assembly comprising a substrate 100 in which first chips are formed, second chips 200 being assembled to the first chips, for example by hybrid bonding, the interconnecting elements 350 being assembled by thermocompression on conductive pads 110 positioned on the substrate 100 and connected to the first chips (Figures 1F, IG and 2F, 2G), e) remove the support substrate 310 and the separation layer 320 (Figures 1H, 2H), for example by applying heat treatment or ultraviolet radiation so as to reduce the adhesive properties of the separation layer 320, f) preferably, implement a heat treatment to melt the solder layer 351 and the primer layer 330 and form solder pads 354 (Figures II and 21).

[0031] The interconnecting elements 350 of the electronic devices 1000 are, in Initially formed on a temporary substrate 300, they are then transferred to the connection pads 110 of the substrate 100, where they are assembled by thermocompression. During the thermocompression step, thermocompressed copper-copper or thermocompressed copper-gold bonds are formed, thus ensuring the mechanical strength of the assembly.

[0032] The resulting interconnections are coplanar.

[0033] The temporary substrate 300 provided in step a) comprises a support substrate 310 covered successively by a separation layer 320 and by a primer layer 330.

[0034] The support substrate 310 is, for example, made of glass or metal.

[0035] The separating layer 320 is, for example, made of a temperature-sensitive or ultraviolet-sensitive adhesive material. Temperature-sensitive or ultraviolet-sensitive means that when heat treatment or ultraviolet radiation is applied to the adhesive material, its adhesive properties decrease, thus allowing it to be separated from the elements to which it was previously attached. Preferably, it is an ultraviolet-sensitive adhesive material.

[0036] A seed layer 330 (also called a germination layer or 'seed layer' in Anglo-Saxon terms) covers the separation layer 320. The seed layer 330 is electrically conductive and allows the pillars 350 to grow by electrolytic deposition. The seed layer is made of a material chosen so that it can be dissolved in the brazing alloy. The seed layer 310 is, for example, made of TiCu.

[0037] In step a), a resin layer 400 having openings 401 is formed on the temporary substrate 300. The resin is, for example, a photoresist. Conventional photolithography techniques can be used to form the resin layer 400 having openings 401.

[0038] The positioning of the openings 401 of the resin layer 400 is chosen so that, when transferring the interconnecting elements 350, they are positioned opposite the conductive areas 110 of the substrate 100.

[0039] The height of the resin layer 400 is preferably greater than the desired height of the interconnecting elements 350. The upper part 151 of the interconnecting elements 350 is thus well defined. The surface area of ​​the openings 401 corresponds to the surface area of ​​the interconnecting elements 350.

[0040] During step b), the interconnecting elements are formed in the openings 401 of the resin 400. The interconnecting elements 350 are formed by successively depositing on the primer layer 330, by electrolytic growth: a layer of a brazing alloy 351, a copper pillar 352, and optionally a gold layer 353.

[0041] The layer of a brazing alloy 351 may be tin or a tin-based alloy, for example an SnAgCu alloy (denoted SAC). The layer 351 has, for example, a thickness of between 10 and 40 µm.

[0042] Copper pillars 352 have, for example, a height between 20 and 60 pm.

[0043] The 353 gold layer has, for example, a thickness of between 1 and 5 pm.

[0044] The copper pillars 352 or the assembly formed by the gold layer 353 and the copper pillars 352 have a height greater than the height of the second chips 200. They have, for example, a height greater than 50pm.

[0045] The interconnecting elements 350 are preferably circular. They may have a diameter between 30 and 50 pm, for example a diameter of 40 pm.

[0046] The dimensions of the interconnecting elements 350 can be adapted according to the pitch size and / or the desired density.

[0047] During step c), the resin 400 is removed (figures 1D, 2D).

[0048] The primer layer 330 not covered by the interconnecting elements 350 is then removed (Figures 1E, 2E). It can be removed by an etching step.

[0049] In step d), the interconnecting elements 350 are assembled into a set comprising, on the one hand, the substrate 100 in which the plurality of first chips (or lower chips) are formed and, on the other hand, the plurality of second chips 200 (or upper chips) (Figures 1F and 2F). The second chips are arranged opposite the first chips and are connected to each other by connecting pads 120, 210.

[0050] The second chips 200 are assembled to the first chips by a die-to-wafer (D2W) technique, in which the first chips are assembled to the second chips by hybrid bonding. A low chip-to-chip impedance is obtained.

[0051] The substrate 100 comprises a first face 101 and a second face 102. The connection pads 120 of the first chips are positioned on the first face 101 of the substrate 100. Connection pads 110, connected to the first chips, are also positioned on the first face 101 of the substrate 100. They are used to connect the first chips to an external element 500.

[0052] The second chips 200 comprise a first face 201 (front face) and a second face 202 (rear face). The connection pads 210 are positioned on the first face 201 of the second chips 200.

[0053] The second 200 chips have a thickness, for example, less than 60 pm, for example less than or equal to 30 pm (for example between 20 and 30 pm).

[0054] This step of assembling the interconnection elements 350 onto the connection pads 110 of the substrate 100 is carried out by thermocompression (figures 1F, 2F).

[0055] Thermocompression is, for example, carried out in the presence of ultrasound. This makes it possible to reduce the temperature and / or pressure during this step.

[0056] During the thermocompression step, the temperature is, for example, between 90 and 170 °C. The temperature is, for example, 150 °C. The temperature is chosen so as not to melt the other materials, and in particular, the brazing alloy.

[0057] The pressure is, for example, between 0.2 N and 0.4 N per interconnecting element 350.

[0058] At the end of the thermocompression step, thermocompressed links are formed between the connection areas 110 and the interconnecting elements 350.

[0059] Thermocompressed bonds are obtained by atomic diffusion of the atoms present at the interfaces. Thermocompressed bonds form solid and durable joints without the need for glue or solvent.

[0060] When the copper pillar 352 is covered by the gold layer 353, the thermocompressed bond is a copper-gold bond ([Fig.lG]).

[0061] When the copper pillar 352 is not covered by the gold layer 353, the thermocompressed bond is a copper-copper bond ([Fig.2G]).

[0062] The thermo-compressed bond does not include any element that is classically found in a primer layer (for example, it is devoid of titanium) since the pillars are manufactured from their free end to their base, then assembled to the conductive areas 110 of the substrate 100, unlike prior art processes in which the pillars are manufactured on the conductive areas from their base (as shown in the prior art).

[0063] The resulting interconnection elements 350 are coplanar. Their upper faces are at the same height as the first face 101 of the substrate 100.

[0064] In step e), the support substrate 310 and the separation layer 320 are removed (Figures 1H, 2H). The separation step is carried out, for example, by applying ultraviolet radiation or heat treatment to the separation layer 320 in order to reduce its adhesive properties.

[0065] This gives us an assembly comprising a substrate 100 in which first chips are formed, second chips 200 being assembled to the first chips, for example by hybrid bonding.

[0066] The interconnecting elements are assembled on conductive pads 110 positioned on the substrate 100 and connected to the first chips, by means of a thermo-compressed copper-copper or copper-gold bond.

[0067] The interconnecting elements can be positioned less than 250 pm, preferably less than 100 pm, and even more preferably less than 50 pm, from the edge of the second chips 200. They are, for example, at a distance of 30 pm from the edges of the second chips 200.

[0068] At the end of step e), the thermo-compressed interconnecting elements 350 comprise successively from the thermo-compressed link: optionally a gold layer 353, a copper pillar 352, a brazing layer 351 and a starter layer 330.

[0069] Step f) called reflow allows the brazing layer 351 and the primer layer 330 to melt to form brazing pads 354 having their final shape for assembly with the external element 500.

[0070] At the end of step f), the thermo-compressed interconnecting elements comprise successively from the thermo-compressed link: optionally a gold layer 353, a copper pillar 352, a brazing layer 353 and a brazing pad 354.

[0071] An intermetallic layer, resulting from diffusion between layers of different materials, may possibly be present depending on the nature of the layers involved.

[0072] After these various steps have been carried out, a cutting step of the substrate 100 can be performed to form individual electronic devices 1000. The cutting step can be carried out using a saw. This step is not shown in the figures since, for the sake of clarity, only a first chip and a second chip are shown in the figures.

[0073] Each electronic device 1000 comprising at least a first chip and a second chip as well as interconnecting elements 350.

[0074] Such a device can then be assembled with an external element 500, such as a printed circuit board (PCB) or a laminated substrate (Figures 3 and 4).

[0075] It can be assembled by the 'bumping' welding ball technique.

[0076] In particular, the method for assembling the device to an external element 500 includes a step in which the interconnecting elements 350 are aligned and brought into contact with the connection pads 510 of the device 500, and a step, for example, of brazing, in which the interconnecting elements are fixed to the connection pads 510. Brazing ensures electrical and mechanical contact between the device and the external element. It can be carried out either by adding additional solder paste or with a brazing flux that deoxidizes and holds the device during the reflow step of the brazing pads 354. The assembly step can be carried out at a temperature between 230°C and 280°C, for example, at 260°C.

[0077] An electrically insulating polymer layer ('underfill') can then be positioned between the external element 500 and the electronic device 1000. This underfill layer is, for example, an epoxy layer. It is injected after the electronic device 1000 has been transferred onto the external element 500 by capillary action.

[0078] A molding step can also then be carried out to form a housing around the second chip 200.

[0079] The electronic device can be an analog memory device. It can be used in systems requiring a large number of inputs / outputs (I / O). It is particularly relevant to the automotive field. (particularly for a Microcontroller Unit (or MCU for Microcontroller Unit)) or for personal objects ('consumer').

[0080] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0081] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing electronic devices (1000) comprising the following steps: a) on a temporary substrate (300) comprising a support substrate (310) successively covered by a separation layer (320) and by a primer layer (330), forming a resin layer (400) having openings (401), b) successively depositing through the openings (401) of the resin layer (400): a solder layer (351), a copper pillar (352), and optionally a gold layer (353), thereby forming interconnecting elements (350), c) removing the resin (400), and etching the portion of the primer layer (330) not covered by the interconnecting elements, d) assembling the interconnecting elements (350) into an assembly comprising a substrate (100) in which first chips are formed, second chips (200) being assembled to early chips, for example by hybrid bonding,the interconnecting elements (350) being assembled by thermocompression onto conductive pads (110) positioned on the substrate (100) and connected to the first chips, e) remove the support substrate (310) and the separation layer (320), f) preferably, implement a heat treatment to melt the solder layer (351) and the primer layer (330) and form solder pads (354).

2. Method according to the preceding claim, wherein the support substrate (310) is made of glass or metal and / or wherein the separating layer (320) is made of a temperature-sensitive or ultraviolet-sensitive adhesive material.

3. A method according to any one of the preceding claims, wherein the interconnecting elements (350) are positioned less than 250pm, preferably less than 100pm, from the edge of the second chips (200).

4. A method according to any one of the preceding claims, wherein the thermocompression step is carried out in the presence of ultrasound.

5. A method according to any one of the preceding claims, wherein, after step f), the method comprises a step during which the substrate (100) is cut to form individual electronic devices (1000).

6. Assembly comprising a substrate (100) in which first chips are formed, second chips (200) being assembled to the first chips, for example by hybrid bonding, interconnecting elements (350) being assembled on conductive pads (110) positioned on the substrate (100) and connected to the first chips, by means of a thermo-compressed bond, for example a copper-copper bond or a copper-gold bond, the interconnecting elements (350) comprising successively from the thermo-compressed bond: optionally a gold layer (353), a copper pillar (352) and a solder pad (354), the interconnecting elements (350) being positioned at less than 250 pm, preferably at less than 100 pm, and even more preferably at less than 50 pm, from the edge of the second chips (200).

7. Electronic device (1000) comprising a substrate (100) in which a first chip is formed, a second chip (200) being assembled to the first chip, for example by hybrid bonding, interconnecting elements (350) being assembled on conductive pads (110) positioned on the substrate (100) and connected to the first chip, by means of a heat-compressed bond, for example a copper-copper bond or a copper-gold bond, the interconnecting elements (350) comprising successively from the heat-compressed bond: optionally a gold layer (353), a copper pillar (352) and a solder pad (354), the interconnecting elements (350) being positioned at less than 250 pm, preferably at less than 100 pm, and even more preferably at less than 50 pm, from the edge of the second chips.

8. Device according to claim 7, wherein the height of the interconnecting elements (350) is between 60 and 80 pm and the diameter of the interconnecting elements (350) is between 30 and 50 pm, preferably between 40 and 50 pm.

9. Assembly comprising an electronic device (1000) as defined in any one of claims 7 and 8, and an external device (500), such as a printed circuit board or a laminated substrate, comprising connection pads (510), the interconnecting elements (350) being assembled on the connection pads (510).

10. Method of manufacturing an assembly as defined in claim 9, the method comprising a step in which the interconnecting elements (350) are assembled on the connection ranges (510) of the external device (500), for example during a brazing step.

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