Integrated circuit package and manufacturing process

Abstract

The adhesive is contained within the package (BT) between the rear face (12) of the chip (1) and the front face (20) of the substrate (2) during the placement and fixation of the chip (1) onto the substrate (2). In this respect, the rear face of the chip has first blind holes (13) and the front face of the substrate has second blind holes (27) defining recesses for the adhesive. (See Figure 5 for abbreviations)

Description

Title of the invention: Integrated circuit package and manufacturing method

[0001] Some embodiments and implementations relate to the field of packaging of integrated circuits, and more particularly the structure and manufacture of integrated circuit packages, for example but not exclusively optical packages.

[0002] The packages classically include a support substrate on which at least one electronic chip is mounted.

[0003] This chip typically has on its front face contact areas (“pad” in English) which are electrically connected to solder areas (“known to those skilled in the art under the Anglo-Saxon name “bond fingers”) arranged on the front face of the support substrate by electrically conductive connecting wires (“this operation is known to those skilled in the art under the Anglo-Saxon name “wire bonding”).

[0004] However, during the operation of mounting the chip on the support substrate, it is glued by means of a layer of glue.

[0005] However, when the chip is pressed onto the layer of glue, the latter may in some cases overflow onto a part of at least some of the soldering areas of the carrier substrate and / or go up along the side walls of the chip to cover at least partially at least some of the contact areas of the chip.

[0006] This results in contamination of the glue-covered parts, leading to a welding defect in the connecting wires and therefore to a malfunction of the integrated circuit.

[0007] There is therefore a need to remedy this drawback.

[0008] According to one embodiment, it is proposed to contain the glue between the rear face of the chip and the front face of the carrier substrate during the placement and fixing of the chip on the carrier substrate.

[0009] According to one aspect, a housing is proposed comprising an electronic chip having a front face having contact areas (“pads”) and a rear face having several first blind holes distributed on its periphery and opening onto the rear face.

[0010] Although not essential, it is recommended to provide at least four first blind orifices.

[0011] A chip is generally rectangular (possibly with equal sides forming a square).

[0012] In this case, the first four blind holes are preferably arranged near the four corners of the rear face of the electronic chip.

[0013] The housing also includes a carrier substrate having a front face (or mounting face) opposite and at a distance from the rear face of the electronic chip.

[0014] The front face of the carrier substrate has bond fingers and several second blind holes opening onto the front face respectively opposite the first blind holes of the chip.

[0015] When the rear face of the electronic chip has at least four first blind holes, the front face of the carrier substrate has at least four second blind holes.

[0016] The rear face of the chip may include four other first blind holes respectively arranged between the first four blind holes and in this case, the front face of the carrier substrate includes four other second blind holes respectively located opposite the other four first blind holes.

[0017] Each pair of a first blind orifice and a second blind orifice mutually opposite defines a housing.

[0018] The housing then includes in each compartment, a pillar of a first adhesive material, for example a pillar of solidified glue.

[0019] The housing also includes electrically conductive connecting wires between the contact areas of the chip and the solder areas of the substrate.

[0020] The housing further includes an encapsulating material, for example a molding resin, encapsulating the connecting wires and at least partially the electronic chip.

[0021] Part of this coating material is located in the space between the rear face of the chip and the front face of the carrier substrate.

[0022] Thus according to this aspect, the electronic chip is fixed to the substrate by means of the adhesive material pillars.

[0023] And this adhesive material is contained in each housing formed by a pair of a first blind orifice and a second blind orifice.

[0024] There is therefore no contamination of the contact areas and the weld areas, which allows for a correct weld of the connecting wires on the one hand on these contact areas and on the other hand on the weld areas.

[0025] In the case of certain packages, the encapsulating material completely encases the electronic chip.

[0026] On the other hand, this is not the case for an optical package, that is to say a package intended to contain a chip equipped with an optical device that emits and / or receives optical signals.

[0027] Indeed, for such a case, the encapsulating material only partially encases the electronic chip.

[0028] More specifically and according to one embodiment, the optical housing comprises an optically transparent element, for example a glass, located opposite and at a distance from the front face of the chip and fixed to this front face by a bead of a second adhesive material, for example a bead of glue.

[0029] This second adhesive material may be identical or different from the first adhesive material.

[0030] This cord of the second adhesive material defines with the chip and the optically transparent element a cavity which is not filled by the encapsulating material.

[0031] Generally speaking, a person skilled in the art will be able to define the geometric characteristics of the first blind holes and the second blind holes as well as the quantity of first adhesive material in order to obtain adhesive pillars filling these blind holes while leaving a space between the back face of the chip and the front face of the carrier substrate.

[0032] That being said, the second blind orifices can have a depth of 25 micrometers to within 10%.

[0033] In practice the carrier substrate can be of the multilayer type (known to those skilled in the art under the Anglo-Saxon expression "laminate substrate").

[0034] Such a carrier substrate comprises an alternation of metallic layers and electrically insulating layers.

[0035] Metallic tracks formed in the metallic layers and vias between these tracks make it possible to create an interconnection network between the solder areas of the front face (upper face) of the carrier substrate and solder balls arranged on the rear face (lower face) of the carrier substrate and intended to be soldered onto a printed circuit board.

[0036] The upper face of the upper electrically insulating layer of the carrier substrate forming the front face of this carrier substrate and the second blind holes can be provided in the upper electrically insulating layer and have a depth corresponding to the thickness of this upper insulating layer.

[0037] The second blind orifices may have, for example, an opening of 200 micrometers to within 10%.

[0038] The first blind holes (made on the rear face of the chip) may have a depth less than that of the second blind holes, for example a depth of 10 micrometers to within 10%.

[0039] According to one embodiment, each pillar of the first adhesive material protrudes by 20 micrometers to within 10% above the front face of the carrier substrate.

[0040] The space between the rear face of the electronic chip and the front face of the substrate then has this value of 20 micrometers to within 10%.

[0041] According to another aspect, a method for manufacturing a casing is proposed.

[0042] This method includes providing an electronic chip having a front face with contact areas and a rear face.

[0043] a formation on said rear face of several first blind orifices distributed around the periphery of this rear face and opening onto this rear face,

[0044] The method also includes providing a carrier substrate having a front face having an area intended to be opposite the rear face of the chip and soldering areas outside this area.

[0045] This area is a placement area above which the chip is intended to be located.

[0046] The process then comprises a formation at the periphery of said zone of several second blind orifices opening onto the front face.

[0047] The process then includes filling the second blind holes with a first adhesive material in liquid form in an amount that allows for an excess of the first material to overflow above the second blind holes.

[0048] This surplus remains localized in the volume located above each second blind orifice by edge effect and by its surface tension.

[0049] Next, typically right after said filling, the rear face of the chip is placed opposite and at a distance from said area so as to align respectively the first blind holes and the second blind holes and allow the excess of first material to penetrate into the first blind holes.

[0050] The process then includes solidifying the first material, typically by baking at an appropriate temperature, so as to obtain pillars of the first material extending into each pair of a first blind orifice and a second blind orifice and into the space between this first and second blind orifices.

[0051] Then, connecting wires are welded between the contact areas and the weld zones.

[0052] The method then includes coating the connecting wires and at least part of the electronic chip with a coating material which also fits into the space between the back face of the chip and the front face of the carrier substrate.

[0053] According to one embodiment, at least four first blind orifices are formed and at least four second blind orifices are formed.

[0054] According to an embodiment adapted to a rectangular chip, the first four blind holes are formed in the vicinity of the four corners of the rear face of the chip.

[0055] In order to increase the fixation of the chip to the carrier substrate, four additional first blind holes can be formed on the rear face of the chip, respectively arranged between the first four blind holes, and four additional second blind holes can be formed on the front face of the carrier substrate, respectively intended for be located opposite the four other first blind holes when the electronic chip is placed.

[0056] The electronic chip can be completely encapsulated with the encapsulating material.

[0057] Alternatively and according to an embodiment, prior to said coating, an optically transparent element, for example a glass, is fixed in front of and at a distance from the front face of the chip by a bead of a second adhesive material defining with the chip and the optically transparent element a cavity which is not filled by the coating material during the coating.

[0058] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiment and implementation, which is by no means limiting, and the accompanying drawings in which:

[0059] [Fig.l] ;

[0060] [Fig.2] ;

[0061] [Fig.3] ;

[0062] [Fig.4] ;

[0063] [Fig.5] ;

[0064] [Fig.6] ;

[0065] [Fig.7] ;and

[0066] [Fig.8] schematically illustrate methods of implementation and realization of the invention.

[0067] In [Fig.1] and [Fig.2] reference 1 designates an electronic chip.

[0068] Fig. 1 is a cross-sectional view along line II of Fig. 2.

[0069] The electronic chip 1 has a front face 10 having contact areas (pads) 11 and a back face 12.

[0070] The chip also includes an optical device 14 for emitting and / or receiving light signals, mounted on the front face 10 of the chip.

[0071] The rear face 12 has several first blind openings 13 distributed around the periphery of the rear face and opening onto this rear face.

[0072] In this embodiment, four first blind orifices 13 are provided.

[0073] A chip is generally rectangular (possibly with equal sides forming a square).

[0074] In this case the first four blind holes 13 are preferably, as illustrated in [Fig.2], located near the four corners of the rear face 12 of the electronic chip.

[0075] As illustrated in [Fig.2], the rear face of the chip may have four other first blind holes 130 respectively arranged between the first four blind holes, for example in the middle of the sides of the rear face 12.

[0076] In figures 3 and 4, reference numeral 2 designates a supporting substrate.

[0077] Fig. 3 is a cross-sectional view along line III-III of Fig. 4.

[0078] The supporting substrate 2 has a front face (upper face or mounting face) 20 and a rear face (lower face) 21 opposite the front face.

[0079] The carrier substrate 2 has on its front face a zone 200 which is a placement zone above which the chip 1 is intended to be located.

[0080] The front face 20 of the carrier substrate has bond fingers 28 outside the placement area 200 and several second blind holes 27, located at the periphery of the placement area 200, opening onto the front face 20 and intended to be respectively opposite the first blind holes 13 of the chip 1.

[0081] When the rear face of the electronic chip has the first four blind holes 13, the front face of the carrier substrate has four second blind holes 27.

[0082] If the rear face of the chip has four other first blind holes 130, the front face of the carrier substrate has four other second blind holes 270 intended to be located respectively opposite the four other first blind holes.

[0083] The carrier substrate 2 is here of the multilayer type (known to those skilled in the art under the Anglo-Saxon expression "laminate substrate").

[0084] Such a carrier substrate comprises an alternation of metallic layers 22, 23 (only two are shown for the sake of simplification) and electrically insulating layers 24, 25, 26.

[0085] Metallic tracks formed in the metallic layers and vias between these tracks make it possible to create an interconnection network between the solder areas 200 of the front face (upper face) of the carrier substrate and solder balls (not shown here) arranged on the rear face (lower face) of the carrier substrate and intended to be soldered onto a printed circuit board.

[0086] The upper face of the upper electrically insulating layer of the carrier substrate forms the front face of this carrier substrate and the second blind holes 27 are here provided in the upper electrically insulating layer 24 and have a depth p2 corresponding to the thickness of this upper insulating layer 24.

[0087] Fig. 5 schematically illustrates a first embodiment of a BT package comprising the chip 1 and the carrier substrate 2 previously described.

[0088] The rear face 12 of the chip and the front face 20 of the substrate are opposite each other, leaving a space 4 between them.

[0089] The first blind holes 13 of the chip are respectively opposite the second blind holes 27 of the carrier substrate.

[0090] Each pair of a first blind orifice 13 and a second blind orifice 27 mutually opposite defines a housing.

[0091] The BT housing then includes in each housing, a pillar 3 of a first adhesive material, for example a pillar of solidified glue.

[0092] Each pillar 3 comprises -a lower part 30 housed in the second corresponding blind orifice 27, - an upper part 30 housed in the first corresponding blind orifice 13, and -an intermediate part 32 between parts 30 and 31 located in the space between the chip and the carrier substrate.

[0093] The BT package also includes electrically conductive connecting wires 9 between the contact areas 11 of the chip and the solder areas 28 of the carrier substrate.

[0094] The electronic chip 1 is fixed to the carrier substrate 2 by means of the adhesive material pillars 3.

[0095] And this adhesive material is contained in each housing formed by a pair of a first blind orifice 13 and a second blind orifice 27 mutually opposite each other.

[0096] There is therefore no contamination of the contact areas 11 and the weld areas 28 by the first adhesive material, which allows a correct weld of the connecting wires 9 to be obtained on the one hand on these contact areas 11 and on the other hand on the weld areas 28.

[0097] The BT housing is here an optical housing comprising an optically transparent element 7, for example a glass, located opposite and at a distance from the front face of the chip on which the optical device 14 is fixed.

[0098] The optically transparent element 7 is fixed to the front face of the chip by a cord 6 of a second adhesive material, for example a cord of glue.

[0099] This second adhesive material may be identical or different from the first adhesive material forming the pillars 3.

[0100] This cord 6 of the second adhesive material defines with the chip 1 and the optically transparent element 7 a cavity 8.

[0101] The BT housing further includes an encapsulation material 5, for example a molding resin, encapsulating the connecting wires 9 and partially the electronic chip 1.

[0102] A portion 52 of this encapsulation material is located in the space between the rear face of the chip and the front face of the carrier substrate.

[0103] Another part 51 of the encapsulating material laterally encases the chip 1, the optically transparent element 4 and the adhesive cord 6.

[0104] The cavity 8 is not filled by the encapsulating material 5.

[0105] For some packages, the encapsulation material completely surrounds the electronic chip.

[0106] This is the case, for example, of the BT1 package shown schematically in [Fig. 6].

[0107] This housing is a non-optical housing.

[0108] In figures 5 and 6, analogous elements or elements having analogous functions have the same references.

[0109] Only the differences between [Fig.5] and [Fig.6] will now be described.

[0110] The front face of chip 1 does not have an optical device and the BT1 package does not have an optically transparent element opposite the front face of chip 1.

[0111] The encapsulating material 5 here comprises an upper part 53 covering the chip 1.

[0112] Generally, a person skilled in the art will be able to define the geometric characteristics of the first blind holes and the second blind holes as well as the quantity of first adhesive material in order to obtain adhesive pillars filling these blind holes while leaving a space between the back face of the chip and the front face of the carrier substrate.

[0113] As an indication, the second blind orifices 27 can have a depth p2 ([Fig.3]) of 25 micrometers to within 10%.

[0114] The second blind orifices 27 can have, for example, an opening d2 ([Fig.2]) of 200 micrometers to within 10%.

[0115] The first blind holes 13 (made on the rear face of the chip) can have a depth pl ([Fig.l]) less than that of the second blind holes, for example a depth pl of 10 micrometers to within 10%.

[0116] Each pillar of the first adhesive material 3 can protrude by 20 micrometers to within 10% above the front face of the carrier substrate, which represents the height of the intermediate part 32 of this pillar.

[0117] The space between the rear face of the electronic chip and the front face of the substrate then has this value of 20 micrometers to within 10%.

[0118] Reference is now made more particularly to figures 7 and 8 to describe a method of implementing a manufacturing process for a case according to the invention.

[0119] This method includes an S70 provision of an electronic chip 1 having a front face having contact areas and a rear face.

[0120] Several first blind orifices 13 are formed (step S71) on said rear face, distributed around the periphery of this rear face and opening onto this rear face,

[0121] The method also includes a provision S72 of a carrier substrate 2 having a front face having a placement area 200 intended to be opposite the rear face of the chip and soldering areas 28 outside this placement area 200.

[0122] The method then comprises a formation S73 at the periphery of said zone 200 of several second blind orifices 27 opening onto the front face.

[0123] The process then includes filling S74 of the second blind holes 27 with a first adhesive material in liquid form in an amount that provides an excess of first material overflowing above the second blind holes 27.

[0124] This first adhesive material can be, for example, the glue marketed under the reference ABLESTIK QMI536 by the company Loctite and the filling of the second blind holes can be carried out conventionally using a syringe.

[0125] The excess glue remains localized in the volume located above each second blind orifice 27 by edge effect and by the surface tension of the glue in the liquid state.

[0126] The next step S75 allows the chip to be fixed to the carrier substrate using the glue pillars 3.

[0127] More specifically, just after said filling of the second blind holes 27, a placement S750 of the rear face of the chip is carried out opposite and at a distance from said placement area 200 of the carrier substrate so as to align respectively the first blind holes 13 and the second blind holes 27 and allow penetration S751 of the excess glue into the first blind holes 13.

[0128] The process then includes a solidification S752 of the first material, typically by baking at an appropriate temperature, for example 150°C for a period of 90 minutes, so as to obtain the pillars 3 of solidified glue extending into each pair of a first blind orifice 13 and a second blind orifice 27 and into the space between this first and second blind orifices.

[0129] At this stage the electronic chip 1 is glued onto the carrier substrate 2 with a space 4 between the chip and the carrier substrate.

[0130] The contact areas 11 and the weld areas 28 are not contaminated by the glue.

[0131] Then an S76 welding of the connecting wires 9 is carried out between the contact areas 11 and the weld areas 28.

[0132] From there, two variants are possible.

[0133] In a first variant, the connecting wires and the electronic chip are completely encapsulated S77 with an encapsulating material, for example a conventional molding resin, which is also inserted into the space 4 between the rear face of the chip and the front face of the carrier substrate, so as to obtain a BT1 package of the type illustrated in [Fig.6].

[0134] In a second variant, prior to said coating, the optically transparent element 7 is fixed (step S78) opposite and at a distance from the front face of the chip by a bead 6 of a second adhesive material defining with the chip and the optically transparent element the cavity 8 which is not filled by the coating material, for example the molding resin, during the coating S79.

[0135] In this example the second adhesive material can be the glue used for the formation of pillars 3.

Claims

Demands

1. Housing, comprising -an electronic chip (1) having a front face (10) having contact areas (11) and a rear face (12) having several first blind holes (13) distributed around its periphery and opening onto the rear face, -a carrier substrate (2) having a front face (20) opposite and at a distance from the rear face (12) of the chip and having solder areas (28) and several second blind holes (27) opening onto the front face respectively opposite the first blind holes (13) of the chip, each pair of a first blind hole (13) and a second blind hole (27) mutually opposite each other defining a housing, -a pillar (3) of a first adhesive material in each housing, -connecting wires (9) between the contact areas (11) and the solder areas (28), -a material encapsulation (5) encapsulating the connecting wires (9) and at least partially the electronic chip,a portion (52) of this encapsulating material being located in the space (4) between the rear face (12) of the chip and the front face (20) of the carrier substrate.

2. Housing according to claim 1, wherein the rear face of the electronic chip has at least four first blind holes (13) and the front face of the carrier substrate has at least four second blind holes (27).

3. Housing according to claim 2, wherein the chip is rectangular and the first four blind holes (13) are arranged in the vicinity of the four corners of the rear face (12) of the chip.

4. Housing according to claim 2 or 3, wherein the rear face of the chip has four other first blind holes (130) respectively disposed between the first four blind holes (13) and the front face of the carrier substrate has four other second blind holes (270) respectively located opposite the other four first blind holes (130).

5. Housing according to any one of the preceding claims, in which the encapsulating material (5) totally encases the electronic chip.

6. Housing according to any one of claims 1 to 4, wherein the housing is an optical housing (BT) comprising an optically transparent (7) located opposite and at a distance from the front face of the chip and fixed to this front face by a bead (6) of a second adhesive material defining with the chip and the optically transparent element a cavity (8) which is not filled by the encapsulation material (5).

7. Housing according to any one of the preceding claims, wherein the second blind orifices (27) have a depth of 25 micrometers to within 10%.

8. Housing according to any one of the preceding claims, wherein the carrier substrate (2) is of the multilayer type comprising an alternation of metallic layers and electrically insulating layers, the upper face of the upper electrically insulating layer (24) forming the front face (20) of the carrier substrate and the second blind holes (27) are provided in the upper electrically insulating layer (24) and have a depth corresponding to the thickness of this upper insulating layer.

9. Housing according to any one of the preceding claims, wherein the second blind orifices (27) have an opening of 200 micrometers to within 10%.

10. Housing according to any one of the preceding claims, wherein the first blind orifices (13) have a depth of 10 micrometers to within 10%.

11. Housing according to any one of the preceding claims, wherein each pillar (3) of the first adhesive material protrudes 20 micrometers to within 10% above the front face of the carrier substrate.

12. A method for manufacturing a housing, comprising: - a provision (S70) of an electronic chip having a front face with contact areas and a rear face; - a formation (S71) on said rear face of several first blind holes distributed around the periphery of this rear face and opening onto this rear face; - a provision (S72) of a carrier substrate having a front face having an area (200) intended to be opposite the rear face of the chip and soldering areas outside this area (200); - a formation (S73) at the periphery of said area of ​​several second blind holes opening onto the front face; - a filling (S74) of the second blind holes with a first adhesive material in the liquid state in an amount sufficient to obtain an excess of first material overflowing above the second blind holes, -a placement (S750) of the back face of the chip opposite and away from said area so as to align respectively the first blind holes and the second blind holes and allow penetration (S751) of the excess of first material into the first blind holes, and a solidification (S752) of the first material so as to obtain pillars of the first material extending into each pair of a first blind hole and a second blind hole and into the space between this first and this second blind holes, a soldering (S76) of connecting wires between the contact areas and the soldering areas, -an encapsulation (S77; S79) of the connecting wires and of at least a part of the electronic chip with an encapsulation material further inserted into the space between the back face of the chip and the front face of the carrier substrate.

13. A method according to claim 12, wherein at least four first blind orifices (13) are formed and at least four second blind orifices (27) are formed.

14. Method according to claim 13, wherein the chip is rectangular and the first four blind holes (13) are formed in the vicinity of the four corners of the rear face of the chip.

15. A method according to claim 14, wherein four other first blind holes (130) are formed on the rear face of the chip, respectively arranged between the first four blind holes, and four other second blind holes (270) are formed on the front face of the carrier substrate, respectively intended to be located opposite the other four first blind holes when the electronic chip is placed.

16. A method according to any one of claims 12 to 15, wherein the electronic chip (S77) is totally coated with the coating material.

17. A method according to any one of claims 12 to 15, wherein prior to said coating (S79), an optically transparent element (S78) is fixed opposite and at a distance from the front face of the chip by a bead of a second adhesive material defining with the chip and the optically transparent element a cavity that is not filled by the encapsulation material during encapsulation.