Method for manufacturing electronic chips with passivated sidewalls

Abstract

Method for manufacturing electronic chips with passivated sidewalls. Method for manufacturing electronic chips (100) with passivated sidewalls from a semiconductor substrate (110) in which chips (100) are formed, a first face (111) of the substrate (110) being covered by connection pads (107), the method comprising the following steps: - optionally forming connection pads (117) on the connection pads (107), - forming trenches (120) between the chips (100), - depositing an insulating material (121) so as to cover the substrate (110) and fill the trenches (120), - thinning the insulating material (121) until the connection pads (117) or the connection pads (107) are accessible, - separating the chips (100) by cutting at least the insulating material (121), thereby producing chips (100) having sidewalls (113) partially covered by the insulating material (121) are obtained. Figure for the abbreviation: Fig. 1F

Description

Title of the invention: Method for manufacturing electronic chips with passivated sidewalls. Technical field

[0001] This description relates to the field of CSP ('Chip-Scale Package') type chips. It relates more particularly to a method for manufacturing bare chips ("bare dice" or "bare chip"). Previous technique

[0002] Bare chips comprise a substrate, made of a semiconductor-conductive material, in which electronic circuits have been fabricated. The substrate is covered by connection pads to allow the chip to be assembled, for example, with a printed circuit board. During chip assembly, the connection pads are soldered or brazed to traces or metallic elements of the printed circuit board. However, during assembly, the solder sometimes migrates up the sides of the chip. Since the sides of the chip are made of a semiconductor material, this can lead to a loss of electrical performance (short circuit, leakage current, etc.). Therefore, there is a need to prevent such phenomena.

[0003] Such chips are particularly interesting in many industrial fields, for example, in the automotive field. Summary of the invention

[0004] There is a need to improve at least in part certain aspects of known processes for manufacturing electronic chips.

[0005] This goal is achieved by a method for manufacturing an electronic chip with passivated sides from a semiconductor substrate in which chips are formed, a first face of the substrate being covered by connection areas, the method comprising the following steps: - preferably, create connection pads on the connection pads, - create trenches between the chips, - to lay down an insulating material to cover the substrate and fill the trenches, - Thin the insulating material until the connection points or connection areas are accessible, - separate the chips by cutting at least the insulating material and the substrate through the trenches, thereby obtaining chips with sides partially covered by the insulating material.

[0006] According to a particular embodiment, trenches are formed by partially cutting the substrate from the first face, the depth of the trenches preferably being between 10 and 80% of the thickness of the chip substrate.

[0007] According to a particular embodiment, the width of the trenches is between 20 and 80 pm.

[0008] According to a particular embodiment, the insulating material comprises a polymer or a resin, preferably an epoxy or phenolic resin, and electrically insulating charges, for example alumina or silica particles.

[0009] This goal is also achieved by an electronic chip with passivated sides comprising a semiconductor substrate, having a first face, a second face and sides, the first face being covered by connection pads, connection pads being able to be positioned on the connection pads, a layer of insulating material covering the first face of the substrate, between the connection pads or between the connection pads, and a part of the sides from the first face of the substrate.

[0010] According to a particular embodiment, the insulating material comprises a polymer or a resin, preferably an epoxy or phenolic resin, and electrically insulating charges, for example alumina or silica particles.

[0011] According to a particular embodiment, the insulating material covers between 10 and 80%, preferably between 50 and 80%, of the height of the sides of the chip.

[0012] According to a particular embodiment, the layer of insulating material has a thickness of less than 50 pm, for example a thickness between 10 and 30 pm.

[0013] This goal is also achieved by a method of assembling an electronic chip as defined above with an external device, such as a printed circuit board, the method comprising the following steps: - position a soldering material between connection elements of the external device and either the connection pads or the connection areas, positioned on the first face of the chip, - solder the soldering material.

[0014] This goal is also achieved by an assembly comprising an electronic chip as defined above, and an external device, such as a printed circuit board, the connection pads or connection areas of the electronic chip being brazed onto the connection elements of the external device by a brazing material.

[0015] This goal is also achieved by the use of such an electronic chip in an automobile, for example in an advanced driver assistance system, in personal electronics, in communication equipment, such as a computer, a mobile phone ('smartphone'), a connected object (LoT) or one of their peripherals.

[0016] This goal is also achieved by an automobile, a communication device, such as a computer, a mobile phone ('smartphone'), a connected object (loT) or one of their peripherals comprising such an electronic chip. Brief description of the drawings

[0017] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0018] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D], [Fig.1E] and [Fig.1F] represent cross-sectional views illustrating steps in a manufacturing process for an electronic chip with passivated sidewalls according to a particular embodiment;

[0019] [Fig.2] schematically represents an electronic chip with a passivated side, in side view and in section, according to a particular embodiment;

[0020] [Fig.3] schematically represents a passivated sidewall electronic chip in three dimensions, according to a particular embodiment.

[0021] The figures are not necessarily represented at a uniform scale for better understanding. Description of the implementation methods

[0022] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0023] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0024] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0025] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0026] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0027] By between X and Y, we mean that the bounds X and Y are included.

[0028] We will now describe in more detail the manufacturing process of an electronic chip (“bare die” or “bare chip”) with passivated sidewalls by referring to figures IA to 1F.

[0029] The process comprises the following steps: a) provide a semiconductor substrate 110 in which chips 100 are formed and of which a first face 111 is covered by connection areas 107 (figure IA), b) optionally, form connection pads 117 on the connection pads 107 (figure IB), c) form trenches 120 in the substrate 110 between the chips 100, the depth of the trenches 120 being less than the thickness of the substrate 110 of the manufactured chip 100 (figure IC), d) deposit a layer of insulating material 121 on the first face 111 of the substrate 110 so as to cover the connection areas 107, and possibly the connection pads 117, and to fill the trenches 120 (figure 1D), e) thin the insulating material layer 121 to make accessible part of the connection pads 117 or part of the connection areas 107 (Figure 1E), f) optionally, carry out a thinning step of the substrate 110 on the rear face 112, g) separate the chips 100 by cutting the substrate 110 between the chips through the layer of insulating material 121, and more particularly by cutting the substrate 110 in the middle of the trenches 120 (figure 1F).

[0030] With such a process, the sides 113 of the resulting chips 100 are partially passivated by means of an insulating layer 121. Potential contamination, due to faulty assembly with an external device, is thus avoided, and there is no degradation of electrical performance. The sides 113 are not completely passivated. The passivation depth of the sides 113 of the resulting chip 100 is adjustable.

[0031] In step a), the fabrication of the discrete component(s) and / or integrated circuit(s) is completed. The chips 100 are formed in the same substrate 110, and have not yet been individualized.

[0032] The substrate 110 comprises a first face 111 (upper face or front face or active face) and a second face 112 (lower face or rear face). The two faces 111 and 112 are parallel to each other. They are connected to each other by lateral walls.

[0033] The substrate 110 is, for example, a semiconductor substrate, for example made of silicon. It can also be made of GaN or SiC.

[0034] The substrate 110 has, for example, a thickness between 100 and 900 pm, preferably between 300 and 900 pm, for example a thickness of about 725 pm.

[0035] One or more connection areas 107 (also called electrical contacts) are formed on the upper surface 111 of the substrate 110 of the electronic chip 100 and allow it to be connected to other elements (chips or printed circuit boards, for example). Preferably, there are at least two connection areas. There could be 6, 8, or 10, or even more than 10, connection areas 107. The number of connection areas 107 will be chosen according to the requirement.

[0036] The electrical connection pads 107 are, for example, at a distance of 10 to 30 pm from the side wall of the chip. The electrical connection pads 107 can be positioned on the upper face 111 of the chip 100 or be flush with the upper face 111 (i.e., level with the upper face 111 of the chip 100).

[0037] The electrical connection pads 107 are also called "UBMs" (for the English expression "Under Bump Metallization" or "pads"). The electrical connection pads 107 are made of a conductive material. The electrical connection pads 107 advantageously comprise at least one of the following elements: gold, titanium, nickel, copper, or tungsten. Preferably, they comprise gold.

[0038] The chip 100 may comprise one or more discrete components. The discrete component(s) may be chosen, for example, from transistors, diodes, filters, thyristors, triacs, etc. The chip 100 may comprise one or more electronic circuits. The chip 100 allows for the implementation of various electronic functions.

[0039] In step b), connecting pads 117 are formed on the connecting pads 107. Step b) is an optional step. The process can be carried out without having performed step b).

[0040] The conductive studs 117 may, in particular, have the shape of a ball (or "bump" in Anglo-Saxon terms). Alternatively, they may be a conductive element having another shape, such as a pillar or a cube.

[0041] The conductive pads 117 are formed from an electrically conductive and "wettable" (i.e., brazable or solderable) material, that is to say, a material on which it is possible to braze. For example, the conductive pads are made of a brazable material generally based on tin, typically SnAgCu.

[0042] The conductive pads 117 are advantageously brazed onto the electrical connection pads 107.

[0043] In step c), the substrate 110 is partially cut between the chips 100 to form trenches 120. The substrate 110 is not cut through its entire thickness. The trenches 120 define the lateral contours 113 of the chips 100. More specifically, the trenches extend from the upper face 111 of the substrate 110.

[0044] They have a depth less than the thickness of the substrate 110. The depth of the trenches 120 is, for example, between 10 and 300 pm, preferably between 20 and 250 pm.

[0045] The depth of the trenches 120 is preferably between 10 and 80%, preferably between 10 and 75% of the thickness of the substrate 110 of the final chip 100. The depth of the trenches 120 is adjustable according to the needs of the application.

[0046] The width of the trenches 120 is, for example, between 20 and 80 pm.

[0047] The bottom of the trenches can be flat or concave.

[0048] This step c) is carried out using a cutting or engraving device. The cutting device is, for example, a mechanical cutting / engraving tool such as a saw, or a laser or plasma engraving tool. The use of a mechanical cutting device, for example, a saw, creates a certain roughness and facilitates the adhesion of the insulating material layer 121 to the sides 113 of the chip. Plasma cutting also creates a surface finish conducive to increased mechanical adhesion.

[0049] The order of steps b) and c) could be reversed.

[0050] In step d), a layer of insulating material 121 is deposited. The insulating material covers the first face 111 of the substrate 110, the connection areas 107 and, where applicable, the connection pads 117. These latter elements are, at the end of step d), arranged within the insulating material. The insulating material also fills the trenches 120.

[0051] The insulating material can be deposited by injection, by squeegee deposition, by spray, by vacuum molding. The insulating material can be liquid or solid, for example in the form of solid granules, in the form of powders or preforms (called "pellets").

[0052] The insulating material is an electrically insulating material. More specifically, the insulating material comprises a base material (polymer or resin) and, preferably, electrically insulating particles. The resin is selected from the group comprising: epoxy resins, phenolic resins, and acrylic resins. The base material may be polyvinylpyrrolidone (PVP), silicone (also called polysiloxane), polyamic acid, tripropylene glycol diacrylate (TPGDA), or an epoxy base. The particles are, for example, oxide particles, and in particular alumina or silica particles.

[0053] Preferably, the resin is a thermosetting resin. Such resins are very stable and resistant to many chemicals.

[0054] The polymerization of the resin is, for example, a UV polymerization step. It can also be carried out by heating or any other polymerization method chosen according to the nature of the material used.

[0055] An annealing step can be carried out after step d).

[0056] In step e), the insulating material 121 is thinned from the front face. It is thinned until the connection pads 117 are accessible when they were deposited in step b) or until the connection areas 107 are accessible.

[0057] The thinning on the front face, implemented during step d), can be carried out by polishing ('grinding').

[0058] The process may also include a rear-face thinning step (step f)). This step is preferably carried out after step e). For this purpose, the structure is turned over and fixed by its front face 111 to a support. The support is, for example, a strip of adhesive tape. The structure is then thinned from its rear face so that the substrate 110 has its final thickness. The thinning is carried out in such a way as not to thin the substrate 110 all the way to the trenches 120.

[0059] In step g), the chips 100 are separated. This singulation step can be carried out by making a cut through the insulating material 121 and through the substrate 110. The cut line is centered with respect to the trenches 120.

[0060] The cutting device is, for example, a mechanical engraving tool such as a saw, or a laser engraving tool.

[0061] The width of the cut is chosen so as to be less than the width of the cavity 120 to leave a layer of insulating material 121 on the sides 113. The cut is centered on the cavity made in step c).

[0062] During the steps described above, and in particular during the cutting steps, the structure can be positioned on an adhesive. The adhesive used can be an ultraviolet (UV) sensitive adhesive for cutting applications ('UV cutting tape').

[0063] At the end of the process, the resulting chips 100 comprise a passivated front face 111 and partially passivated sides 113. The passivation is due to the presence of the insulating material layer 121.

[0064] The thickness of the insulating material layer 121 is less than 50 µm, for example between 10 and 50 µm. The thickness of the insulating material layer 121 on the front face 111 is, for example, between 10 and 30 µm. The thickness of the insulating material layer 121 on the sides 113 is, for example, 1 µm.

[0065] Only a portion of the side 113 is passivated. The sides comprise a first portion formed in the substrate 110, made of semiconductor material, and a second portion made of insulating material 121. The insulating material 121 is housed in a recess (or notch) formed in the substrate 110. The recess extends from the first face 111 to the second face 112 in a plane perpendicular to both the first and second faces 112. A portion of the side 113 is covered with insulating material 121, and a portion of the first face 111 is covered with insulating material 121.

[0066] With such a process the height of the sides 113 covered by the insulating material 121 can be easily adapted.

[0067] The chips obtained are surface-mount devices (or SMDs for "surface mounting device") of the WLCSP ('Wafer-level chip scale packaging') or "flip-chip" type, that is to say, they can be fixed to an external element / device 400, for example, a printed circuit board (or PCB for 'printed circuit board'), another component or a laminated substrate, by their upper face 111.

[0068] The external element 400 comprises, for example, a support 401 on which connecting elements 402 and conductive tracks 403 are formed (Figures 2 and 3). The connecting elements 402 and the tracks 403 may be made of copper.

[0069] The assembly process includes a step in which a soldering material 500 is positioned between the chip 100 and the connection elements 402 of the external device 400.

[0070] The assembly thus obtained comprises an electronic chip 100, as defined previously, and an external device 400, such as a printed circuit board, comprising connection elements 402. The connection pads 117 or the connection areas 107 of the electronic chip 100 are brazed onto the connection elements 402 of the external device 400 by a brazing material 500.

[0071] Once assembled on the external device 400, the chips are passivated in all areas near the solder alloy. During soldering, even if the solder material runs up the wettable sides 113 of the chips 100 and / or spreads across the front face, they will function correctly. The layer of insulating material 121 electrically isolates the chip 100 from the solder alloy 500.

[0072] Such CSP-type electronic chips find applications in many industrial fields.

[0073] They can, for example, be intended for the automotive industry (particularly for Advanced Driver-Assistance Systems (ADAS)), in the field of the Internet of Things and smart homes. They can be used in near-field communication (NFC), or in the implementation of 5G networks, data centers and servers.

[0074] They may be, for example, intended for use in personal electronics, in 5G connection devices or more generally in connected devices, in communication equipment, or in computers and peripherals.

[0075] They may also be of interest for other fields, such as for the industrial field, in particular for green energies.

[0076] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0077] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing passivated-sidewall electronic chips (100) from a semiconductor substrate (110) in which chips (100) are formed, a first face (111) of the substrate (110) being covered by connection pads (107), the method comprising the following steps: - preferably, forming connection pads (117) on the connection pads (107), - forming trenches (120) between the chips (100), - depositing an insulating material (121) so as to cover the substrate (110) and fill the trenches (120), - thinning the insulating material (121) until the connection pads (117) or the connection pads (107) are accessible, - separating the chips (100) by cutting at least the insulating material (121) and the substrate (110) through the trenches (120), thereby chips (100) having sides (113) partially covered by the insulating material (121) are obtained.

2. A method according to claim 1, wherein trenches (120) are formed by partially cutting the substrate (110) from the first face (111), the depth of the trenches (120) preferably being between 10 and 80% of the thickness of the substrate (110) of the chip (100).

3. A method according to any one of the preceding claims, wherein the width of the trenches (120) is between 20 and 80 pm.

4. A method according to any one of the preceding claims, wherein the insulating material (121) comprises a polymer or resin, preferably an epoxy or phenolic resin, and electrically insulating charges, for example, alumina or silica particles.

5. Electronic chip (100) with passivated sides comprising a semiconductor substrate (110), having a first face (111), a second face (112) and sides (113), the first face (111) being covered by connection pads (107), connection pads (117) being able to be positioned on the connection pads (107), a layer of insulating material (121) covering the first face (111) of the substrate (110), between the connection pads (117) or between the connection areas (107), and part of the flanks (113) from the first face (111) of the substrate (110).

6. Electronic chip (100) according to claim 5, wherein the insulating material (121) comprises a polymer or resin, preferably an epoxy or phenolic resin, and electrically insulating charges, for example alumina or silica particles.

7. Electronic chip (100) according to any one of claims 5 and 6, wherein the insulating material covers between 10 and 80%, preferably between 50 and 80%, of the height of the sides (113) of the chip (100).

8. Electronic chip according to any one of claims 5 to 7, wherein the insulating material layer (121) has a thickness of less than 50 pm, for example a thickness between 10 and 30 pm.

9. Method of assembling an electronic chip (100) according to any one of claims 5 to 8, with an external device (400), such as a printed circuit board, the method comprising the following steps: - positioning a solder material (500) between connection elements (402) of the external device (400) and either the connection pads (117) or the connection areas (107), positioned on the first face (111) of the chip (100), - soldering the solder material (500).

10. Assembly comprising an electronic chip (100) according to any one of claims 5 to 8, and an external device (400), such as a printed circuit board, the connection pads (117) or connection areas (107) of the electronic chip (100) being brazed onto the connection elements (402) of the external device (400) by a brazing material (500).

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