Optoelectronic device

Abstract

Optoelectronic Device The present description relates to an optoelectronic device comprising at least one pixel (10), the pixel comprising a photodiode (12) and a transfer transistor (16) in a first portion of a substrate (32), the first portion being surrounded by a wall (50), the wall comprising an insulating portion (52) and a semiconducting sheath (54) doped with a first type of conductivity, the transfer transistor (16) comprising a gate and first (46, 48) and second (36) conductivity regions, the first conductivity region (46, 48) comprising a first box (46) located in the substrate and a third epitaxial region (48) resting on the substrate in contact with the first box (46), the third region (48, 82) and the first box being doped with the same second type of conductivity opposite to the first type of conductivity, the third region (48) being more strongly doped than the first box (46). Figure for the abstract: Fig. 2A

Description

Title of the invention: Optoelectronic device technical field

[0001] This description relates generally to optoelectronic devices and their manufacturing processes and more specifically to devices comprising image sensors. Previous technique

[0002] Image sensors generally comprise sets of pixels, for example arranged in a matrix. Each pixel in the set comprises, for example, a photosensitive element, for example a photodiode, and a circuit for reading the photosensitive element.

[0003] The image sensor can, for example, operate in so-called "rolling shutter" mode or in so-called "global shutter" mode. In "global shutter" mode, all the photodiodes in the pixel set are read simultaneously. In "rolling shutter" mode, the photodiodes are read one after the other, for example, column by column or row by row. Summary of the invention

[0004] An embodiment overcomes all or part of the drawbacks of known optoelectronic devices.

[0005] One embodiment provides for an optoelectronic device comprising at least one pixel, the pixel comprising a photodiode and a transfer transistor in a first portion of a substrate, the first portion being surrounded by a wall, the wall comprising an insulating portion and a semiconducting sheath doped with a first type of conductivity, the transfer transistor comprising a gate and first and second conductivity regions, the first conductivity region comprising a first box located in the substrate and a third epitaxial region resting on the substrate in contact with the first box, the third region and the first box being doped with the same second type of conductivity opposite to the first type of conductivity, the third region being more strongly doped than the first box.

[0006] Another embodiment provides a method for manufacturing an optoelectronic device comprising at least one pixel, the method comprising a step of forming a photodiode of the pixel and a step of forming a transfer transistor of the pixel, the photodiode and the transfer transistor being located in a first portion of a substrate, the first portion being surrounded by a wall, the wall comprising an insulating portion and a semiconducting sheath doped with a first type of conductivity, the transfer transistor comprising a gate and a first and second conductivity regions, the first conductivity region comprising a first box located in the substrate and a third epitaxial region resting on the substrate in contact with the first box, the third region and the first box being doped with the same second type of conductivity opposite to the first type of conductivity, the third region being more strongly doped than the first box.

[0007] According to one embodiment, the photodiode comprises second and third boxes of different conductivity types, the third box being of the second conductivity type and resting on the second box.

[0008] According to one embodiment, the third compartment constitutes the second conductivity region of the transistor.

[0009] According to one embodiment, the concentration of dopants in the third region is at least one hundred times greater than the concentration of dopants in the first chamber.

[0010] According to one embodiment, the substrate is covered with an interconnection network comprising at least one via reaching the third region.

[0011] According to one embodiment, the third region completely covers the first box.

[0012] According to one embodiment, the third region partially overlaps the third region, the third region being in alignment with the via reaching the third region.

[0013] According to one embodiment, the device comprises a pixel matrix, the device being configured so that the pixels operate in a so-called "Global Shutter" operating mode.

[0014] According to one embodiment, the wall comprises a conductive core and an insulating sheath, the insulating sheath constituting the insulating portion, the insulating portion separating the conductive core from the semiconducting sheath.

[0015] According to one embodiment, the process comprises: a. the formation, by doping the substrate, of the first cavity and the second cavity; b. the formation of a first mask covering the first cavity and exposing the location of the third cavity; c. the formation of the third cavity; d. the removal of the first mask and the formation of a second mask comprising an opening exposing at least partially the first cavity and covering the third cavity; and e. the formation of the third region by epitaxial growth from the first cavity.

[0016] According to one embodiment, the second mask corresponds to a layer of the interconnection network, the opening partially uncovering the first box and being filled by the third region and by the via.

[0017] According to one embodiment, the process comprises the simultaneous formation of pixels and transistors. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1] schematically represents an example of a pixel;

[0020] Figures [Fig. 2A] and [Fig. 2B] schematically represent one embodiment of a optoelectronic device;

[0021] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D] and [Fig.3E] represent a method of implementing a manufacturing process for the device of Figures 2A and 2B;

[0022] Figure 4 schematically represents another embodiment of an optoelectronic device; and

[0023] [Fig.5A], [Fig.5B], [Fig.5C] and [Fig.5D] represent an implementation method of manufacturing the device of [Fig.4]. Description of the implementation methods

[0024] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0026] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0028] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0029] Figure 1 schematically represents an example of pixel 10 of an optoelectronic device. More precisely, pixel 10 is part of a set of pixels of an image sensor of the optoelectronic device. The pixels are, for example, all identical to the pixel shown in Figure 1. The pixels are, for example, arranged in a matrix, that is, in rows and columns.

[0030] The optoelectronic device is, for example, a device comprising a camera or a device comprising a time-of-flight measurement element. The described optoelectronic device embodiments are, for example, suitable for industrial control devices, everyday products such as biometric products or telephones. The described optoelectronic device embodiments are also suitable for the automotive field, in particular for devices enabling driver monitoring.

[0031] Pixel 10 includes a photodiode 12. Pixel 10 further includes a circuit 14 for reading the photodiode 12.

[0032] The readout circuit 14 includes a transfer transistor 16. The transistor 16 is, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The transistor 16 is, for example, controlled by a voltage TG applied to a control node, for example, a gate, of the transistor 16. A conduction node, for example, a source or drain, of the transistor 16 is, for example, connected, preferably connected, to the photodiode 12. Another conduction node of the transistor 16, drain or source, is connected, preferably connected, to a sensing node 18. Thus, the photodiode 12 is connected to the sensing node 18 by the transfer transistor 16.

[0033] The readout circuit 14 further includes a reset transistor 20. The transistor 20 is, for example, a MOSFET transistor. The transistor 20 is, for example, controlled by a voltage RST applied to a control node, for example a gate, of the transistor 20. A conduction node, for example source or drain, of the transistor 20 is, for example, connected, preferably connected, to the node 18. Another conduction node of the transistor 16, drain or source, is connected, preferably connected, to an application node 21 of a pixel supply voltage Vpix.

[0034] The reading circuit 14 further comprises transistors 22 and 24. Transistors 22 and 24 are, for example, MOSFET transistors. Transistors 22 and 24 are connected in series between a supply application node 26, Va, for example, different from the voltage Vpix, and an output node 28 of pixel 10. The voltage applied to node 28 is, for example, configured to be representative of the amount of light received by the photodiode 12.

[0035] Transistor 22 is connected between node 26 and a node 30 midway between transistors 22 and 24. In other words, a conduction node, source or drain, of transistor 22 is connected, preferably connected, to node 26 and another conduction node, drain or source, of transistor 22 is connected, preferably connected, to node 30. Transistor 22 is controlled by the voltage of the measuring node 18. Thus, the control node of transistor 22, for example the gate of transistor 22, is connected, preferably connected, to the measuring node 18.

[0036] Transistor 24 is, for example, a selection transistor and is connected between node 30 and node 28. In other words, a conduction node, source or drain, of transistor 24 is connected, preferably connected, to node 30 and another conduction node, drain or source, of transistor 24 is connected, preferably connected, to node 28. Transistor 24 is controlled by a voltage Sel applied to the control node, for example the gate, of transistor 24.

[0037] Fig. 2A and Fig. 2B schematically represent an embodiment of an optoelectronic device. More precisely, Fig. 2A corresponds to a cross-sectional view along plane AA of Fig. 2B and Fig. 2B corresponds to a top view along plane BB of Fig. 2A.

[0038] Figures 2A and 2B partially represent a pixel 10 of the optoelectronic device. More specifically, Figures 2A and 2B represent the photodiode 12 and the transfer transistor 16.

[0039] The photodiode 12 is located in a substrate 32. The substrate 32 is, for example, made of a semiconductor material, for example silicon. The substrate 32 is, for example, P-doped. The substrate 32 comprises an upper face 32a and a lower face 32b.

[0040] The photodiode 12 is located in the substrate 32. The photodiode 12 comprises, for example, a housing 34 and a housing 36 within the substrate 32. The housing 34 is, for example, a buried housing. In other words, the housing 34 is, for example, located within the substrate 32. The housing 34 is preferably separated from face 32b by a portion of the substrate 32. The housing 36 is, for example, flush with face 32a of the substrate 32. The housing 36 is, for example, located between the housing 34 and face 32a. The housings 34 and 36 are, for example, in contact with each other.

[0041] The boxes 34 and 36 are, for example, made of semiconductor materials. For example, the boxes 34 and 36 are made of the same semiconductor material, for example the same material as the substrate 32, for example silicon. The boxes 34 and 36 are, for example, doped with opposite types of doping, so as to form a PN junction at the interface of the boxes 34 and 36. The box 34 is, for example, N-type doped and the box 36 is, for example, P-type doped.

[0042] The transfer transistor 16 is located in and on the substrate 32. The transistor 16 comprises, for example, a gate located on face 32a of the substrate 32. The gate of the transistor 16 comprises, for example, a gate insulator layer 38, a gate conductor layer 40, and spacers 42. The layer 38 rests, for example, on face 32a of the substrate 32, preferably on a portion of the substrate 32 along the edges of the boxes 34 and 36. Thus, the layer 38 preferably rests on a portion 44 of the substrate in lateral contact with the boxes 34 and 36. The portion 44 is, for example, P-doped. The portion 44 constitutes, for example, the channel of the transistor 16.

[0043] Layer 40 rests on layer 38. Layer 40 is preferably separated from the substrate 32 by layer 38. Spacers 42, preferably made of an insulating material, laterally surround layers 38 and 40.

[0044] A first conduction region of the transistor 16, for example a source region in the case where the transistor 16 is an insulated-gate field-effect transistor (MOSFET), is constituted by a portion of the photodiode 12, for example by the box 34.

[0045] A second conduction region of the transistor 16, for example a drain region in the case where the transistor 16 is an insulated-gate field-effect transistor (MOSFET), is constituted by a box 46 and a region 48. Said second conduction region of the transistor 16 constitutes the measurement node 18 of the [Fig.1].

[0046] The box 46 is located in the substrate 32. More precisely, the box 46 is flush with the upper face 32a of the substrate 32. The box 46 is separated from the first conduction region by the portion 44. The box 46 is made of a semiconductor material, for example the same material as the substrate 32, for example silicon. The box 46 is doped with the same type of conductivity as the region 34, for example type N. Preferably, the box 46 is doped with the opposite type to that of the substrate 32.

[0047] Region 48 rests on the box 46. Region 48 preferably rests on the entire region 46. Region 46 is thus preferably completely covered by region 48. Region 48 therefore rests on the substrate 32, more precisely on the upper face 32a of the substrate 32. Region 48 is, for example, an epitaxial region. Region 48 is made of a semiconductor material, for example, silicon. Region 48 is doped with the same type of conductivity as the box 46, for example, type N. Region 48 is more heavily doped than the box 46. For example, the dopant concentration of region 48 is at least ten times, for example at least one hundred times, preferably at least one thousand times, greater than the dopant concentration of the box 46. For example, the dopant concentration of region 48 is approximately between 10 cm⁻¹ and 5 × 10 cm⁻¹. For example, the concentration of dopants in chamber 46 is approximately equal to 1017 cm3.

[0048] Pixel 10 includes a wall 50. Wall 50 surrounds the assembly including photodiode 12 and transistor 12. Wall 50 thus surrounds a portion of the substrate including boxes 34, 36, portion 44 and box 46.

[0049] Preferably, the gate of transistor 12, i.e., layers 38, 40 and spacers 42, extends from a first portion of wall 50 to a second portion of wall 50, preferably opposite the first portion. The gate of transistor 16 thus divides the portion of substrate 32 surrounded by wall 50 in two. The photodiode 12, i.e. that is, boxes 34 and 36, is located on one side of the grid and the assembly including region 48 and box 46 is located on the other side of the grid.

[0050] The wall 50 extends from the face 32a of the substrate 32. The wall 50 preferably extends over at least the height of the photodiode 12. Thus, the wall preferably has a height greater than the combined height of the boxes 34 and 36.

[0051] According to one embodiment, the wall 50 comprises an insulating core 52. The insulating core corresponds, for example, to a shallow trench insulation wall (STI). The core 52 preferably extends at least over the height of the photodiode 12. Thus, the core 52 preferably has a height greater than the combined height of the boxes 34 and 36.

[0052] The wall 50 further comprises a layer 54, or sheath 54. The layer 54 separates, preferably completely, the core 52 from the substrate 32. The layer 54 separates, for example, the core 52 from the box 46. Preferably, the layer 54 is in contact with the box 46. Preferably, the core 52 is completely covered by the layer 54, preferably with the exception of the upper face of the core 52, which is flush with the upper face 32a of the substrate 32. The layer 54 is made of a semiconductor material, for example, the same material as the substrate 32. The layer 54 is preferably doped with the type of doping opposite to the type of doping of the box 46. The layer 54 is preferably P-type doped. The layer 54 is more heavily doped than the substrate 32, for example, at least ten times more heavily doped. Layer 54 is more heavily doped than the portion of substrate 32 surrounding wall 50, for example at least ten times more heavily doped.The concentration of dopants in layer 54 is, for example, approximately equal to 1017 cm3. For example, layer 54 does not extend opposite region 48.

[0053] According to another embodiment, the core 52 is replaced by a conductive core, for example made of polycrystalline silicon, and an insulating sheath, for example made of silicon dioxide or silicon nitride. The insulating sheath then separates the conductive core from the layer 54. The layer 54 separates, for example, the insulating sheath from the housing 46.

[0054] The electronic device includes, for example, an interconnection network 56 covering the upper surface of the substrate 32. The interconnection network thus covers the wall 50, the photodiode 12, and the transistor 12. The interconnection network comprises a stack of insulating layers and conductive elements located within the insulating layers of the stack. The conductive elements, for example, conductive vias and conductive tracks, allow electrical connections to be formed between different elements of the pixel 10 and between the pixel 10 and elements external to the pixel. In the example shown in Figures 2A and 2B, two insulating layers 57 and 62 of the stack, as well as conductive vias 58 and 60 and a conductive track 64, are depicted. The conductive vias and conductive tracks are made of a material different from region 48, preferably made of metal. Layer 57, for example, constitutes the bottom layer of the stack. Layer 57 covers the upper face 32a of the substrate 32. Layer 57 thus preferably completely covers the upper face of the wall 50, the upper face of the box 36, region 48, and the gate of transistor 12. Vias 58 and 60 pass through layer 57 so as to reach region 58 and the conductive layer 40, respectively. The insulating layer 62 completely covers layer 57, for example. Trace 64, for example, is located in layer 62 and is in contact with via 58.

[0055] During the operation of pixel 10, pixel 10 includes a charge generation stage in photodiode 16. During this stage, transistor 16 is configured to be off. Thus, the charges are contained in photodiode 12. During another operating stage of pixel 10, the charges are transferred to the measuring node 18, i.e., to the conduction region of transistor 12 comprising region 48 and housing 46.

[0056] In certain operating modes, for example in a "Rolling Shutter" operating mode, the loads are held in the measuring node 18 for only a short time, for example less than 10 ps. In other operating modes, for example in a "Global Shutter" operating mode, the loads are held in the larger measuring node 18, for example more than 30 ms.

[0057] The measurement node could have been formed entirely within the substrate 32. Alternatively, a shallow insulating trench could have been formed in place of the wall 50. This measurement node would then have comprised a chamber having the doping concentration of the region 48 located within the substrate 32, for example, in contact with the gate of transistor 16 and with the shallow insulating trench. However, such a structure would lead to leakage at the measurement node, which would be particularly significant in operating modes where the charges are maintained in the measurement node for a considerable time. Indeed, at the interface between the chamber and the gate, a gate-induced drain leakage (GIDL) phenomenon would occur. Furthermore, at the interface between the chamber and the shallow trench, the depleted region generated by the shallow trench would lead to the recombination of electron-hole pairs.

[0058] Figures 3A, 3B, 3C, 3D, and 3E represent an implementation of a manufacturing process for the device shown in Figures 2A and 2B. Figures 3A to 3E more precisely represent steps, preferably successive, of a manufacturing process, preferably simultaneous, for a pixel 10 as described in relation to Figures 2A and 2B and a transistor, for example, a MOSFET 62. Each Figure 3A to 3E thus comprises a first view, located To the left of the figure, a portion of the substrate is shown, in and on which a MOSFET transistor is formed. Each [Fig. 3A] to [Fig. 3E] includes a second view, located to the right of the figure, representing a portion of the substrate, in and on which a pixel 10 is formed. The left portion corresponds, for example, to a logic region of an electronic chip. Alternatively, the right portion could, for example, correspond to transistors 20, 22, and 24 of [Fig. 1]. The right portion includes, for example, a sensor region of a chip.

[0059] Fig. 3A represents a step in a manufacturing process for the device of Figures 2A and 2B.

[0060] During this step, the wall 50 is formed in the substrate 32. The substrate 32 is, for example, doped, for example, P-type doped. In addition, shallow insulating trenches are formed in the substrate 32. In particular, shallow trenches 64 surrounding the transistors 62 are formed.

[0061] The step in [Fig.3A] further includes the formation of the gate of transistor 12 and the gate of transistor 62. The step thus includes the formation of the insulating layer 38, the conductive layer 40, an insulating layer 66 constituting the gate insulator of the gate of transistor 62 and a conductive layer 68 constituting the gate conductor of the gate of transistor 62.

[0062] As an alternative, at least some shallow trenches, for example all shallow trenches, formed in substrate 32 can be replaced by walls identical to wall 50.

[0063] Fig. 3B represents another step in a manufacturing process for the device of Figures 2A and 2B.

[0064] The step in [Fig. 3B] corresponds to a doping step. More precisely, during the step in [Fig. 3B], regions 70 corresponding to a portion of the source and drain regions of the transistor 62 are formed in the substrate 32, more precisely in the portion of the substrate shown on the left of [Fig. 3B]. The regions 70 are, for example, flush with the upper surface of the substrate 32. The regions 70 are preferably doped with the same type of conductivity.

[0065] In addition, the step in [Fig.3B] includes the formation, by doping, of the box 34 and the box 46 in the substrate 32, more precisely in the part of the substrate shown on the right of [Fig.3B].

[0066] In the case where the regions 70 are doped with the same type of conductivity as the boxes 34 and 46, the doping is carried out simultaneously, for example.

[0067] The doping carried out during the step in [Fig.3B] is preferably carried out with concentrations less than 10 cm⁻¹, for example substantially equal to 10 cm⁻¹.

[0068] Fig. 3C represents another step in a manufacturing process for the device of Figures 2A and 2B.

[0069] During this step, spacers are formed on the side walls of layers 40, 42, 66, 68 of the gates of transistors 16 and 62. Thus, spacers 42 are formed in the portion corresponding to the right part of [Fig.3C] and spacers 72 are formed on the side walls of layers 66 and 68 in the portion corresponding to the left part of [Fig.3C].

[0070] The step in [Fig.3C] includes the formation of a hard mask 73, for example of silicon oxide or silicon nitride, covering at least the box 46. The mask 73 covers, for example, a portion of the wall 50 and part of the gate of the transistor 16. The mask does not cover the locations of the boxes 34, 36 and the source and drain regions of the transistor 62.

[0071] The step in [Fig.3C] further includes the formation of source and drain regions 74 of the transistor 62, preferably after the formation of the spacers 74 and the mask 73. The formation of the regions 74 corresponds, for example, to doping with a higher concentration of the portion of the substrate located under the regions 70.

[0072] The step in [Fig.3C] further includes the formation of region 36, for example by doping.

[0073] The doping carried out during the step in [Fig.3C] is preferably carried out with concentrations greater than 10 cm, for example between 10 cm and 1020 cm3.

[0074] Fig. 3D represents another step in a manufacturing process for the device of Figures 2A and 2B.

[0075] The step in [Fig.3D] includes the removal of mask 73.

[0076] The step in [Fig. 3D] includes the formation of a hard mask 76, for example in silicon nitride or silicon oxide, covering at least box 36 and regions 72. The mask 76 preferably includes an opening 78 exposing at least box 46, preferably all of box 46, and exposing for example part of wall 50 and part of the grid of transistor 16. Preferably, the hard mask 76 includes an opening 78 for each pixel 10 and does not include any other openings.

[0077] The step in [Fig.3D] further includes a step of formation of region 48. The formation of region 48 corresponds for example to an epitaxial growth from the cavity 46.

[0078] Fig. 3E represents another step in a manufacturing process for the device of Figures 2A and 2B.

[0079] The step in [Fig.3E] includes, for example, the removal of mask 76.

[0080] The step in [Fig.3E] further includes the formation of the interconnection network 56. [Fig.3E] represents only the formation of layer 57 and vias 58 and 60 on the upper face of the substrate, as well as the formation of vias reaching the different regions of transistor 62. The process further includes the formation of the other insulating layers, in particular layer 62 not shown, and the conductive elements of the other layers, in particular tracks 64 not shown.

[0081] Figure 4 schematically represents another embodiment of an optoelectronic device. Figure 4 partially represents a pixel 80 of the optoelectronic device such as the device in Figure 1. More specifically, Figure 4 represents the photodiode 12 and the transfer transistor 16.

[0082] Pixel 80 comprises the elements of pixel 10 in Figures 2A and 2B. Thus, pixel 80 comprises: - the substrate 32, having an upper face 32a and a lower face 32b; - the photodiode 12, including the boxes 34 and 36; - transistor 16, the gate of the transistor being made up of layers 38, 40 and spacers 42, a first conduction region, for example the source region being made up of the box 36 and the other conduction region, corresponding for example to the drain region including the box 46; - the wall 50 comprising the core 52 and the layer 54; and - the interconnection network 56.

[0083] Pixel 80 differs from pixel 10 in that region 48 is replaced by region 82. Region 82 partially covers box 46. A portion of box 46 is therefore not covered by region 82, and is, for example, covered by layer 57.

[0084] Region 82 is made of the same material as region 48 in Figures 2A and 2B, and preferably has the same concentration of dopants.

[0085] Region 82 is preferably located in alignment with via 58. Thus, region 82 preferably has horizontal dimensions substantially equal to the horizontal dimensions of via 58. The upper face of region 82 is therefore covered, preferably entirely covered, by via 58. The lateral walls of region 82 are preferably not covered by via 58. The lateral walls of region 82 are preferably covered by layer 57.

[0086] Fig. 5A, Fig. 5B, Fig. 5C and Fig. 5D represent an implementation method of manufacturing the device of Fig. 4.

[0087] Figures 5A to 5D more precisely represent, preferably successive, steps of a manufacturing process, preferably simultaneous, of a pixel 80 as described in relation to [Fig. 4] and of a transistor, for example a MOSFET transistor 84. Each [Fig. 5A] to 5D thus comprises a first view, located on the left of said figure, representing a part of the substrate, in and on which the transistor 84. Each 5D [Fig. 5A] includes a second view, located to the right of said figure, representing a portion of the substrate, in and on which a pixel 80 is formed. The left-hand portion corresponds, for example, to a logic region of an electronic chip. Alternatively, the right-hand portion may, for example, correspond to transistors 20, 22, and 24 of [Fig. 1]. The right-hand portion includes, for example, a sensor region of a chip.

[0088] Fig. 5A represents a step in a manufacturing process for the device in Fig. 4.

[0089] The step in [Fig.5A] includes the steps in Figures 3A to 3C. The step in [Fig.4] thus includes the formation of: - trench 64; - of the grid comprising layers 66, 68 and spacers 72; - regions 74; - of wall 50; - boxes 34 and 36; - of the grid comprising layers 38, 40 and spacers 42; and region 46.

[0090] The step in [Fig.5A] further includes the removal of mask 73.

[0091] Figure [Fig. 5B] represents another step in a manufacturing process for the device in Figure [Fig. 4],

[0092] Step [Fig. 5B] comprises the formation of a hard mask 86, for example, of silicon oxide or silicon nitride. The mask 86 is, for example, made of the material of layer 57. The mask includes an opening 88 at the location of region 82 and the via 58 covering region 82. The dimensions of the opening 88 are preferably substantially equal to the dimensions of the assembly comprising region 82 and the via 58 covering region 82. The mask 86 preferably covers the entire structure resulting from step [Fig. 5A] except for the portion of the box 46 intended to be covered by region 82. This portion is uncovered by the opening 88.

[0093] Figure [5C] represents another step in a manufacturing process for the device in Figure [4],

[0094] During this step, region 82 is formed in opening 88. Region 82 is formed, for example, by epitaxial growth, for example from cavity 46. Opening 88 is not entirely filled by region 82.

[0095] Figure [Fig. 5D] represents another step in a manufacturing process for the device in Figure [Fig. 4],

[0096] The step in [Fig.5D] includes the formation, in layer 86 constituting layer 57, of openings at the locations of via 60 and vias crossing layer 57.

[0097] The step in [Fig.5D] further includes the formation of vias 58 and 60, as well as the formation of vias reaching the different regions of transistor 62.

[0098] The process further includes the formation of the other insulating layers, in particular the layer 62 not shown, and the conductive elements of the other layers, in particular the tracks 64 not shown.

[0099] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0100] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. An optoelectronic device comprising at least one pixel (10, 80), the pixel comprising a photodiode (12) and a transfer transistor (16) in a first portion of a substrate (32), the first portion being surrounded by a wall (50), the wall comprising an insulating portion (52) and a semiconducting sheath (54) doped with a first type of conductivity, the transfer transistor (16) comprising a gate and first (46, 48, 82) and second (36) conductivity regions, the first conductivity region (46, 48, 82) comprising a first cell (46) located in the substrate and a third epitaxial region (48, 82) resting on the substrate in contact with the first cell (46), the third region (48, 82) and the first cell being doped with the same second type of conductivity opposite to the first type of conductivity, the third region (48, 82) being more heavily doped than the first chamber (46).

2. Device according to claim 1, wherein the photodiode (16) comprises second (34) and third (36) boxes of different conductivity types, the third box (36) being of the second conductivity type and resting on the second box (34).

3. Device according to claim 1 or 2, wherein the third box (36) constitutes the second conductivity region of the transistor (12).

4. Device according to any one of claims 1 to 3, wherein the concentration of dopants in the third region (48, 82) is at least one hundred times greater than the concentration of dopants in the first chamber (46).

5. Device according to any one of claims 1 to 4, wherein the substrate (32) is covered with an interconnection network (56) comprising at least one via (58) reaching the third region (48, 82).

6. Device according to any one of claims 1 to 5, wherein the third region (48) completely covers the first box (46).

7. Device according to any one of claims 1 to 6, wherein the third region (82) partially overlaps the third region (48, 82), the third region (82) being in alignment with the via (58) reaching the third region (48, 82).

8. Device according to any one of claims 1 to 7, wherein the device comprises a pixel matrix (10, 80), the device being configured so that the pixels operate in a so-called "Global Shutter" operating mode.

9. Device according to any one of claims 1 to 8, wherein the wall (50) comprises a conductive core and an insulating sheath, the insulating sheath constituting the insulating portion, the insulating portion separating the conductive core from the semiconducting sheath (54).

10. A method for manufacturing an optoelectronic device comprising at least one pixel (10, 80), the method comprising a step of forming a photodiode (12) of the pixel and a step of forming a transfer transistor (16) of the pixel, the photodiode and the transfer transistor being located in a first portion of a substrate (32), the first portion being surrounded by a wall (50), the wall comprising an insulating portion (52) and a semiconducting sheath (54) doped with a first type of conductivity, the transfer transistor (16) comprising a gate and first (46, 48, 82) and second (36) conductivity regions, the first conductivity region (46, 48, 82) comprising a first box (46) located in the substrate and a third epitaxial region (48, 82) resting on the substrate in contact with the first box (46), the third region (48,82) and the first cell being doped with the same second type of conductivity opposite to the first type of conductivity, the third region (48, 82) being more strongly doped than the first cell (46).

11. Method according to claim 10 applied to the formation of a device according to any one of claims 1 to 9.

12. A method according to claim 10 or 11, wherein the method comprises: a. the formation, by doping the substrate (32), of the first cavity (46) and the second cavity (34); b. the formation of a first mask (73) covering the first cavity (46) and exposing the location of the third cavity (36); c. the formation of the third cavity; d. the removal of the first mask (73) and the formation of a second mask (57, 86) comprising an opening (78, 88) exposing the less partially the first compartment (46) and covering the third compartment (36); and e. the formation of the third region (48, 82) by epitaxial growth from the first compartment (46).

13. A method according to claim 11 in relation to claim 5, wherein the second mask (86) corresponds to a layer of the interconnection network, the opening partially uncovering the first box (46) and being filled by the third region (82) and by the via (58).

14. A method according to any one of claims 10 to 13, wherein the method comprises the simultaneous formation of pixels (10, 80) and transistors.