Manufacturing process for co-integrated FDSOI PFET and NFET transistors

Abstract

The invention relates to a method for manufacturing semiconductor devices incorporating PMOS and NMOS transistors. The method begins by depositing a silicon-germanium alloy (SiGe) layer onto a semiconductor-on-insulator substrate, comprising a silicon layer on a buried oxide layer, itself located on a semiconductor support. An isolation trench is then created, separating the regions intended for the NMOS and PMOS transistors. The PMOS region is masked to allow stress to be applied to the silicon layer of the NMOS region via STRASS recrystallization. Next, the NMOS region is masked, and the mask of the PMOS region is removed to apply stress by germanium enrichment. Figure for the abstract: Fig. 5

Description

Title of the invention: Method for manufacturing co-integrated FDSOI PFET and NFET transistors

[0001] Scope

[0002] The invention relates to a method for manufacturing a semiconductor structure comprising an N-type field-effect transistor (NFET) having a voltage-stressed silicon channel region, and a p-type field-effect transistor (PFET) having a compressive silicon-germanium Si(i_x)Gex channel region. More particularly, the semiconductor structure is fabricated on a substrate comprising a buried insulating layer.

[0003] Problem raised and prior art

[0004] An example of MOSFET transistor technology with an insulating layer buried in the substrate is FDSOI technology, an acronym for Fully Depleted Silicon-on-Insulator. This technology offers several advantages over standard bulk substrate-based technologies in terms of analog performance, power consumption, and robustness. Generally, in an FDSOI transistor, the source, drain, and channel region are separated from the rest of the semiconductor substrate by an insulating dielectric layer, usually an oxide, denoted BOX (for Buried Oxide). The channel region is the area between the drain and the source where the charge carrier conduction channel forms when the transistor is in a conducting state. The conduction channel region is made of a semiconductor material.

[0005] When the channel region is made of a crystalline material, said region is arranged according to a crystal lattice formed by periodic units. It is possible to fabricate layers of semiconductor materials with crystalline units subjected to internal mechanical stresses. The internal mechanical stresses can be tensile or compressive. At the scale of the crystal lattice, the internal mechanical stresses experienced by the crystalline units of the deposited layer generate asymmetries in said units and modifications of the electromagnetic forces between the atoms.

[0006] Engineering the internal mesh stresses in the layer forming the channel region allows for an increase in charge carrier mobility and thus obtains at least the following advantages for the operation of the transistor: - an increase in switching speed: higher mobility of charge carriers (electrons and holes) allows transistors to switch more quickly between the "ON" and "OFF" states. - an increase in conduction current: better mobility means that for the same applied voltage, the current flowing through the transistor channel is higher. - a reduction in energy consumption: by increasing the mobility of the carriers, the transistors can operate efficiently at lower voltages, which reduces energy consumption and losses through heat dissipation.

[0007] More specifically, for an NMOS transistor, an internal voltage stress applied to the lattice of the layer forming the channel region improves electron mobility. For a PMOS transistor, an internal compressive stress applied to the lattice of the layer forming the channel region improves hole mobility.

[0008] However, in state-of-the-art solutions, the fabrication of NMOS transistors with a voltage-stressed channel region and PMOS transistors with a compression-stressed channel region requires two separate processes. This introduces additional steps in the overall fabrication process of a semiconductor device comprising the two aforementioned transistor types, resulting in longer manufacturing times and increasing the risk of technological variability within the same circuit.

[0009] More specifically, the introduction of tensile stress in a silicon channel region is achievable by the technique of "top recrystallization of amorphized Si(ix)Gex on SOI," known by the acronym STRASS (for Strained Si by Top Recrystallization of Amorphized Si, |XJGcx e on SOI), and the induction of compressive stress in a channel region of a silicon-germanium alloy is achievable by the technique of "silicon enrichment with germanium." Performing these two operations requires the growth of two separated silicon-germanium Si(ix)Gex layers by epitaxy. The two layers exhibit lateral faces of the epitaxial layers of Si(ix)Gex.The lateral facets of the Si(ix)Gex layer obtained by epitaxy present an increased risk of dislocation formation during the amorphization operations required to create internal stresses using state-of-the-art methods. Dislocations reduce the mechanical robustness of the fabricated semiconductor device.

[0010] Furthermore, the appearance of dislocations in the Si(ix)Gex layers can induce short circuits in the manufactured semiconductor device. Indeed, the fabrication of NMOS / PMOS transistors generally requires a silicification step. This step involves the formation of silicides, which are metallic compounds obtained by the reaction between silicon and a metal, such as titanium, cobalt, or nickel. The main objective is to reduce the contact resistance between the source and drain of each transistor and the metallic contact layers. In the event of dislocations, silicification can induce electrically conductive areas within the dislocations, which can lead to short circuits and thus a malfunction of the device.

[0011] Response to the problem and provision of a solution

[0012] To overcome the limitations of existing solutions, the invention proposes a manufacturing process in which the fabrication of NMOS transistors with a voltage-stressed channel region and the fabrication of PMOS transistors with a compression-stressed channel region are cointegrated. The process according to the invention makes it possible to fabricate both types of transistors from a single layer of Si(ix)Gex prior to the separation of two regions by STI, which does not exhibit apparent lateral facets during thermal annealing. This reduces the risk of dislocations and thus improves the mechanical robustness and electrical reliability of the fabricated device.

[0013] Furthermore, the process according to the invention makes it possible to reduce the number of steps compared to processes according to the state of the art and thus reduce the manufacturing time and energy consumption of the manufacturing process of PMOS and NMOS transistors with channel areas in constrained semiconductors.

[0014] Furthermore, the process according to the invention allows better control of the crystalline and therefore electrical properties of the PMOS and NMOS channel zone thanks to the control of the following two parameters: the thickness of the common layer of Si(ix)Gex deposited by epitaxy during the manufacturing process according to the invention, and the percentage of germanium in said layer.

[0015] A semiconductor structure with increased charge carrier mobility in PMOS and NMOS transistors is obtained by the process according to the invention without degrading the mechanical or electrical robustness of said device.

[0016] Summary / Claims

[0017] The invention relates to a method for manufacturing a semiconductor device comprising at least one PMOS transistor and at least one NMOS transistor; said method comprising the following steps: a) deposit a layer of a Si(ix)Gex alloy, with 0 <x<l, sur un substrat de type semi-conducteur-sur-isolant. Ledit substrat comprenant une couche de silicium disposée sur une couche d'oxyde enterrée qui est disposée sur un support massif en un matériau semi-conducteur ; b) fabricate an insulation trench extending from the S i(i_x)Gex layer to at least the buried oxide layer; the dielectric insulation trench separating a first region dedicated to said NMOS transistor and a second region dedicated to said PMOS transistor; c) mask the part of the Si(ix)Gex layer located in the second region by depositing a first masking structure; d) induce a stress in the crystal lattice of the silicon layer located in the first region by a process of upper recrystallization of the previously amorphized Si(ix) Gex layer; e) mask the part of the silicon layer located in the first region by depositing a second masking structure and etch the first masking structure; f) induce stress in the crystal lattice of the silicon layer located in the second region by a germanium enrichment process.

[0018] According to a particular aspect of the invention, the first masking structure is made of dielectric material. According to a particular aspect of the invention, the second masking structure is made of dielectric material.

[0019] According to a particular aspect of the invention, the manufacturing process further comprises the following step: g) manufacturing the drain and source of the NMOS transistor in the silicon layer located in the first region; and manufacturing the drain and source of the PMOS transistor in the part of the silicon layer enriched with germanium located in the second region.

[0020] According to a particular aspect of the invention, the manufacturing process further comprises a thinning step by etching the part of the Si(ix)Gex layer located in the second region before step f).

[0021] According to a particular aspect of the invention, step d) comprises the following substeps: dl) ion implantation in the stack formed by the semiconductor layer and the Si(i_x)Gex layer in the first region so as to make the silicon layer and partially the Si(i_x)Gex layer in the first region amorphous; d2) thermal annealing of the structure so as to recrystallize the semiconductor layer and the Si(i_x)Gex layer in the first region; d3) removal of the Si layer, ix)Gcx recrystallized in the first region by etching;

[0022] According to a particular aspect of the invention, the thermal annealing step d2) is carried out at a temperature below 850°C.

[0023] According to a particular aspect of the invention, the ion implantation step dl) is carried out by ions comprising silicon or germanium or argon or fluorine, or carbon, or nitrogen or oxygen.

[0024] According to a particular aspect of the invention, step f) comprises the following substeps: fl) thermal oxidation of the Si(i_x)Gex layer located in the second region so as to diffuse the germanium atoms towards the silicon layer in the second region and transform the Si(i_x)Gex layer into a SiO2 layer; f2) thermal annealing of the structure so as to recrystallize the germanium-enriched silicon layer in the second region; f3) removal of the SiO2 layer formed in the second region by etching.

[0025] According to a particular aspect of the invention, the thermal oxidation step fl) is carried out at a temperature between 700°C and 1100°C.

[0026] According to a particular aspect of the invention, the thermal annealing step f2) is carried out at a temperature between 700°C and 1100°C.

[0027] According to a particular aspect of the invention, the deposition during step a) is an epitaxial growth of a crystalline layer in a Si(i_x)Gex alloy.

[0028] According to a particular aspect of the invention, the Si(ix)Gex layer deposited in step a) is an amorphous layer. The manufacturing process further comprises a crystallization step of said amorphous Si(ix)Gex layer carried out before step d) to transform the amorphous Si, |XGcx layer into a crystalline layer.

[0029] According to a particular aspect of the invention, the Si(ix)Gex layer is formed during step a) with a thickness between 6nm and 25nm.

[0030] According to a particular aspect of the invention, the Si(ix)Gex layer formed during step a) comprises 20% to 30% germanium.

[0031] According to a particular aspect of the invention, the thickness of the Si(ix)Gex layer deposited during step a) is equal to 8nm.

[0032] According to a particular aspect of the invention, at least one of the first masking structure or the second masking structure comprises a SiN layer disposed on a SiO2 layer.

[0033] The invention also relates to a semiconductor device comprising a PMOS transistor and an NMOS transistor separated from each other by a dielectric insulating trench. The NMOS transistor is made of a crystalline silicon layer deposited on a buried oxide layer. The lattice of the crystalline silicon layer is subjected to internal tensile mechanical stresses. The PMOS transistor is made of a crystalline Si(ix)Gex layer deposited on a buried oxide layer. The lattice of the crystalline Si(ix)Gex layer is subjected to internal compressive mechanical stresses.

[0034] According to a particular aspect of the invention, the magnitude of the mechanical tensile stresses is greater than or equal to IGPa. Detailed description

[0035] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0036] Fig. 1 illustrates the flowchart of a manufacturing process according to the invention.

[0037] Figure 2a illustrates the structure obtained at the end of the first step of the process of manufacture according to the invention.

[0038] Fig. 2b illustrates the structure obtained at the end of the second step of the manufacturing process according to the invention.

[0039] Fig. 2c illustrates the structure obtained at the end of the third step of the manufacturing process according to the invention.

[0040] Fig. 2d illustrates the structure obtained at the end of the fourth step of the manufacturing process according to the invention.

[0041] Fig. 2e illustrates the structure obtained at the end of the fifth step of the manufacturing process according to the invention.

[0042] Fig. 2f illustrates the structure obtained at the end of the fifth step of the manufacturing process according to the invention.

[0043] Fig. 2g illustrates the structure obtained at the end of the fifth step of the manufacturing process according to the invention.

[0044] Figure 3 illustrates the substeps of the "higher recrystallization of Si(ix)Gex amorphized on SOI", STRASS

[0045] Figure 4 illustrates the sub-steps of the enrichment of silicon with germanium.

[0046] Figure 5 illustrates a semiconductor device according to the invention.

[0047] Figure 1 illustrates the flowchart of the PI process for manufacturing a photonic device DI according to the invention. Figures 2a to 2g illustrate the steps of the PI process according to the invention.

[0048] The first step (a) consists of depositing a crystalline layer 12 in a Si( i_X)Gex alloy on a SUB substrate of the semiconductor-on-insulator type SOI by epitaxy. The intermediate structure obtained at the end of the first step (a) is illustrated in [Fig. 2a]. The substrate SUB comprises a silicon layer 11 deposited on a buried oxide layer BOX, which is itself deposited on a solid support of a semiconductor material 10. The Si(lx)Gex crystalline layer 12 is deposited on the silicon layer 11 of the substrate SUB. The silicon layer 11 has a thickness between 5 and 1 µm. The Si(lx)Gex crystalline layer 12 is formed by epitaxy from the silicon layer 11; this is referred to as heteroepitaxy. During this process, the silicon layer 11 on which the Si(lx)Gex layer grows imposes a crystalline orientation on the latter. The epitaxially formed silicon-germanium alloy takes the lattice parameter of the layer 11 in the plane of growth. Layer 12 has a thickness between 6nm and 25nm.As an example, the epitaxy of the silicon-germanium alloy layer is carried out by vapor-phase epitaxy. The stoichiometry of the epitaxially treated layer 12 is controlled to obtain a Si(lx)Gex layer 12 comprising 25 to 30% germanium.

[0049] The second step (b) consists of fabricating an STI isolation trench extending from the epitaxial layer 12 to the bulk semiconductor substrate 10. The intermediate structure obtained at the end of the second step (b) is illustrated in [Fig. 2b]. The dielectric isolation trench STI delimits two spatial regions: a first ZN region and a second ZP region. The first ZN region is intended to accommodate an NMOS transistor. The second ZP region is intended to accommodate a PMOS transistor. The second step (b) comprises the following substeps: the first substep (b1) consists of depositing a protective structure over the entire surface of the Si(i_x)Gex layer 12, comprising a first protective layer of SiO2 and a second protective layer of silicon nitride Si3N4. The second substep (b2) consists of fabricating a bulk semiconductor substrate 10 by lithography and etching operations.The third substep (b3) consists of filling the trench with an insulating material, typically silicon dioxide (SiO2). This is done by chemical vapor deposition (CVD). The insulating material filling is achieved by depositing TEOS (Si(0C2Hs)4), which is used as a precursor in chemical vapor deposition processes for the formation of the silicon dioxide filler. The TEOS deposition is carried out at a base temperature below 650°C, for example, 540°C. The low-temperature deposition helps to avoid [the problem of] ... The migration of germanium from layer 12 to the silicon layer 11 is a process described in the fourth substep (b4), which involves planarizing the top surface of the wafer by chemical-mechanical polishing. The protective structure is thus split into two distinct parts: a first part 13a located in the first ZN region and a second part 13b located in the second ZP region. The Si(ix)Gex layer 12 is split into two distinct parts: a first part 12a located in the first ZN region and a second part 12b located in the second ZP region. The Si layer 11 is split into two distinct parts: a first part 11a located in the first ZN region and a second part 11b located in the second ZP region. The buried oxide layer BOX is split into two distinct parts separated by the STI trench.

[0050] The third step (c) consists of masking the portion of the Si(ix)Gex layer 12b located in the second ZP region by depositing a first dielectric masking structure and etching the portion 13a of the protective structure located in the first ZN region. The intermediate structure obtained at the end of the third step (c) is illustrated in [Fig. 2c]. The masking structure is, for example, made of a Si3N4 silicon nitride layer. The protective structure located in the first ZN region is removed by etching so as to expose the first portion 12a of the Si(ix)Gex layer located in the first ZN region.

[0051] The fourth step (d) consists of inducing a voltage stress in the crystal lattice of the portion of the Si lia layer located in the first ZN region by the "higher recrystallization of amorphized Si(ix)Gex on SOI" (STRASS) technique. It should be noted that the 1la layer is intended to accommodate the channel region of the NMOS transistor being fabricated. Introducing a voltage stress in the crystal lattice of the lia layer increases the electron mobility in the future channel region of the NMOS transistor. The fourth step (d) comprises the following substeps illustrated in the flowchart of [Fig.3]: the first substep (dl) consists of carrying out an ion implantation in the stack formed by the semiconductor layer 1la and the 12a layer in Si(i mGcx of the first ZN region. The ions used include silicon or germanium or argon or fluorine, or carbon, or nitrogen or oxygen.The ion implantation dose is between 114 and 115 ions / cm². The ion implantation operation amorphizes the silicon layer 11a and partially amorphizes the layer 12a. The amorphous portion 12a' of the 12a layer is confined between the amorphous layer 11a and a still crystalline upper portion 12' of the 12a' layer. The second substep (d2) consists of thermal annealing of the structure at a temperature of 850°C or lower for a variable duration. between 30 seconds and 10 minutes, preferably 5 minutes. This allows the semiconductor layer 1la and the Si(ix)Gex 12a layer to be recrystallized in the first ZN region without diffusion of germanium from layer 12a to the silicon layer 1la located in the same ZN region. During recrystallization, annealing allows the atoms in layers 1la and 12a to rearrange into the crystal structure of the upper crystalline part 12a”, inducing a tensile stress in the silicon layer 1la because the crystal lattice adapts to that of the silicon-germanium alloy layer 12a” during this operation. The third substep (d3) consists of removing the 12a Si(ix)Gex layer from the first ZN region by chemical etching, for example with hydrogen chloride HCl in an epitaxial growth tool or by wet etching using, for example, TMAH or NH40H or per-acetic acid.Alternatively, the third substep (d3) is carried out by gaseous dry etching with NF3 or CIF3. The intermediate structure obtained at the end of the fourth step (d) is illustrated in [Fig. 2d]. The lia layer intended to host the channel region of the NMOS transistor has a voltage-stressed crystal lattice, which improves the electron mobility in said lia layer.

[0052] The fifth step (e) consists of masking the strained silicon layer 1a located in the first ZN region by depositing a second dielectric masking structure and etching the first masking structure 14a, 14a' to unmask the Si(i_x)Gex layer 12b. The intermediate structure obtained at the end of the fifth step (e) is illustrated in [Fig. 2e]. The masking structure 14a, 14a' is, for example, made by a stack consisting of a SiO2 layer 14a' and a Si3N4 silicon nitride layer 14a. The SiO2 layer 14a' acts as a mechanical stress buffer to protect the surface of the layer 1a. Indeed, the SiO2 14a' layer acts as a stop layer when you want to etch the SiN layer, then removing the thin SiO2 layer allows you to obtain the more homogeneous 12 layer.

[0053] The sixth step (f) consists of inducing a compressive stress in the crystal lattice of the silicon layer 11b located in the second ZP region by "germanium enrichment." Recall that the layer 11b is intended to accommodate the channel region of the PMOS transistor being manufactured. Introducing a compressive stress in the crystal lattice of the layer 11b increases the hole mobility in the future channel region of the PMOS transistor. The sixth step (f) comprises the following substeps illustrated in the flowchart of [Fig. 4]: the first substep (fl) consists of a thermal oxidation of the layer 12b to Si(ix)Gex. The thermal oxidation progressively transforms the layer 12b into Si(ix)Gex, a layer of SiO2, starting from the upper surface of the layer 12b towards the interface with the layer 11b. in Si. Indeed, layer 12b is exposed to an oxidizing environment, generally oxygen at high temperatures. Oxidation is carried out at a temperature between 700°C and 1100°C, preferably between 850°C and 1050°C, to enrich the silicon layer 11b with germanium. The silicon atoms in layer 12b oxidize to form silicon dioxide (SiO2), while the germanium atoms do not oxidize as readily. The process pushes the germanium atoms towards the unoxidized region and towards the silicon layer 11b, enriching layer 11b with germanium. This substep then allows the germanium atoms to diffuse towards the silicon layer 11b in the second ZP region and transform layer 12b into a SiO2 layer. As an example, we obtain an 11b layer of silicon enriched with a proportion of germanium between 15% and 80%, preferably between 20% and 40% and more preferably between 20% and 30%.The second substep (f2) consists of thermal annealing the structure to homogenize the previously germanium-enriched silicon 11b layer in the second ZP region. Thermal annealing is carried out at a temperature between 700°C and 1100°C, preferably between 850°C and 1050°C, for a duration of 30 minutes to 3 hours. To ensure sufficient and homogeneous germanium diffusion, the annealing time must be adjusted with the temperature used to obtain an adequate thermal budget: for example, substep (f2) is carried out at 900°C for 3 hours, or at 1050°C for 30 minutes. This results in a constrained crystal lattice in the germanium-enriched silicon 11b layer that is completely homogeneous. The crystal lattices are subjected to compressive stress, increasing hole mobility.The temperature range chosen for thermal annealing simultaneously densifies and solidifies the structure of the STI insulation trench. The third sub-step (f3) consists of removing the oxidized 2b layer formed in the second ZP region by etching.

[0054] Advantageously, the PI process includes a step of thinning the Si(ix)Gex layer 12b before the execution of the enrichment step f). This optional step allows the degree of germanium enrichment of the layer 11b to be adjusted after step f). Indeed, the percentage of germanium that diffuses into the layer 11b depends on two initial parameters: the thickness of the layer 12b and the percentage of germanium in said layer 12b.

[0055] The intermediate structure obtained at the end of the sixth step (f) is illustrated in [Fig. 2f]. The layer 11b intended to accommodate the channel region of the PMOS transistor has a crystalline lattice under compressional stress, which improves the mobility of the holes in said layer 1a.

[0056] The seventh step (g) consists of manufacturing the NMOS transistor in the lia layer under constraint and manufacturing the PMOS transistor in the 11b layer under constraint. The fabrication of the two transistors is carried out by standard CMOS fabrication steps, including lithography, doping to form the drains D and the sources S, and the deposition of the gates G. The intermediate structure obtained at the end of the seventh step (g) is illustrated in [Fig.2g].

[0057] Figure 5 illustrates a DI semiconductor device according to the invention. The DI semiconductor device is obtained by the PI process according to the invention. The DI semiconductor device comprises a PMOS transistor and an NMOS transistor separated from each other by a dielectric isolation trench (DIT). The NMOS transistor comprises a gate (G), a drain (D), and a source formed in a channel region by a layer 1a. The layer 1a is a crystalline silicon layer. The lattice of the layer 1a is subjected to internal mechanical voltage stresses. The layer 1a is disposed on an oxide layer embedded in a silicon substrate (10). The internal stresses of the layer 1a increase the electron mobility in the channel region of the NMOS transistor. The PMOS transistor comprises a gate (G), a drain (D), and a source (S) formed in a channel region by a layer 11b.Layer 11b is a crystalline silicon-germanium alloy layer. The lattice of layer 11b is subjected to internal compressive mechanical stresses. Layer 11b is deposited on a BOX-buried oxide layer within the silicon substrate 10. The internal stresses of layer 11b increase the mobility of the holes in the channel region of the PMOS transistor.

[0058] According to an advantageous embodiment of the invention, the amplitude of the tensile mechanical stresses in layer 11a is greater than or equal to 1GPa. According to an advantageous embodiment of the invention, the amplitude of the compressive mechanical stresses in layer 11b is between 0.8 GPa and 1.6 GPa. These stress values ​​allow for improved charge carrier mobility in the context of an FDSOI-type transistor. By way of non-limiting example, for a germanium concentration of 25% in layer 11b, a compressive stress of 1.5 GPa is achieved. The PI process according to the invention makes it possible to achieve these stress amplitude values ​​with a reduced number of steps compared to prior art processes.As an example, a tensile stress greater than IGPa in layer 1la and a compressive stress greater than IGPa in layer 11b can be obtained with a common Si layer 12 (iMGcxdeposited in a single step by epitaxy (step a)) with a thickness of 8 nm and a concentration of 30% germanium.

Claims

Demands

1. A method (PI) for manufacturing a semiconductor device (D1) comprising at least one PMOS transistor and at least one NMOS transistor; said method comprising the following steps: - (a) depositing a layer of a Si(ix)Gex alloy (12) on a semiconductor-on-insulator (SOI) substrate (SUB); said substrate (SUB) comprising a silicon layer (11) disposed on a buried oxide layer (BOX) which is disposed on a solid support of a semiconductor material (10); - (b) fabricating an insulation trench (STI) extending from the Si(ix)Gex layer (12) to at least the buried oxide layer (BOX); the dielectric insulation trench (STI) separating a first region (ZN) dedicated to said NMOS transistor and a second region (ZP) dedicated to said PMOS transistor; - (c) mask the part (12b) of the Si(ix)Gex layer located in the second region (ZP) by depositing a first masking structure (13b,14b);- (d) induce stress in the crystal lattice of the silicon layer (1a) located in the first region (ZN) by a process of upper recrystallization of the previously amorphized Si(ix)Gex layer (STRASS); - (f) mask part (1a) of the silicon layer located in the first region (ZN) by deposition of a second masking structure (13a,14a) and etch the first masking structure (13b,14b); - (g) induce stress in the crystal lattice of the silicon layer (11b) located in the second region (ZP) by a process of germanium enrichment.

2. Method (PI) of manufacturing a semiconductor device (D1) according to claim 1 further comprising the following step: g) fabricating the drain and source (D,S) of the NMOS transistor in the silicon layer located in the first region (ZN); and fabricating the drain and source (D2,S2) PMOS transistor in the part (11b) of the silicon layer enriched with germanium located in the second region (ZP);

3. A method (PI) for manufacturing a semiconductor device (Dl) according to any one of claims 1 or 2, further comprising a thinning step by etching of the portion (12b) of the layer in Si(i_x)Gex located in the second region (ZP) before the step

4. D- A method (PI) for manufacturing a semiconductor device (Dl) according to any one of claims 1 to 3, wherein step (d) comprises the following substeps: - (dl) ion implantation in the stack formed by the semiconductor layer (1la) and the Si(ix)Gex layer (12a) in the first region (ZN) so as to render amorphous the silicon layer (1la) and partially the Si(ix)Gex layer (12a) in the first region (ZN); - (d2) thermal annealing of the structure so as to recrystallize the semiconductor layer (1la) and the Si(ix)Gex layer (12a) in the first region (ZN); - (d3) removal of the recrystallized Si(ix)Gex layer (12a) in the first region (ZN) by etching;

5. Method (PI) of manufacturing a semiconductor device (Dl) according to claim 4 wherein the thermal annealing step d2) is carried out at a temperature below 850°C.

6. Method (PI) of manufacturing a semiconductor device (Dl) according to any one of claims 4 or 5 wherein the ion implantation step dl) is carried out by ions comprising silicon or germanium or argon or fluorine, or carbon, or nitrogen or oxygen.

7. A method (PI) for manufacturing a semiconductor device (D1) according to any one of claims 1 to 6, wherein step (f) comprises the following substeps: - (fl) thermal oxidation of the Si(lx)Gex (12b) layer located in the second region (ZP) so as to diffuse the germanium atoms towards the silicon (11b) layer in the second region (ZP) and transform the Si(l-x)Gex (12b) layer into a SiO2 layer; - (f2) thermal annealing of the structure so as to recrystallize the germanium-enriched silicon (11b) layer in the second region (ZP); - (f3) removal of the SiO2 (12b) layer formed in the second region (ZP) by etching;

8. A method (PI) for manufacturing a semiconductor device (Dl) according to claim 7 wherein the thermal oxidation step (fl) is carried out at a temperature between 700°C and 1100°C.

9. Method (PI) of manufacturing a semiconductor device (Dl) according to any one of claims 7 or 8 wherein the thermal annealing step f2) is carried out at a temperature between 700°C and 1100°C.

10. Method (PI) of manufacturing a semiconductor device (Dl) according to any one of claims 1 to 9 the deposition in step a) is an epitaxial growth of a crystalline layer in a Si(lx)Gex alloy (12).

11. A method (PI) for manufacturing a semiconductor device (Dl) according to any one of claims 1 to 9 wherein the Si(lx)Gex (12) layer deposited in step a) is an amorphous layer; the manufacturing method (PI) further comprising a crystallization step of said amorphous Si(lx)Gex (12) layer carried out prior to step (d).

12. Method (PI) of manufacturing a semiconductor device (Dl) according to any one of claims 1 to 11 wherein the Si(lx)Gex layer (12) is formed in step a) with a thickness between 6nm and 25nm.

13. Method (PI) of manufacturing a semiconductor device (Dl) according to any one of claims 1 to 12 the Si(lx)Gex layer (12) is formed during step a) comprises 20% to 30% germanium.

14. Method (PI) of manufacturing a semiconductor device (Dl) according to any one of claims 1 to 13 wherein the thickness of the Si(lx)Gex (12) layer deposited in step a) is equal to 8nm.

15. Method (PI) of manufacturing a semiconductor device (Dl) according to any one of claims 1 to 14 wherein at least one of the first masking structure (13a,14a) or the second masking structure (13a,14a) comprises a SiN layer disposed on a SiO2 layer.

16. Semiconductor device (Dl) comprising a PMOS transistor and an NMOS transistor separated from each other by a dielectric isolation trench (STI); the NMOS transistor being made in a crystalline silicon layer (Ia) disposed on a layer

17. buried oxide layer (BOX); the unit cells of the crystalline silicon layer (lia) subjected to internal tensile mechanical stresses; the PMOS transistor being made in a crystalline Si(lx)Gex layer (11b) disposed on a buried oxide layer (BOX); the unit cells of the crystalline Si(lx)Gex layer (lia) subjected to internal compressive mechanical stresses. Semiconductor device (Dl) according to claim 16 wherein the magnitude of the tensile mechanical stresses is greater than or equal to IGPa.

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