Half-bridge power module made using isolated GaN-on-silicon transistors

Abstract

The invention relates to a half-bridge power module comprising a substrate structured in three layers: a first layer of p-doped silicon, a second layer of p-doped silicon with a lower doping level, and a third layer of n-doped silicon. The module integrates two active components. The first component, located in a first zone, includes a heterojunction, a box, and two terminals for a voltage. The second component, located in a second zone, includes a heterojunction and a box isolated from the first by deep insulating trenches reaching the first layer. Each trench comprises a dielectric encapsulation layer and a filler material. Figure for the abstract: Fig. 1a

Description

Title of the invention: Half-bridge power module made from isolated GaN-on-silicon transistors Scope

[0001] The invention relates to the monolithic integration of heterojunction power transistors in semiconductor devices, and more particularly in a half-bridge power module. The invention further relates to a method for manufacturing a half-bridge power module comprising two HS (High Side) and LS (Low Side) transistors integrated on the same substrate. Problem raised

[0002] Wide-bandgap GaN active components, particularly planar high-electron-mobility transistors (HEMTs) on silicon substrates, are used for high-efficiency, high-density power electronics due to their high-frequency operation. In the context of the invention, a "GaN active component" is understood to be a transistor or diode in which the active region (conduction channel formation region) is formed by a heterojunction comprising at least one GaN layer; for example, a GaN / AlGaN heterojunction. By way of illustration, an AlGaN / GaN heterojunction transistor is a type of HEMT used for high-frequency and power applications. It uses an interface between AlGaN and GaN to create a two-dimensional (2DEG) high-mobility electron gas. This gas allows for a rapid, gate-controlled electron flow. GaN can withstand high voltages and operate at high temperatures.Furthermore, in a GaN diode, the anode and cathode are distinguished by their role in electron conduction. The anode is connected to the AlGaN layer and receives electrons in forward bias. The cathode is connected to the GaN layer, where a two-dimensional electron gas (2DEG) forms at the AlGaN / GaN interface. This 2DEG facilitates electron conduction. In forward bias, electrons move from the cathode to the anode, crossing the junction. In reverse bias, the potential barrier blocks this flow.

[0003] Monolithic integration of active components (transistors, diodes, etc.) reduces parasitic inductances in power and control circuits, thus exploiting the full high-frequency potential of GaN transistors. Considerable effort has been made to integrate active components onto the same silicon substrate. However, integrating multiple high-voltage GaN HEMTs remains challenging. in a power circuit and more specifically in a half-bridge power module.

[0004] To better understand the technical problem raised, we will begin by describing the general structure of a half-bridge power module. A half-bridge module is a semiconductor device that integrates two switches, generally power transistors such as MOSFETs or IGBTs, arranged in a half-bridge configuration. The module comprises a first high-side (HS) transistor, called the high-side switch, and a second low-side (LS) transistor, called the low-side switch, connected in series. The connection point between the two transistors, called the "central node," generates an alternating output voltage. The first high-side transistor, HS, connects the central node to a positive supply voltage when it is in the conducting state. The second low-side transistor, LS, connects the central node to a low supply voltage (ground, for example) when it is in the conducting state.The module also includes diodes connected in series with each other to form a branch parallel to the branch formed by the LS and HS transistors. Its operation is based on the alternating activation and deactivation of the two transistors, which varies the voltage at the central node and allows control of the output waveform and frequency. This type of module is commonly used in power conversion applications, such as inverters, switched-mode power supplies, or motor control in chopper mode.

[0005] In this context, a major technical problem is encountered, namely the phenomenon of crosstalk between the high and low switches, which can lead to charge trapping in the substrate, causing current collapse in the low transistor. Indeed, in a half-bridge module, the LS and HS transistors fabricated on the same silicon substrate are not completely physically isolated from each other and can therefore interact via the substrate, which presents a parasitic propagation path for unwanted currents between the two switches. During rapid switching of the high transistor HS, abrupt potential variations occur at the common node, which can generate interference in the substrate shared with the low transistor LS.These interferences can manifest as parasitic currents induced through the substrate, but also as charge trapping in the common substrate. These phenomena disrupt the normal operation of the low-LS transistor by altering its bias. The same problem is also encountered in the diodes of a half-bridge power module integrated on the same substrate. Prior art / State of the art restrictions

[0006] The publication entitled “Suppression of the Backgating Effect of Enhancement-Mode p-GaN HEMTs on 200-mm GaN-on-SOI for Monolithic Integration” by X. Li, M. Van Hove et al. proposes a semiconductor device comprising two GaN transistors integrated on an SOI-type substrate. The proposed device includes an isolation trench extending to the buried BOX oxide layer of the SOI substrate in order to create isolated cells for each transistor. The drawback of this solution lies in delamination problems at the interface between the individual cell and the bulk silicon substrate. This delamination problem necessitates a limitation on the maximum thickness of the AlGaN / GaN heterojunction, thereby limiting the maximum operating voltage of the module. Answer to the problem and provision of a solution

[0007] To overcome the limitations of existing solutions, the invention proposes a half-bridge power module in which the high and low transistors are fabricated on a substrate with a specific doping profile, utilizing a plurality of deep isolation trenches. The combination of the substrate's doping profile and the arrangement of these deep isolation trenches provides better isolation between the two transistors compared to prior art solutions, and thus a considerable reduction in current collapse phenomena. This allows for an increased maximum voltage range at the central node, up to 1000V in the device according to the invention.

[0008] Furthermore, the module manufacturing process according to the invention allows for the production of individual enclosures for each of the active components (transistors or diodes) during the "front end" phase of the microelectronic manufacturing process, unlike prior art solutions which require insulation operations during the final "back end" phase of the chip manufacturing process. Indeed, the structure proposed for insulating the enclosures according to the invention withstands the thermal budgets required for the manufacturing of the active components (transistors or diodes). This makes it possible to manufacture the insulation structures in a step prior to the manufacturing of the components and thus allows the insulation step to be integrated into the "front end" phase.Furthermore, the manufacture of the isolation structures according to the invention does not require any modification of the manufacturing steps of the active components, which offers compatibility of the process according to the invention for easy integration into existing semiconductor production lines. Summary / Claims

[0009] The invention relates to a half-bridge power module comprising: - A substrate comprising: a first layer of p-doped silicon; • a second layer of p-doped silicon with a doping concentration lower than that of the first layer and placed on top of the first layer; • and a third layer of n-doped silicon arranged on top of the second layer; - a first active component located in a first zone of said substrate comprising: • a first heterojunction located on the third layer; • a first compartment dedicated to the first component and formed in the first zone of said substrate; • a first terminal and a second terminal intended to receive a non-zero supply voltage; - a second active component located in a second zone of said substrate and having: • a second heterojunction located on the third layer; • a second enclosure dedicated to the second component and formed in the second zone of said substrate; the second caisson being isolated from the first caisson by a first group of deep isolation trenches extending to the first layer; • a first terminal connected to the electrical ground and a second terminal connected to the first terminal of the first active component; each insulation trench of said first group comprising: a coating layer of a dielectric material disposed on the internal walls of the trench and a filler material filling the volume in the trench.

[0010] According to a particular aspect of the invention, each isolation trench of said first group has a width-to-depth ratio between 1 / 100 and 1 / 2.

[0011] According to a particular aspect of the invention, the depth of each isolation trench of said first group is between Ipm and lOOpm.

[0012] According to a particular aspect of the invention, the width of each isolation trench of said first group is between 0.5pm and 1Opm.

[0013] According to a particular aspect of the invention, the filling material is chosen from poly-silicon or SiO2.

[0014] According to a particular aspect of the invention, the half-bridge power module further comprises a first connection trench located in the first zone and crossing the first heterojunction so as to connect on the one hand the first terminal of the first active component and on the other hand the third layer in the first box.

[0015] According to a particular aspect of the invention, the half-bridge power module further comprises a second connection trench located in the second zone and crossing the second heterojunction so as to connect on the one hand the first terminal of the second active component and on the other hand the third layer in the second box.

[0016] According to a particular aspect of the invention, the half-bridge power module further comprises a third connection trench located in the third zone of the substrate separated from the second zone by a second group of a plurality of deep isolation trenches; the connection trench connecting on the one hand the first terminal of the second active component and on the other hand the first layer in the third zone.

[0017] According to a particular aspect of the invention, the first heterojunction and the second heterojunction are AlGaN / GaN heterojunctions.

[0018] According to a particular aspect of the invention, the first active component is a power transistor; the first terminal of the first active component is its drain, the second terminal of the first active component is its source, the second active component is a power transistor; the first terminal of the first active component is its source, the second terminal of the second active component is its drain.

[0019] According to a particular aspect of the invention, the first active component is a diode; the first terminal of the first active component is its cathode, and the second terminal of the first active component is its anode. The second active component is a diode; the first terminal of the first active component is its anode, and the second terminal of the second active component is its cathode.

[0020] The invention also relates to a method for manufacturing a half-bridge power module according to the invention comprising the following steps: a. fabricate a heterojunction of two semiconductor materials by epitaxial growth on a substrate comprising the following stacking: a first layer of p-doped silicon, a second layer of p-doped silicon with a doping concentration lower than that of the first layer and disposed on the first layer, and a third layer of n-doped silicon disposed on the second layer, b. fabricate a first group of deep insulation trenches extending to the first layer and separating a first zone of the substrate from a second zone of the substrate; the fabrication is carried out by engraving a plurality of parallel trenches extending to the first layer, then depositing a dielectric layer on the internal walls of each trench, and then filling each trench with a filling material; the first group of deep insulation trenches; c. manufacture a first active component comprising the part of the heterojunction located in the first zone and having at least two terminals and a dedicated box formed in the part of the substrate located in the first zone and manufacture a second active component comprising the part of the heterojunction located in the second zone and having at least two terminals and a second dedicated box formed in the part of the substrate located in the first zone.

[0021] According to a particular aspect of the invention, the deposition of the dielectric material on the walls in step b) is a deposition of SiO2 by "chemical vapor deposition" or by decomposition of TetraEthyl OrthoSilicate.

[0022] According to a particular aspect of the invention, the filling of each trench in step b) is carried out by a deposit of poly-silicon by "chemical vapor deposition".

[0023] According to a particular aspect of the invention, step b) further comprises the manufacture of a second group of deep isolation trenches going down to the first layer and separating on the one hand a third zone of the substrate and on the other hand the second zone of the substrate.

[0024] According to a particular aspect of the invention, the method for manufacturing a half-bridge power module comprises the following step: manufacturing a connection trench located in the third zone of the substrate connecting on the one hand a first terminal of the second active component and on the other hand the first layer in the third zone.

[0025] According to a particular aspect of the invention, the manufacturing process comprises the following step: For each active component, manufacture a connection trench through the heterostructure of the active component and connecting a first terminal of said active component to the third layer in the box dedicated to the active component. Detailed description

[0026] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0027] Fig. 1a illustrates a cross-sectional view of the half-bridge power module according to a first embodiment.

[0028] Figure 1b illustrates a cross-sectional view of the half-bridge power module according to a second embodiment. The HS and LS transistors of the half-bridge power module according to this embodiment have not been shown for the sake of simplicity.

[0029] Figure [Fig. 2] illustrates the flowchart of a manufacturing process according to the invention.

[0030] Figure 3a illustrates the structure obtained at the end of the first step of the process of manufacture according to the invention.

[0031] Figure 3b illustrates the structure obtained at the end of the second step of the process of manufacture according to the invention.

[0032] Figure 3c illustrates the structure obtained at the end of the third step of the process of manufacture according to the invention.

[0033] Fig. 3d illustrates the structure obtained at the end of the fourth step of the manufacturing process according to the invention.

[0034] Figure 3e illustrates the structure obtained at the end of the fifth step of the process of manufacture according to the invention.

[0035] Fig. 3f illustrates the structure obtained at the end of the sixth step of the manufacturing process according to the invention.

[0036] Figure 3g illustrates the structure obtained at the end of the seventh step of the process of manufacture according to the invention.

[0037] Fig. 3h illustrates the structure obtained at the end of the eighth step of the manufacturing process according to the invention.

[0038] In the figures illustrating the invention, the horizontal is represented by the X and Y directions of an orthogonal coordinate system (X, Y, Z). The Z direction of this orthogonal coordinate system represents the vertical direction. Hereafter, terms such as "upper," "lower," "above," "below," "top," and "bottom" are defined with respect to this Z direction. The terms "left" and "right" are defined with respect to the X direction. The terms "front" and "back" are defined with respect to the Y direction. Hereafter, the term "thickness" designates the maximum thickness of an element along the Z direction, also known as the stacking direction. The term "width" designates the dimension of a layer along the X direction.

[0039] Fig. 1a illustrates a cross-sectional view, along the (X, Z) axis, of the power module half-bridge 1 according to a first embodiment. The half-bridge 1 power module comprises a silicon SUB substrate, a first HS transistor and a second LS transistor isolated from each other by a first group of deep insulation trenches TIL

[0040] The SUB substrate comprises a first layer 10, a second layer 11, and a third layer 12. The first layer 10 is a p-doped silicon layer. The second layer 11 is located on top of the first layer 10. The second layer 11 is p-doped with a lower concentration of positive dopants than the first layer 10. The third layer 12 is located on top of the second layer 11. The third layer 12 is n+ doped with a gradual variation in the concentration of negative dopants. The SUB substrate thus exhibits a p / p- / n+ doping profile from bottom to top, starting from the first layer 10. As an example, the doping profile of the substrate SUB is achieved by phosphorus implantation at 400 keV for a dose of 6.1015 at / cm2 and thermal annealing for 5h at 1100 C°.

[0041] The first HS transistor acts as the high switch with a gate G1 to control its conduction state, a source S1, and a drain D1 connected to a voltage source (not shown) that generates a non-zero supply voltage Vin of up to 1000V relative to the module's electrical ground. The second LS transistor acts as the low switch with a gate G2 to control its conduction state, a source S2 connected to electrical ground, and a drain D2 connected to the source SI of the first HS transistor via a conductive trace PL. The electrical connection point between the drain D2 of the second LS transistor and the source S1 of the first HS transistor constitutes the central node NC, which generates an output voltage of module 1.

[0042] The first HS transistor is fabricated in a first ZI region of the SUB substrate, and the second LS transistor is fabricated in a second Z2 region adjacent to said first ZI region. The first and second regions are separated from each other by the first group of deep isolation trenches TI1. The first HS transistor comprises a dedicated channel region 13a, 14a consisting of a first AlGaN / GaN heterojunction located in the first ZI region. Layer 13a is GaN epitaxially bonded to the third layer 12, and layer 14a is AlGaN epitaxially bonded to layer 13a. The interface between AlGaN and GaN creates a discontinuity in the energy bands, which leads to the formation of a two-dimensional (2DEG) electron gas in layer 13a near the junction. This gas is a region where electrons can move with very high mobility, because they do not undergo collisions with atoms, unlike in a classical conductor.When the first transistor is in a conducting state (via control of its gate potential Gl), the two-dimensional electron gas forms a conduction channel under the interface 13a / 14a, through which electrons can move rapidly. Similarly, the second LS transistor includes a dedicated channel region 13b, 14b consisting of a second AlGaN / GaN heterojunction located in the second Z2 region. The second heterojunction 13b, 14b functions similarly to the first heterojunction 13a, 14a. The second heterojunction 13b, 14b is electrically separated and isolated from the first heterojunction 13a, 14a by the first set of deep isolation trenches TH.

[0043] The first group of deep isolation trenches TI1 is formed by at least two deep isolation trenches extending to the first layer 10, so as to form a first box CS1 dedicated to the first HS transistor and a second box CS2 dedicated to the second LS transistor. The isolation of the boxes CS1 and CS2 eliminates crosstalk phenomena through the SUB substrate between the first HS transistor and the second LS transistor. Eliminating crosstalk problems reduces the risk of charge trapping in the SUB substrate and thus reduces the current collapse problem for the second LS transistor.

[0044] Each cell comprises an isolated portion of the third n+-doped layer 12 and an isolated portion of the second p-doped layer 11. Thus, each individual cell comprises an individualized n+ / p- diode formed by the junction between the two doped portions of layers 11, 12. The combination of the N+ / P- / P+ diode of the first cell CS1 in series with the P+ / P- / N+ diode of the second cell allows the current flow from the first cell to the second cell CS2 to be blocked.

[0045] Each deep insulation trench of the first group is formed by an encapsulation layer 21 made of a dielectric material disposed on the internal walls of the trench and a filling material 22 filling the internal volume of the trench cavity. The encapsulation / filling structure ensures good electrical insulation between the boxes CS1, CS2 and the heterojunctions 14b, 13b / 14a, 13a while ensuring the mechanical robustness of each insulation trench. The encapsulation layer 21 has a thickness between 50 nm and 5 pm, to withstand between 60 V and 6000 V respectively (assuming an insulation breakdown voltage of 12 MV / cm). Preferably, the encapsulation layer 21 is made of SiO2. Preferably, the filling material 22 is polysilicon. Each deep insulation trench has a width between 0.5pm and 1Opm and a depth between 1pm and 1OOpm.Advantageously, each deep isolation trench has a width-to-depth ratio of between 1 / 2 and 1 / 100, more advantageously between 1 / 70 and 1 / 100, which improves the electrical isolation between the two adjacent transistors HS, LS.

[0046] The combination of the use of several deep insulation trenches grouped with the doping profile of the individualized boxes by transistors makes it possible to obtain better results in terms of charge trapping reduction compared to state-of-the-art solutions.

[0047] Furthermore, the use of a group of several insulation trenches makes it possible to increase the maximum voltage range at the central node, reaching up to 1000V. Indeed, in state-of-the-art solutions, robustness against high voltage amplitudes (up to 1000V) requires a considerable increase in the width of the insulation trenches. However, for widths greater than 10 µm, it becomes difficult to fill the trench with insulation, making the production of modules operating at high voltages challenging. In this context, the solution proposed according to the invention makes it possible to ensure the module's resistance to higher voltage values ​​without complicating the manufacturing process, with the number of trenches ranging from 2 to more than ten.

[0048] Furthermore, the structure and materials of the deep insulation trenches according to the invention are compatible with integration into a process sequence of the module manufacturing prior to the manufacturing of the transistors, as they are resistant to the thermal budgets required for the manufacturing of the active components in the continuation of the process.

[0049] Advantageously, module 1 includes a first TCI connection trench located in the first zone Z1. The first TCI connection trench crosses the first heterojunction 13a, 14a so as to connect, on the one hand, the source SI of the first HS transistor and, on the other hand, the part of the third layer 12 in the first CSL box. This makes it possible to impose the same electrical potential between the source SI of the first HS transistor and its localized CSL box. Thus, even when the potential of the central node NC is equal to the supply voltage Vin, there is no potential difference between the source SI and the CS1 box, which makes it possible to considerably reduce the leakage currents through the CS1 box and thus reduce the risk of charge trapping in the SUB substrate.Furthermore, the first TCI connection trench connects the SI source to the cathode of the diode formed by the n+ / p- junction in the associated CS1 cavity. This creates a conductive layer beneath the HS transistor, acting as a localized substrate isolated from the n+ layer located beneath the LS transistor. The first TCI connection trench includes a dielectric encapsulation layer (e.g., SiO2) on the internal lateral walls of the cavity. The first TCI connection trench is filled with an electrically conductive material, such as copper, which opens into the third layer 12 in the first CS1 cavity through an opening at the lower end of the TCI trench. The first TCI connection trench has a width between 0.5 µm and 1 µm and a depth between 1 µm and 1 µm.

[0050] Symmetrically, module 1 further comprises a second connection trench TC2 located in the second zone Z2. The second connection trench TC2 passes through the second heterojunction 13b, 14b so as to connect, on the one hand, the source S2 of the second transistor LS and, on the other hand, the portion of the third layer 12 in the second box CS2. This allows the localized box CS2 to be connected to ground and thus reduces leakage currents through the box CS2. In addition, the second connection trench TC2 allows the source S2 to be connected to the cathode of the diode formed by the n+ / p- junction in the associated box CS2, which provides a conductive layer under the transistor LS acting as a localized substrate isolated from the n+ layer located under the transistor HS. The same structural characteristics and advantages detailed for the first connection trench TC1 remain valid for the second connection trench TC2.

[0051] Advantageously, module 1 further comprises a second group of deep insulating trenches TC2 similar to the first group TCI, which separate a third zone Z3 from the second zone Z2. Module 1 includes a third connecting trench TC3 located in the third zone. The third connecting trench TC3 is connected to ground and to the source S2 of the second transistor LS via a conduction track P2 in contact with its upper end. The third connecting trench TC3 has a lower end that opens onto the first layer 10 of the substrate SUB. The third connecting trench TC3 includes a dielectric coating layer (e.g., SiO2) disposed on the internal lateral walls of its cavity.The third connection trench TC3 is filled with an electrically conductive material, such as copper, which opens onto the first layer 10 via an opening at its lower end. The third connection trench TC3 thus allows direct biasing of the first layer 12, which is common to all components of module 1 (the circuit's ground). This biasing is performed directly at the wafer level (semiconductor wafer fabrication) rather than at the die level (chip assembly) during integration into a package, which simplifies the manufacturing process.

[0052] Module 1 further comprises a dielectric insulating layer 15 disposed on the upper surface of the AlGaN layers 14a, 14b. The insulating layer 15 acts as a mechanical support on which the connection tracks PI and P2 are deposited, but also as an insulator between the different electrodes SI, G1, DI and S2, G2, D2 of the active components LS, HS.

[0053] Figure [Fig. 1b] illustrates a cross-sectional view of the half-bridge power module 1 according to a second embodiment of the invention. The second embodiment differs from the first embodiment by the integration of diodes LS and HS as active components instead of transistors. The first diode HS is located in the first zone Z1 with a cathode Ct1 that receives the supply voltage Vin, an anode Anl, and a conduction zone formed by the heterojunction 14a and 13a made of AlGaN and GaN, respectively. The second diode LS is located in the second zone Z2 with a cathode Ct2 connected to the anode Anl and forming the central node NC, an anode An2 connected to ground, and a conduction zone formed by the heterojunction 14b and 13b made of AlGaN and GaN, respectively. The structural characteristics and resulting technical advantages described for the first embodiment remain valid for the second embodiment.

[0054] Alternatively, the invention offers the same advantages with regard to limiting current collapse for a mixed modulus 1 in which a A transistor is located in the first zone ZI and a diode is located in the second zone Z2, or vice versa.

[0055] Figure 2 illustrates the flowchart of a manufacturing process PROC1 according to the invention. Figures 3a-3h illustrate the structure obtained at the end of each step of the manufacturing process PROC1 according to the invention.

[0056] The first step (a) consists of fabricating a heterojunction of two semiconductor materials by epitaxial growth on a SUB substrate. The intermediate structure obtained at the end of the first step (a) is illustrated in [Fig. 3a]. The SUB substrate comprises the following stacking: a first layer 10 of p-doped silicon, a second layer 11 of p-doped silicon with a doping concentration lower than that of the first layer 10 and placed on top of the first layer 10, and a third layer 12 of n-doped silicon placed on top of the second layer 11. The doping profile of the SUB substrate is achieved by phosphorus implantation at 400 keV for a dose of 6 x 10¹⁵ at / cm² and thermal annealing for 5 h at 1100°C. As a non-limiting example, layer 13 of the heterojunction is a GaN layer and layer 14 is an AlGaN layer.The heterojunction formed by layers 13,14 constitutes the conduction zone ZA of the active components that will be manufactured in the following steps of the PROC1 process.

[0057] The second step (b) consists of manufacturing a first group of deep isolation trenches TU extending down to the first layer 10 and separating, on the one hand, a first zone ZI of the substrate and, on the other hand, a second zone Z2 of the substrate SUB. The intermediate structure obtained at the end of the second step (b) is illustrated in [Fig. 3b]. Step (b) begins with a substep of etching a plurality of parallel cavities along the stacking direction Z and through layers 11, 12, 13, and 14 until reaching the first layer 10 of the substrate SUB. The etching of the cavities is carried out by a succession of lithography and dry or wet chemical etching steps. Then, a second substep is performed, which consists of depositing a dielectric coating layer 21 on all the internal walls of each cavity.For example, the coating layer 21 is made of SiO2 and has a thickness between 50 nm and 5 pm (here the thickness is measured along the direction orthogonal to the inner wall on which the layer is deposited). For example, the coating layer 21 is deposited by chemical vapor deposition, tetraethyl orthosilicate decomposition (TEOS deposition), or atomic layer deposition (ALD). The third substep then consists of filling the remaining volume of each cavity with a filler material 22, for example, polysilicon. For example, the filler layer is deposited by subatmospheric chemical vapor deposition.

[0058] Advantageously, the second step (b) simultaneously comprises the fabrication of a second group of deep isolation trenches TI2 extending to the first layer 10 and separating, on the one hand, a third zone Z3 of the substrate and, on the other hand, the second zone Z2 of the substrate. The second group of deep isolation trenches TI2 has the same structural characteristics as the first group.

[0059] The third step (c) consists of fabricating a first active component HS (here a transistor) in the first region ZI and a second active component LS (here a transistor) in the second region Z2. The intermediate structure obtained at the end of the third step (c) is illustrated in [Fig. 3c]. The fabrication of the two transistors LS, HS is carried out by standard CMOS fabrication steps, including lithography, doping, deposition, etching to form the drains D1, D2 and the sources SI, S2, and the deposition of the gates Gl, G2. This yields a first HS transistor comprising a first dedicated cavity CS1 formed in the first region ZI of said substrate SUB, and a second LS transistor comprising a second dedicated cavity CS2 formed in the second region Z2 of said substrate SUB.

[0060] The fourth step (d) consists of depositing a dielectric insulating layer 15 on the upper surface of the AlGaN layers 14a, 14b, which encapsulates the terminals of the HS and LS transistors. The insulating layer 15 is planarized by chemical polishing to obtain a thickness corresponding to that of the terminal contacts of the LS and HS transistors. The intermediate structure obtained at the end of the fourth step (d) is illustrated in [Fig. 3d].

[0061] Once the third zone Z3 has been created in step (b), the fifth step (e) consists of fabricating a TC3 connection trench located in the third zone Z3 of the SUB substrate. The TC3 connection trench connects, on the one hand, the source S2 of the second LS transistor and, on the other hand, the first layer 10 in the third zone Z3. The fifth step (e) comprises a first substep (e1) which consists of etching at least one cavity along the Z stacking direction and through layers 11, 12, 13, 14, and 15 until reaching the first layer 10 of the SUB substrate. The cavity has a width between 1pm and 50pm and a depth between 1pm and 50pm. The second substep (e2) consists of depositing a dielectric layer on the inner lateral walls of said cavity.The third substep (e3) consists of etching the dielectric layer deposited on the surface of the cavity floor to create an opening that leads to the first layer 10 of the SUB substrate. The fourth substep (e4) consists of filling the cavity with an electrically conductive material, for example, a metallic deposit. In the fifth substep (e5), the excess metal deposited in the cavity is planarized by chemical-mechanical polishing to obtain a thickness equal to the thickness of the layer. 15. The intermediate structure obtained at the end of the fifth step (e) is illustrated in [Fig.3e].

[0062] The sixth step (f) consists of fabricating a connection trench for each transistor, either LS or HS. Each of the TCI, TC2 connection trenches passes through the heterostructure of the associated transistor to connect its source to the third layer 12 in the cavity dedicated to the transistor associated with the fabricated connection trench. The fabrication of each TCI, TC2 connection trench comprises the following substeps: a first substep (fl) which consists of etching at least one cavity along the Z-stack direction and through layers 13, 14, and 15 until reaching the third layer 12 of the SUB substrate. The cavity has a width between 1pm and 50pm and a depth between 1pm and 50pm. The second substep (f2) consists of depositing a dielectric layer on the inner side walls of said cavity.The third substep (f3) consists of etching the dielectric layer deposited on the surface of the cavity floor to create an opening that leads to the third layer 12 of the SUB substrate. The fourth substep (f4) consists of filling the cavity with an electrically conductive material, for example, a metallic deposit. In the fifth substep (f5), the excess metal deposited in the cavity is planarized by chemical-mechanical polishing to obtain a thickness equal to the thickness of the insulation layer 15. The intermediate structure obtained at the end of the sixth step (f) is illustrated in [Fig. 3f].

[0063] The seventh step (g) consists of depositing an electrically conductive track P2, for example made of copper or titanium, interconnecting the connection trench TC3, the connection trench TC2, and the source S2 of the second transistor LS. Simultaneously, the seventh step (g) further consists of depositing an electrically conductive track PI, for example made of copper or titanium, interconnecting the connection trench TCI, the drain D2 of the second transistor LS, and the source SI of the first transistor HS.

[0064] The eighth step (h) consists of depositing a dielectric ENC encapsulation layer onto the resulting structure to protect it mechanically and insulate it electrically. The intermediate structure obtained at the end of the eighth step (h) is illustrated in [Fig. 3h].

[0065] In the process according to the invention, the deep insulation trenches are manufactured before the active components are manufactured by means of a multi-layer filling of the insulation trenches that is insensitive to the thermal budget of the subsequent process. This simplifies the manufacturing process and thus saves production time and improves reliability because the insulation of the Z1 and Z2 zones is not carried out in the "back end".

Claims

1. Demands Half-bridge power module (1) comprising: - A substrate (SUB) comprising: • a first layer (10) of p-doped silicon; • a second layer (11) of p-doped silicon with a doping concentration lower than that of the first layer (10) and disposed on the first layer (10); • and a third layer (12) of n-doped silicon arranged on the second layer (11); - a first active component (HS) located in a first zone (Zl) of said substrate (SUB) comprising: • a first heterojunction (13a, 14a) arranged on the third layer (12); • a first box (CS1) dedicated to the first component and formed in the first zone (Zl) of said substrate (SUB); • a first terminal (SI, Anl) and a second terminal (Dl, Ctl) intended to receive a non-zero supply voltage (Vin); - a second active component (LS) located in a second zone (Z2) of said substrate (SUB) and having: • a second heterojunction (13b, 14b) arranged on the third layer (12); • a second box (CS2) dedicated to the second component and formed in the second zone (Z2) of said substrate (SUB); the second box (CS2) being isolated from the first box (CS1) by a first group of deep isolation trenches (TH) extending to the first layer (10); • a first terminal (S2, An2) connected to the electrical ground and a second terminal (D2, Ct2) connected to the first terminal (SI, Anl) of the first active component (HS); each insulation trench of said first group (TH) comprising: a coating layer (21) of a dielectric material disposed on the internal walls of the trench and a filling material (22) filling the volume in the trench.

2. Half-bridge electronic module (1) according to claim 1 in which each isolation trench of said first group (TI 1) has a width-to-depth ratio between 1 / 100 and 1 / 2.

3. Half-bridge power module (1) according to any one of claims 1 or 2 wherein the depth of each isolation trench of said first group (TU) is between Ipm and lOOpm.

4. Half-bridge power module (1) according to any one of claims 1 to 3 wherein the width of each insulation trench of said first group (TU) is between 0.5pm and 1Opm.

5. Half-bridge power module (1) according to any one of claims 1 to 4 wherein the filling material is selected from poly-silicon or SiO2.

6. Half-bridge power module (1) according to any one of claims 1 to 5 further comprising a first connection trench (TCI) located in the first zone (Zl) and passing through the first heterojunction (13a,14a) so as to connect on the one hand the first terminal (SI, Anl) of the first active component (HS) and on the other hand the third layer (12) in the first box (CS1).

7. Half-bridge power module (1) according to any one of claims 1 to 6 further comprising a second connection trench (TC2) located in the second zone (Z2) and passing through the second heterojunction (13b,14b) so as to connect on the one hand the first terminal (S2, An2) of the second active component (LS) and on the other hand the third layer (12) in the second box (CS2).

8. Half-bridge power module (1) according to any one of claims 1 to 7 further comprising a third connection trench (TC3) located in a third zone (Z3) of the substrate (SUB) separated from the second zone (Z2) by a second group of a plurality of deep isolation trenches (TI2); the connection trench (TC3) connecting on the one hand the first terminal (S2, An2) of the second active component (LS) and on the other hand the first layer (10) in the third zone (Z3).

9. Half-bridge power module (1) according to any one of claims 1 to 8 wherein the first heterojunction and the second heterojunction are AlGaN / GaN heterojunctions.

10. Half-bridge power module (1) according to claim 9 in which: - the first active component (HS) is a power transistor; the first terminal (SI) of the first active component (HS) is its source, the second terminal (Dl) of the first active component (HS) is its drain; - the second active component (LS) is a power transistor; the first terminal (S2) of the first active component (LS) is its source, the second terminal (D2) of the second active component (LS) is its drain.

11. Half-bridge power module (1) according to claim 9, wherein: - the first active component (HS) is a diode; the first terminal (Anl) of the first active component (HS) is its anode, the second terminal (Ctl) of the first active component (HS) is its cathode; - the second active component (LS) is a diode; the first terminal (An2) of the first active component (LS) is its anode, the second terminal (Ct2) of the second active component (HS) is its cathode.

12. A method for manufacturing (PROC1) a half-bridge power module (1) according to claim 1 comprising the following steps: a. fabricate a heterojunction of two semiconductor materials by epitaxial growth on a substrate (SUB) comprising the following stacking: a first layer (10) of p-doped silicon, a second layer (11) of p-doped silicon with a doping concentration lower than that of the first layer (10) and disposed on the first layer (10), and a third layer (12) of n-doped silicon and disposed on the second layer (H), b. construct a first group of deep isolation trenches (TI1) extending to the first layer (10) and separating, on the one hand, a first zone (Zl) from the substrate and on the other hand a second zone (Z2) of the substrate; the fabrication is carried out by engraving a plurality of parallel trenches up to the first layer (10) then depositing a dielectric layer on the internal walls of each trench then filling each trench with a filling material; the first group of deep insulation trenches (TU); c. fabricate a first active component (HS) comprising the part of the heterojunction located in the first zone (Zl) and having at least two terminals and a dedicated box formed in the part of the substrate (SUB) located in the first zone (Zl) and fabricate a second active component (LS) comprising the part of the heterojunction located in the second zone (Z2) and having at least two terminals and a second dedicated box (CS2) formed in the part of the substrate (SUB) located in the first zone (Zl).

13. A manufacturing process (PROC1) of a half-bridge power module (1) according to claim 12 wherein the deposition of the dielectric material on the walls in step b) is a deposition of SiO2 by "chemical vapor deposition" or by decomposition of TetraEthyl OrthoSilicate.

14. A manufacturing method (PROC1) for a half-bridge power module (1) according to any one of claims 12 or 13, wherein the filling of each trench in step b) is carried out by a poly-silicon deposition by chemical vapor deposition.

15. Z>. Method of manufacturing (PROC1) a half-bridge power module (1) according to any one of claims 12 to 14 wherein step b) further comprises manufacturing a second set of deep isolation trenches (TI2) extending to the first layer (10) and separating on the one hand a third zone (Z3) of the substrate and on the other hand the second zone (Z2) of the substrate.

16. A method for manufacturing (PROC1) a half-bridge power module (1) according to claim 15 comprising the following step: (e) manufacturing a connection trench (TC3) located in the third zone (Z3) of the substrate (SUB) connecting on the one hand a first terminal (S2, An2) of the second active component (LS) and on the other hand the first layer (10) in the third zone (Z3).

17. A method of manufacturing (PROC1) a half-bridge power module (1) according to any one of claims 12 to 16 comprising the following step: (f) For each active component, fabricate a connection trench (TCI, TC2) through the heterostructure of the active component and connecting a first terminal (SI, S2) of said active component to the third layer (12) in the box (CS1, CS2) dedicated to the active component.