Method for manufacturing a power electronic device, and electronic device obtained by this method
A manufacturing method for power electronic devices addresses the challenges of controlling trench bottom oxide thickness and protecting trench sides, resulting in improved performance and reliability through precise thermal oxidation and etching processes.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Filing Date
- 2024-11-08
- Publication Date
- 2026-05-15
AI Technical Summary
Existing manufacturing processes for power electronic devices, such as SiC-based MOSFET transistors, face challenges in controlling the thickness of the thick trench bottom oxide and protecting the inner sides of the trenches during oxide etching, leading to potential damage and suboptimal performance.
A method involving the formation of a stack of semiconductor layers with a trench, followed by insulating layer deposition, polysilicon filling, controlled thermal oxidation, and selective etching to create a thick trench bottom oxide layer, ensuring precise control and protection of the trench sides.
The method allows for precise control of the trench bottom oxide thickness, enhancing the quality and durability of the oxide layer, thereby improving the performance and reliability of power electronic devices like MOSFET transistors.
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Abstract
Description
Title of the invention: Method for manufacturing a power electronic device, and electronic device obtained by this method. Technical field
[0001] This description relates generally to electronic devices.
[0002] The present description relates in particular to a method of manufacturing a power electronic device in a stack of two semiconductor layers of two types of opposite conductivity, and an electronic device obtained by this method.
[0003] The present description relates more particularly to power electronic devices in which a trench is formed in the stacking of the two semiconductor layers, and in which trench a grid can be formed. Previous technique
[0004] So-called power electronic devices have been developed to meet the needs of power electronics.
[0005] An electronic device may include one or more individual electronic components such as a diode, for example a gate diode, a transistor, or one or more electronic components reproducing one or more electronic functions, such as an integrated circuit.
[0006] A power electronic device means an electronic device capable of carrying a large current and / or receiving a high voltage at its terminals.
[0007] For example, power electronic devices based on silicon carbide (SiC) substrates have been made, due to the physical properties of SiC. In particular, field-effect transistors, for example semiconductor metal-oxide-semiconductor field-effect transistors (MOSFETs), based on SiC can achieve a higher breakdown voltage, or even a lower on-state resistance, than silicon (Si)-based MOSFETs.
[0008] For example, the publication "A 4H-SiC trench MOSFET with thick bottom oxide for improving characteristics, H Takaya, J. Morimoto, K. Hamada, T. Yamamoto, J. Sakakibara, Y. Watanabe, N. Soejima 2013, 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)" describes a SiC-based MOSFET transistor, and in particular 4H-SiC, which is one of the SiC crystal structures exhibiting excellent thermal conductivity, particularly well suited to high-power applications.
[0009] The aforementioned publication describes a vertical MOSFET transistor structure, that is, a transistor in which, when conducting, current flows between the front and rear faces of the substrate in and on which it is formed. The drain region may be on the rear face of the substrate, with the source region then being on the front face of the substrate, or vice versa. The vertical MOSFET transistor comprises, on the heavily doped 4H-SiC N-type substrate, a lightly doped N-type layer, surmounted by a P-type layer. The lightly doped N-type layer forms a so-called drift region. A trench is formed from the front face of the P-type layer into the N-type layer. An oxide layer is formed in the trench, and then this oxide layer is etched to retain only a thick oxide layer at the bottom of the trench, designated as "TBO" (Thick Bottom Oxide).Then, a thin oxide layer is formed on the inner sides of the trench, which is then filled with a polysilicon layer to create the gate of the MOSFET transistor. A source region is formed around the gate while a drain region is created on the back side of the substrate.
[0010] The substrate may not be SiC-based. However, in general, a power MOSFET includes a drift region, which is an initially lightly doped region, as described above, located between the source and drain regions, so as to withstand a high voltage. The doping concentration and the thickness of the drift region can be adjusted according to the target operating voltage.
[0011] US patent 8598654B2 describes vertical MOSFET transistors with a structure similar to that of the aforementioned publication. In US patent 8598654B2, a drift region is formed in a lightly doped N-type epitaxial layer disposed on a heavily doped N-type substrate, and a P-type layer forming a body region is disposed on the drift region. Heavily doped N-type source regions are formed in the body region on either side of a gate, while drain regions are contacted on the back side of the substrate. The gates of the transistors are each formed in a trench that extends through the body region and terminates in the drift region within the epitaxial layer. The deposition of an oxide layer, then the etching of this oxide layer makes it possible to form a grid oxide on the inner sides of each trench and a thick trench bottom oxide (TBO).Next, a conductive or semiconducting material fills the trench in contact with the gate oxide and the thick trench bottom oxide. The thick trench bottom oxide may have a charge used to at least partially compensate for a charge in the drift region, to increase the doping concentration in the drift region, and to reduce the on-state resistance of the MOSFET transistor. In other words, the bottom oxide. The trench allows for optimization of doping in the drift region to obtain a relatively low on-state resistance, while maintaining a relatively high breakdown voltage.
[0012] The MOSFET transistors described above, and in particular the manufacturing processes for these transistors, have certain disadvantages, in particular, the manufacturing processes described do not allow for good control of the thickness of the thick trench bottom oxide, and they induce a risk that the inner sides of the trenches will be attacked by the etching of the oxide. Summary of the invention
[0013] There is a need for a method of manufacturing a power electronic device which overcomes at least the disadvantages indicated above, that is to say, which allows good control of the thickness of the thick trench bottom oxide, and protection of the inner sides of the trench in which the thick oxide is formed.
[0014] Preferably, a manufacturing process for a power electronic device is sought that is compatible with a CMOS (Complementary Metal Oxide Semiconductor) type process.
[0015] Preferably, a manufacturing process for a power electronic device is sought which allows control of the quality of the thick trench bottom oxide.
[0016] An embodiment overcomes all or part of the drawbacks of known manufacturing processes for power electronic devices.
[0017] An embodiment provides a method for manufacturing a power electronic device, the manufacturing method comprising, starting from a structure having a stack of a first semiconductor layer of a first type of conductivity and a second semiconductor layer of the second type of conductivity opposite to the first type of conductivity, the stack comprising a front face which is a front face of the second semiconductor layer and a back face which is a back face of the first semiconductor layer, and a trench extending from the front face through the second semiconductor layer to the inside of the first semiconductor layer: - the formation of at least one insulating layer covering the sides and bottom of the trench; - the filling of the trench lined with at least one insulating layer with polysilicon, so as to form a polysilicon region in said trench; - a first thermal oxidation of a first portion of the polysilicon region extending from the front face in depth to a non-zero distance from the bottom of the trench, so as to form a first oxide layer of silicon in the trench on a second portion of unoxidized polysilicon from the polysilicon region; - the removal of the first layer of silicon oxide; and - a second thermal oxidation of the second portion of the polysilicon region so as to form a second layer of silicon oxide at the bottom of the trench.
[0018] According to one embodiment, the manufacturing process further comprises, after the second thermal oxidation, filling the trench with a filler layer of a conductive and / or semiconducting material so as to form a grid in said trench, said filler layer being positioned on the second layer of silicon oxide; for example, the conductive and / or semiconducting material comprises polysilicon and / or a metallic material, such as tungsten and / or titanium nitride.
[0019] According to one embodiment: - the first silicon oxide layer extends to a first level located below an interface level between the first semiconductor layer and the second semiconductor layer, and the second portion of the polysilicon region extends from the bottom of the trench to the first level; and / or - the second layer of silicon oxide extends from the bottom of the trench to a second level located below the interface level between the first semiconductor layer and the second semiconductor layer.
[0020] According to one embodiment, the first and second thermal oxidations are carried out at a temperature between 700°C and 1500°C.
[0021] According to one embodiment, the removal of the first silicon oxide layer includes a selective wet etching, for example anisotropic.
[0022] According to one embodiment, at least one insulating layer is a layer forming grid insulation and barrier.
[0023] According to one embodiment, the at least one insulating layer comprises a stacking of a barrier layer, for example of aluminium trioxide, hafnium oxide or aluminium nitride, on a grid insulator layer, for example of silicon dioxide, the manufacturing process further comprising, after the second thermal oxidation, the removal of an exposed portion of the barrier layer not covered by the second silicon oxide layer.
[0024] According to one embodiment, at least one insulating layer is a barrier layer, the manufacturing process further comprising, after the second thermal oxidation, the removal of an exposed portion of the barrier layer not covered by the second silicon oxide layer, and then the formation of a grid insulation layer on the second silicon oxide layer and the sides of the trench.
[0025] According to one embodiment, the removal of the exposed portion includes wet etching, for example selective wet etching.
[0026] According to one embodiment, a hard engraving mask is disposed on the front face of the stack, the trench also extending through said hard engraving mask.
[0027] One embodiment provides for a power electronic device obtained by the manufacturing process as described above, said electronic device comprising: - a stack of a first semiconductor layer of a first type of conductivity and a second semiconductor layer of the second type of conductivity opposite to the first type of conductivity, the stack comprising a front face which is a front face of the second semiconductor layer and a back face which is a back face of the first semiconductor layer; - a trench extending from the front face through the second semiconductor layer to the inside of the first semiconductor layer; - a layer of grid insulation located at least on the sides of the trench; - a layer of silicon oxide located at the bottom of the trench; the silicon oxide layer being a thick layer of thermal silicon oxide, and extending from the bottom of the trench to a level below an interface level between the first semiconductor layer and the second semiconductor layer.
[0028] According to one embodiment, the electronic device further comprises a grid in the trench on the silicon oxide layer, the grid being isolated from the stack by the grid insulator layer and the silicon oxide layer; the grid being made of a conductive and / or semiconducting material, for example polysilicon and / or a metallic material, such as tungsten and / or titanium nitride.
[0029] According to one embodiment, the electronic device further comprises a barrier layer in the trench and located below and laterally around the silicon oxide layer; for example the grid insulator layer covers the silicon oxide layer or is below the barrier layer.
[0030] According to one embodiment, the electronic device is a semiconductor metal oxide field-effect transistor, or a gate diode.
[0031] According to one embodiment, the first and second semiconductor layers are made of silicon, silicon carbide, or gallium nitride.
[0032] According to one embodiment, the first semiconductor layer has a first thickness, the second semiconductor layer has a second thickness, the trench has a first depth in the stack and a second depth in the first semiconductor layer, the second depth being less than the first thickness, and the second silicon oxide layer, or silicon oxide layer, has a third thickness less than the second depth.
[0033] According to one embodiment, the first silicon oxide layer has a fourth thickness greater than the second thickness, and for example less than the first depth. Brief description of the drawings
[0034] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0035] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D], [Fig.1E], [Fig.1F], [Fig.1G], [Fig.1H], [Fig.II] and [Fig.U] are cross-sectional views illustrating, schematically and partially, successive stages of a manufacturing process for a power electronic device according to an embodiment;
[0036] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E], [Fig.2F], [Fig.2G], and [Fig.2H] are cross-sectional views illustrating, schematically and partially, successive stages of a manufacturing process for a power electronic device according to another embodiment;
[0037] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D], [Fig.3E], [Fig.3F], [Fig.3G], and [Fig.3H] are cross-sectional views illustrating, schematically and partially, successive stages of a manufacturing process for a power electronic device according to another embodiment. Description of the implementation methods
[0038] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0039] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the complete implementation of the power electronic devices, including any control circuits they may have, has not been detailed, as the implementation of these power electronic devices is within the capabilities of a person skilled in the art, based on the information provided in this description.
[0040] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without intermediate elements other than conductors, and when referring to two connected (in English "coupled") elements between them, this means that these two elements can be connected or linked via one or more other elements.
[0041] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0042] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.
[0043] In the following description, when reference is made to a barrier layer, it refers, unless otherwise specified, to a layer adapted to form a diffusion and / or oxidation barrier.
[0044] Fig.1A, Fig.1B, Fig.1C, Fig.1D, Fig.1E, Fig.1F, Fig.1G, Fig.1H, Fig.II and Fig.U are cross-sectional views illustrating, schematically and partially, successive stages of a manufacturing process for a 100 power electronic device according to an embodiment.
[0045] Fig. 1A illustrates a starting structure comprising a semiconductor substrate 101 of a first type of conductivity, a semiconductor layer 102 of the first type of conductivity on the semiconductor substrate 101, and a semiconductor layer 103 of the second type of conductivity on the semiconductor layer 102.
[0046] The substrate 101 has a front face 101A and a rear face 101B opposite the front face 101A.
[0047] In the following description, the first type of conductivity is considered to be of the N type and the second type of conductivity is of the P type, although it may be the reverse.
[0048] The semiconductor substrate 101 is for example made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or any other material suitable for a power electronic device.
[0049] For example, the semiconductor substrate 101 is heavily N-doped (N+ doping). As an example, the semiconductor substrate 101 has a doping level more than ten times that of the semiconductor layer 102.
[0050] The semiconductor layer 102 is an epitaxial layer, that is, formed by epitaxial growth, or epitaxy. For example, the semiconductor layer 102 is made of the same material as the substrate 101.
[0051] For example, the semiconductor layer 102 is lightly doped with N (N- doping). By way of example, the semiconductor layer 102 has a lower doping level to one tenth of the doping level of the semiconductor substrate 101. As an example, the semiconductor layer 102 has a doping concentration of approximately 1.1016 at. / cm3.
[0052] The semiconductor layer 102 forms a drift region.
[0053] The semiconductor layer 103 is an epitaxial layer. For example, the semiconductor layer 103 is made of the same material as the semiconductor layer 102, or even of the same material as the substrate 101.
[0054] For example, the semiconductor layer 103 is heavily P-doped (P+ doping). As an example, the semiconductor layer 103 has a doping level more than ten times that of the semiconductor layer 102.
[0055] For example, the semiconductor substrate 101 is made of N-doped SiC, the semiconductor layer 102 is made of N-doped SiC, and the semiconductor layer 103 is made of P-doped SiC.
[0056] The semiconductor layers 102 and 103 form a stack 104 having a PN junction. The stack 104 has a front face 104A, corresponding to the front face of the semiconductor layer 103, and a back face 104B opposite the front face 104A, corresponding to the back face of the semiconductor layer 102. The back face 104B of the stack 104 is on the front face 101A of the substrate 101.
[0057] A hard etching mask 105 is disposed on the front face of the semiconductor layer 103, i.e. on the front face 104A of the stack 104.
[0058] The hard etching mask 105 has a front face 105A and a rear face 105B opposite the front face 105A and positioned on the front face 104A of the stack 104.
[0059] The hard etching mask 105 protects areas covered by this mask during the etching process to form the trench 106 described later. The hard etching mask 105 is preferably made of a material with etching selectivity such that when the semiconductor layers 102 and 103 are etched to create the trench 106, the hard etching mask 105 remains intact. The hard etching mask 105 is, for example, made of silicon nitride (SiN). When the semiconductor layers 102 and 103 are made of SiC, the hard etching mask 105 can be referred to as the SiC etching mask.
[0060] Figure 1B illustrates a structure obtained after a step of forming an aperture 105C in the hard etching mask 105, typically by photolithography to form an etching mask (not shown), then by etching through the etching mask, the etching stopping at the semiconductor layer 103. The etching It can be a wet etching or a dry etching, for example a plasma etching, preferably chemical.
[0061] The etching mask used to form the 105C aperture can be a photosensitive resin. This etching mask is removed, for example by stripping, after the 105C aperture has been formed.
[0062] Fig. 1C illustrates a structure obtained at the end of a trench 106 formation step from the opening 105C in the semiconductor layer 103 to the semiconductor layer 102. In other words, the trench 106 extends from the front face 104A of the stack 104, and stops in the semiconductor layer 102, and it does not extend to the substrate 101.
[0063] The trench 106 is typically made by etching, the etching being configured to stop in the semiconductor layer 102. The etching can be a wet etching or a dry etching, for example a plasma etching, preferably chemical.
[0064] The engraving to create the trench 106 is carried out through the hard engraving mask 105 which protects the areas covered by this mask, the opening 105C corresponding to the formation area of the trench 106.
[0065] The trench 106 has a depth pl, taken from the front face 104A of the stack 104, which is less than the thickness e4 of the stack 104, and greater than the thickness e3 of the semiconductor layer 103. In addition, the trench 106 has a depth p2 in the semiconductor layer 102 which is less than the thickness e2 of the semiconductor layer 102.
[0066] The trench 106 has a depth p3, taken from the front face 105A of the hard etching mask 105, which is substantially equal to the depth pl plus the thickness e5 of the hard etching mask 105.
[0067] Fig.1D illustrates a structure obtained after a formation step, for example deposition, of an insulating layer 107 on the structure of Fig.1C, i.e. on the hard etching mask 105 and in the trench 106. The insulating layer 107 notably covers the sides and the bottom of the trench 106.
[0068] The insulating layer 107 can form a diffusion / oxidation barrier layer, for example to protect the semiconductor layers 102 and 103 from oxidation. The insulating layer 107 can also form a gate insulator layer.
[0069] The material of the insulating layer 107 can be chosen according to one or more of the following materials: alumina, or aluminum trioxide, (Al2O3), hafnium oxide (HfO2), aluminum nitride (AIN), and silicon dioxide (SiO2).
[0070] The technique used to form the insulating layer 107 may be an atomic layer deposition (ALD) technique, for example a PEALD technique, i.e., plasma-assisted ALD deposition, or a chemical vapor deposition (CVD) technique, for example a PECVD technique, i.e. a plasma-assisted CVD deposition.
[0071] According to the technique used to form the insulating layer 107, another insulating layer 107' can be formed on the rear face 101B of the substrate 101. In this case, this insulating layer 107' is then removed, for example by wet means, before the next step.
[0072] Fig.1E illustrates a structure obtained after a formation step, for example deposition, of a layer of polysilicon (polycrystalline silicon) 110 on the structure of Fig.1D, i.e. on the insulating layer 107. The layer of polysilicon 110 notably fills the trench 106.
[0073] For example, the technique used to form the polysilicon layer 110 is a low-pressure chemical vapor deposition (LPCVD) technique. Another polysilicon layer 110' can be formed on the rear face 101B of the substrate 101.
[0074] The polysilicon 110 layer forms a polysilicon 111 region in the trench 106 and it further generally includes an upper portion of polysilicon 112 which extends over the polysilicon 111 region and the hard etching mask 105.
[0075] Fig. 1F illustrates a structure obtained after a flattening step of the polysilicon 110 layer, so as to remove the upper portion of polysilicon 112, and retain the region of polysilicon 111 which is flush with the front face 105A of the hard etching mask 105. The flattening step includes for example a Chemical Mechanical Polishing, or CMP, step.
[0076] The thickness e6 of the polysilicon region 111 is substantially equal to the depth p3 of the trench 106 taken from the front face 105A of the hard etching mask 105 (less the thickness of the insulating layer 107 at the bottom of the trench 106).
[0077] This flattening step also removes portion 107A of the insulating layer 107 which was on the hard etching mask 105, so that the insulating layer 107 is found mainly on the sides and bottom of the trench 106.
[0078] Figure 1G illustrates a structure obtained after a thermal oxidation step of an upper portion 113 of the polysilicon region 111. This thermal oxidation step leaves a lower portion 114 of the polysilicon region 111 unoxidized. The lower portion 114 is in contact with the upper portion 113. The upper portion 113 extends to the level of the upper face 105A of the hard etching mask 105. The lower portion 114 extends to the bottom of the trench 106.
[0079] A layer of silicon oxide 115, which is a thermal oxide, is thus formed in the trench 106 on the lower portion 114 unoxidized of the polysilicon region 111. The silicon oxide layer 115 has a thickness e7. The lower portion 114 has a non-zero (greater than zero) thickness e8.
[0080] Although not shown in [Fig.1G], in general, the thermal oxidation of polysilicon increases the volume relative to the volume of polysilicon not yet oxidized, which means that the thermal silicon oxide 115 can overflow above the trench 106 or even on either side of the trench 106 onto the hard etching mask 105, as described later.
[0081] For example, thermal oxidation is carried out at an oxidation temperature between 700 and 1500°C. A person skilled in the art will ensure that the oxidation temperature is preferably below a predetermined maximum temperature to avoid NP inter-diffusion between the semiconductor layers 102 and 103.
[0082] The thermal oxidation of the upper portion 113 is carried out such that the lower, unoxidized portion 114 of the polysilicon region 111 preferably extends below the interface level between the semiconductor layer 102 and the semiconductor layer 103. In other words, the thickness e7 of the silicon oxide layer 115 is preferably greater than the thickness e3 of the semiconductor layer 103, for example, greater than the sum of the thickness e5 of the etching hard mask 105 and the thickness e3 of the semiconductor layer 103. The thickness e8 of the lower, unoxidized portion 114 is equal to the thickness e6 of the polysilicon region 111 minus the thickness e7 of the silicon oxide layer 115. The thickness e8 of the lower portion 114 oxidized is preferably less than the depth p2 of the trench 106 in the semiconducting layer 102 (less the thickness of the insulating layer 107 at the bottom of the trench 106).
[0083] If another layer of polysilicon 110' was formed on the rear face 101B of the substrate 101, it can also be thermally oxidized and form another layer of silicon oxide 115' on the rear face 101B of the substrate 101.
[0084] Fig. 1H illustrates a structure obtained after a step of removing the silicon oxide layer 115 by etching. This etching is a wet etching, preferably anisotropic, preferably a selective etching of the thermal silicon oxide with respect to the unoxidized polysilicon of the lower portion 114, or even in some cases with respect to the material of the insulating layer 107. Thus, the etching stops at the lower portion 114 of unoxidized polysilicon.
[0085] If the other silicon oxide layer 115' was formed in the previous step on the rear face 101B of the substrate 101, it can be removed at the same time as the silicon oxide layer 115.
[0086] The flanks of trench 106 are advantageously protected during this withdrawal stage: - by the insulating layer 107 forming a protective layer; and - by the type of engraving which is a wet engraving, for example selective, and not a dry engraving.
[0087] Figure II illustrates a structure obtained after a thermal oxidation step of the lower portion 114 of the polysilicon region 111. This results in a layer of silicon oxide 116, which is a thermal oxide, at the bottom of the trench 106, forming a thick trench bottom oxide (TBO) layer. The trench bottom oxide layer 116 has a thickness e9.
[0088] The thickness e9 of the trench bottom oxide layer 116 is less than the depth p2 of the trench 106 in the semiconducting layer 102 (less the thickness of the insulating layer 107 at the bottom of the trench 106). The thickness e9 is, for example, greater than 10 nanometers (nm).
[0089] The thickness e7 of the silicon oxide layer 115, and therefore the thickness e8 of the lower portion 114, can be defined so that this lower portion 114, once oxidized, and therefore the trench bottom oxide layer 116, remains below the interface level between the semiconductor layer 102 and the semiconductor layer 103. More generally, the thickness e9 of the trench bottom oxide layer 116 can be controlled, for example by controlling the thickness e7 of the silicon oxide layer 115.
[0090] Furthermore, a thermal silicon oxide is obtained that exhibits superior quality to oxides obtained by deposition, notably with fewer interface defects and less charge trapping, and which shows better resistance to chemical attack, for example during chemical etching. In addition, a silicon oxide is obtained with a higher electrical resistance than that of a silicon oxide obtained by deposition. Indeed, the dielectric constant of thermal SiO2 is between approximately 3.8 and 3.9, while the dielectric constant of SiO2 obtained by PECVD deposition is approximately 4.1.
[0091] By way of illustration; - the thickness e2 of the 102 semiconductor layer (drift layer) is between 5 and 12 pm, for example equal to about 10 pm; - the thickness e3 of the semiconductor layer 103 is between 500 and 2500 nm; - the thickness e4 of the stack 104 comprising the semiconductor layer 102 and the semiconductor layer 103 is between 5.5 and 14.5 pm; - the depth pl of trench 106 in stack 104 is between 800 and 3000 nm; - the depth p2 of the trench 106 in the semiconducting layer 102 is between 100 and 500 nm; - the thickness e5 of the hard etching mask 105 is between 30 and 200 nm, for example equal to about 50 nm; - the thickness e7 of the silicon oxide layer 115 is greater than the thickness e3 of the semiconductor layer 103; - the thickness e9 of the trench bottom oxide layer 116 is between 100 and 300 nm.
[0092] The width of the opening 105C, which conditions the width of the trench 106, is for example between 100 and 5000 nm, for example equal to about 500 nm.
[0093] Fig. U illustrates a structure obtained after a step of filling the trench 106 with a filling layer 117 of a conductive and / or semiconducting material on the trench bottom oxide layer 116. The material of the filling layer 117 is selected to form a grid 118 in the trench 106, the grid 118 being isolated from the semiconducting stack 104 at least by the insulating layer 107, and by the trench bottom oxide layer 116.
[0094] The material of the filler layer 117 may comprise a metal, for example tungsten and / or titanium nitride (TiN), and / or polysilicon. The filler layer 117 may be a stack of layers, for example a stack of at least one metal layer and one polysilicon layer.
[0095] Although not shown in [Fig.U], the filler layer 117 generally includes an upper portion extending over the trench 106 and the etching hard mask 105, this upper portion being subsequently removed by a planing step, so that the filler layer 117 is flush with the front face 105A of the etching hard mask 105. The planing step includes, for example, a chemical mechano-polishing (CMP) step.
[0096] Next, a source region can be formed in the semiconductor layer 103 around the gate 118, and a drain region in the substrate 101, the source region being connected to a source electrode S and the drain region being connected to a drain electrode D.
[0097] The structure of [Fig. 1 J] allows, for example, the formation of a MOSFET transistor 100 comprising a gate 118 in a trench 106 extending into a stack 104 of a P-type semiconductor layer 103 on an N-type semiconductor layer 102 forming a drift region, the trench 106 stopping in the N-type semiconductor layer 102. The gate 118 is isolated from the stack 104 by an insulating layer 107 located on the sides of the trench 106 and by a trench bottom oxide layer 116 located at the bottom of the trench 106 under the gate 118. The trench bottom oxide layer 116 extends from the bottom of the trench to a level which is below the interface level between the semiconducting layer 102 and the semiconducting layer 103. The trench bottom oxide layer 116 is a silicon oxide layer obtained by thermal oxidation of polysilicon.
[0098] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, and Fig. 2H are cross-sectional views illustrating, schematically and partially, successive stages of a manufacturing process for a 200 power electronic device according to another embodiment.
[0099] The process of Figures 2A to 21 includes steps common to the process of Figures IA to IJ. These common steps will not be detailed again below.
[0100] [Fig.2A] shows a structure obtained from the structure of [Fig.1C], on which, instead of forming a single insulating layer 107 as described in relation to [Fig.1D], a stack 207 of two insulating layers is formed, comprising a grid insulation layer 208 and a barrier layer 209 on the grid insulation layer 208. The stack 207 covers the sides and bottom of the trench 106, as well as the hard etching mask 105.
[0101] Thus, instead of a single layer that can fulfill the two functions of diffusion / oxidation barrier and grid insulator, two layers are formed, each having one of these functions.
[0102] Such a stacking 207 makes it possible in particular to better protect the sides of the trench 106 during the step of removing the silicon oxide layer 115 / 215 described previously and taken up again later.
[0103] The material of the grid insulating layer 208 can be silicon dioxide (SiO2). The material of the barrier layer 209 can be chosen from one or more of the following materials: alumina, or aluminum trioxide (Al2O3), hafnium oxide (HfO2) and aluminum nitride (AIN).
[0104] Similar to what is described in relation to [Fig.1E], a layer of polysilicon 210 is deposited on the stack 207, i.e. on the barrier layer 209. The layer of polysilicon 210 notably fills the trench 106. The layer of polysilicon 210 forms a region of polysilicon 211 in the trench 106 and an upper portion of polysilicon 212 which extends above the region of polysilicon 211 and the stack 207.
[0105] [Fig.2B] illustrates a structure obtained after a flattening step of the polysilicon 210 layer, similarly to what is described in connection with [Fig.1F], so as to remove the upper portion of polysilicon 212, and retain the region of polysilicon 211 which is exposed at the front face 105A of the hard etching mask 105.
[0106] This flattening step also removes portion 207A of stack 207 which was on the etching hard mask 105, so that stack 207 is found mainly on the sides and bottom of trench 106.
[0107] Figure 2C illustrates a structure obtained after a thermal oxidation step, similar to that described in relation to Figure 1G, which oxidizes an upper portion 213 of the polysilicon region 211. This step leaves a lower portion 214 of the polysilicon region 211 unoxidized, in contact with the oxidized upper portion 213. A layer of silicon oxide 215, which is a thermal oxide, is thus formed in the trench 106 on the lower portion 214 of unoxidized polysilicon. The thermal oxidation is carried out such that the lower portion 214 extends below the interface level between the semiconductor layer 102 and the semiconductor layer 103.
[0108] During this step, another layer of silicon oxide 215' can form on the rear face 101B of the substrate 101, by oxidation of the substrate 101, the thickness of which can be reduced as a result of this oxidation.
[0109] The thermal oxidation of polysilicon increases the volume compared to the volume of unoxidized polysilicon, resulting in a portion 215A of thermal silicon oxide being obtained above the trench 106, or even on either side of the hard etching mask 105. A flattening step can be carried out to remove this portion 215A and restore the silicon oxide layer 215 to the level of the upper face 105A of the hard etching mask 105, before the next step.
[0110] [Fig. 2D] illustrates a structure obtained after a removal step by etching the silicon oxide layer 215, the etching being preferably wet and selective, for example anisotropic, similarly to that described in connection with [Fig. 1H]. The etching stops at the lower portion 214.
[0111] If the other silicon oxide layer 215' was formed in the previous step on the rear face 101B of the substrate 101, it can be removed at the same time as the silicon oxide layer 215.
[0112] Figure 2E illustrates a structure obtained after a thermal oxidation step of the lower portion 214 of the polysilicon 211 region, similarly to that described in connection with Figure 2. This results in a layer of silicon oxide 216, which is a thermal oxide, at the bottom of the trench 106, forming a thick trench bottom oxide (TBO) layer 216. During this step, another layer of silicon oxide 216' can form on the rear face 101B of the substrate 101, by oxidation of the substrate 101, the thickness of which can be reduced as a result of this oxidation.
[0113] Figure 2F illustrates a structure obtained after a step of removing an upper portion 209A of the barrier layer 209. This upper portion 209A is an exposed portion, not covered by the trench bottom oxide layer 216. There remains a lower portion 209B of the barrier layer 209 which is below and laterally around the trench bottom oxide layer 216.
[0114] This removal step preferably includes a selective wet etching of the material of the barrier layer 209 with respect to the material, for example SiO2, of the grid insulation layer 208. Thus, this removal step leaves the grid insulation layer 208 on the sides of the trench 106.
[0115] Figure 2G illustrates a structure obtained after a step of filling trench 106 with a filler layer 217 of a conductive and / or semiconducting material on the trench bottom oxide layer 216, similarly to that described in connection with Figure U. The material of the filler layer 217 is selected to form a grid 218 in trench 106.
[0116] The grid 218 is isolated from the semiconductor stack 104 by the grid insulator layer 208, by the trench bottom oxide layer 216, or even by the lower portion 209B of the barrier layer 209 which surrounds the trench bottom oxide layer 216.
[0117] The filler layer material 217 may comprise a metal, for example tungsten and / or titanium nitride (TiN) and / or polysilicon. The filler layer 217 may be a stack of layers, for example a stack of at least one metal layer and one polysilicon layer.
[0118] The filler layer 217 includes an upper portion 217A which extends over the trench 106 and the etching hard mask 105.
[0119] Fig. 2H illustrates a structure obtained after a flattening step of the upper portion 217A so that the filler layer 217 is flush with the front face 105A of the hard etching mask 105. The flattening step includes, for example, a chemical polishing step (CMP).
[0120] Similar to what is described in relation to [Fig.U], a source region can then be formed in the semiconductor layer 103 around the gate 218, and a drain region in the substrate 101, the source region being connected to a source electrode S and the drain region being connected to a drain electrode D.
[0121] The structure of [Fig.2H] allows, for example, the formation of a MOSFET 200 transistor, which includes elements common to the MOSFET 100 transistor of [Fig.U]. These common elements will not be detailed again below.
[0122] The MOSFET transistor 200 of [Fig.2H] differs from the MOSFET transistor 100 of [Fig.U] mainly in that the trench bottom oxide layer 216 is surrounded laterally and below by the barrier layer 209.
[0123] Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F, Fig. 3G, and Fig. 3H are cross-sectional views illustrating, schematically and partially, successive stages of a manufacturing process for a 300 power electronic device according to another embodiment.
[0124] The process of Figures 3A to 3H includes steps common to the process of Figures 2A to 2H. These common steps will not be detailed again below.
[0125] [Fig. 3A] shows a structure obtained from the structure of [Fig. 1C], on which, instead of forming a stack 207 as described in connection with [Fig. 2A], a barrier layer 309 (insulating layer) is formed. The barrier layer 309 covers the sides and bottom of the trench 106, as well as the hard etching mask 105. The material of the barrier layer 309 can be chosen from one or more of the following materials: alumina, or aluminum trioxide (Al₂O₃), hafnium oxide (HfO₂), and aluminum nitride (Ni).
[0126] Similar to what is described in relation to [Fig.2A], a layer of polysilicon 210 is deposited on the barrier layer 309. The polysilicon 210 layer forms a region of polysilicon 211 in the trench 106 and an upper portion of polysilicon 212 which extends over the trench 106 and the barrier layer 309.
[0127] [Fig.3B] illustrates a structure obtained after a flattening step of the polysilicon 210 layer, similarly to that described in connection with [Fig.2B], so as to remove the upper portion of polysilicon 212, and retain the region of polysilicon 211 which is exposed at the front face 105A of the hard etching mask 105. This flattening step also removes the portion 309A of the barrier layer 309 which was on the hard etching mask 105, so that the barrier layer 309 is found mainly on the sides and bottom of the trench 106.
[0128] Figure 3C illustrates a structure obtained after a thermal oxidation step, similar to that described in relation to Figure 2C, which oxidizes an upper portion 213 of the polysilicon region 211, leaving a lower portion 214 of unoxidized polysilicon in contact with the oxidized upper portion 213. This forms a layer of silicon oxide 215, which is a thermal oxide, in the trench 106 on the lower portion 214. The thermal oxidation is carried out such that the lower portion 214 is below the interface level between the semiconductor layer 102 and the semiconductor layer 103.
[0129] Similar to [Fig.2C], there is a portion 215A of thermal silicon oxide above the trench 106, or even on either side of the hard etching mask 105, and another layer of silicon oxide 215' can form on the rear face 101B of the substrate 101.
[0130] Figure 3D illustrates a structure obtained after a removal step by etching the silicon oxide layer 215, similarly to what is described in connection with the [Fig. 2D]. The etching stops at the lower portion 214 of unoxidized polysilicon. The other silicon oxide layer 215' can be removed at the same time as the silicon oxide layer 215.
[0131] Figure 3E illustrates a structure obtained after a thermal oxidation step of the lower portion 214 of the polysilicon 211 region, similarly to that described in connection with Figure 2E. This results in a layer of silicon oxide 216, which is a thermal oxide, at the bottom of the trench 106, forming a thick trench bottom oxide (TBO) layer 216. During this step, another layer of silicon oxide 216' can form on the rear face 101B of the substrate 101, by oxidation of the substrate 101.
[0132] Fig. 3F illustrates a structure obtained after a step of removing an upper portion 309A of the barrier layer 309. This upper portion 309A is an exposed portion, not covered by the trench bottom oxide layer 216. There remains a lower portion 309B of the barrier layer 309 which is below and laterally around the trench bottom oxide layer 216.
[0133] An upper part of the sides of trench 106 can thus be uncovered, which provides the advantage of being able to clean these sides.
[0134] Fig. 3G illustrates a structure obtained after a step of forming a grid insulator layer 308 on the structure of Fig. 3F, in particular on the sides and bottom of the trench 106. The grid insulator layer 308 may include an upper portion 308A on the hard etching mask 105.
[0135] Next, the trench 106 is filled with a filling layer 217 of a conductive and / or semiconducting material on the trench bottom oxide layer 216, similarly to what is described in connection with [Fig.2G], in order to form a grid 218 in the trench 106.
[0136] Fig. 3H illustrates a structure obtained after a step of removing, by flattening, the upper portion 217A of the filling layer 217 so that the filling layer 217 is flush with the front face 105A of the hard etching mask 105, similarly to what is described in connection with Fig. 2H.
[0137] During this step, the upper portion 308A of the grid insulating layer 308 can also be removed.
[0138] The grid 218 is isolated from the semiconductor stack 104 by the grid insulator layer 308, by the trench bottom oxide layer 216, or even the lower portion 309B of the barrier layer 309. The grid insulator layer 308 is found on the trench bottom oxide layer 216, and no longer under the trench bottom oxide layer 216 as in [Fig.2H].
[0139] The structure of [Fig. 3H] allows, for example, the formation of a MOSFET 300 transistor, which includes elements common to the MOSFET 200 transistor of [Fig. 2H]. These common elements will not be detailed again below.
[0140] The MOSFET transistor 300 of [Fig. 3H] differs from the MOSFET transistor 200 of [Fig. 2H] mainly in that the trench bottom oxide layer 216 is further covered by the gate insulator layer 308. The embodiment of Figures 3A to 3H makes it possible to have a gate insulator layer 308 which is not at risk of being attacked during the removal of the thermal oxide since it is deposited at the end of the process.
[0141] The electronic devices in Figures IJ, 2H and 3H each have a vertical structure, in which the conduction electrodes, which are source and drain electrodes in the illustrated examples, but which could be, for example, an anode and a cathode in the case of a diode, are located on either side of the structure comprising the substrate 101, the stack 104, or even the layer 105. This advantageously allows, in particular compared to electronic devices having a lateral structure, in which the conduction electrodes are located on the same side of the substrate, higher breakdown voltages to be obtained.
[0142] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, although structures and manufacturing methods for MOSFET-type transistors have been detailed above in connection with Figures IA to 3H, the described embodiments apply to other types of electronic devices comprising one or more electronic components formed in a stack of two semiconductor layers of two opposing types of conductivity with a trench in these two semiconductor layers, and, for example, a gate in the trench. The electronic components may, for example, have a vertical structure, or a horizontal structure in which the source and drain are on either side of the gate in the same plane.Furthermore, although embodiments in which the first conductivity type is N-type and the second conductivity type is P-type have been described above, a person skilled in the art can adapt the embodiments of this description to cases where the conductivity types are reversed. In addition, a hard etching mask might not be required.
[0143] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Demands
1. Method of manufacturing a power electronic device (100; 200; 300), the manufacturing method comprising, from a structure having a stack (104) of a first semiconductor layer (102) of a first type of conductivity and a second semiconductor layer (103) of the second type of conductivity opposite to the first type of conductivity, the stack comprising a front face (104A) which is a front face of the second semiconductor layer and a back face (104B) which is a back face of the first semiconductor layer, and a trench (106) extending from the front face through the second semiconductor layer to the inside of the first semiconductor layer: - the formation of at least one insulating layer (107; 208, 209; 309) covering the sides and the bottom of the trench;- filling the trench lined with at least one insulating layer with polysilicon, so as to form a polysilicon region (111; 211) in said trench; - a first thermal oxidation of a first portion (113; 213) of the polysilicon region extending from the front face (104A) in depth to a non-zero distance from the bottom of the trench (106), so as to form a first layer of silicon oxide (115; 215) in the trench on a second portion (114; 214) of unoxidized polysilicon of the polysilicon region; - the removal of the first layer of silicon oxide (115; 215); and - a second thermal oxidation of the second portion (114; 214) of the polysilicon region so as to form a second layer of silicon oxide (116; 216) at the bottom of the trench.;
2. A manufacturing method according to claim 1, further comprising, after the second thermal oxidation, filling the trench (106) with a filling layer (117; 217) of a conductive and / or semiconducting material so as to form a grid (118; 218) in said trench, said filling layer being positioned on the second layer of silicon oxide; for example, the conductive and / or semiconducting material comprises polysilicon and / or a metallic material, such as tungsten and / or titanium nitride.
3. A method according to claim 1 or 2, wherein: - the first silicon oxide layer (115; 215) extends to a first level located below an interface level between the first semiconductor layer and the second semiconductor layer, and the second portion (114; 214) of the polysilicon region extends from the bottom of the trench (106) to the first level; and / or - the second silicon oxide layer (116; 216) extends from the bottom of the trench to a second level located below the interface level between the first semiconductor layer and the second semiconductor layer.
4. A process according to any one of claims 1 to 3, wherein the first and second thermal oxidations are carried out at a temperature between 700°C and 1500°C.
5. A method according to any one of claims 1 to 4, wherein the removal of the first silicon oxide layer (115; 215) comprises a selective wet etching, for example anisotropic.
6. A method according to any one of claims 1 to 5, wherein at least one insulating layer (107) is a grid-forming insulating and barrier layer.
7. A method according to any one of claims 1 to 5, wherein at least one insulating layer (208, 209) comprises a stacking (207) of a barrier layer (209), for example of aluminium trioxide, hafnium oxide or aluminium nitride, on a grid insulator layer (208), for example of silicon dioxide, the manufacturing method further comprising, after the second thermal oxidation, the removal of an exposed portion (209A) of the barrier layer not covered by the second silicon oxide layer (216).
8. A method according to any one of claims 1 to 5, wherein at least one insulating layer (309) is a barrier layer, the manufacturing method further comprising, after the second thermal oxidation, the removal of an exposed portion (309A) of the barrier layer not covered by the second silicon oxide layer (216), and then the formation of a grid insulator layer (308) on the second silicon oxide layer and the sides of the trench (106).
9. A method according to claim 7 or 8, wherein the removal of the exposed portion (209A; 309A) comprises wet etching, for example selective wet etching.
10. A method according to any one of claims 1 to 9, wherein a hard etching mask (105) is disposed on the front face (104A) of the stack (104), the trench (106) also extending through said hard etching mask.
11. A power electronic device (100; 200; 300) obtained by the manufacturing process selected according to any one of claims 1 to 10, said electronic device comprising: - a stack (104) of a first semiconductor layer (102) of a first type of conductivity and a second semiconductor layer (103) of the second type of conductivity opposite to the first type of conductivity, the stack comprising a front face (104A) which is a front face of the second semiconductor layer and a back face (104B) which is a back face of the first semiconductor layer; - a trench (106) extending from the front face through the second semiconductor layer to the interior of the first semiconductor layer; - a grid insulator layer (107; 208; 308) located at least on the sides of the trench; - a layer of silicon oxide (116; 216) located at the bottom of the trench;the silicon oxide layer being a thick layer of thermal silicon oxide, with a thickness greater than 10 nm, and extending from the bottom of the trench to a level located below an interface level between the first semiconductor layer and the second semiconductor layer.;
12. Electronic device (200; 300) according to claim 11, further comprising a grid (118; 218) in the trench (106) on the silicon oxide layer (116; 216), the grid being isolated from the stack (104) by the grid insulator layer and the silicon oxide layer; the grid being made of a conductive and / or semiconducting material, for example polysilicon and / or a metallic material, such as tungsten and / or titanium nitride.
13. Electronic device (200; 300) according to claim 11 or 12, further comprising a barrier layer (209; 309) in the trench
14.
15. (106) and located below and laterally around the silicon oxide layer (216); for example the grid insulator layer (208; 308) covers the silicon oxide layer (216), or is below the barrier layer (209). Electronic device (100; 200; 300) according to any one of claims 11 to 13, the electronic device being a semiconductor metal-oxide-semiconductor field-effect transistor, or a gated diode. Electronic device (100; 200; 300) according to any one of claims 11 to 14, wherein: - the first and second semiconductor layers (102, 103) are made of silicon, silicon carbide, or gallium nitride; and / or - the first semiconductor layer (102) has a first thickness (e2), the second semiconductor layer (103) has a second thickness (e3), the trench (106) has a first depth (pl) in the stack (104) and a second depth (p2) in the first semiconductor layer, the second depth (p2) being less than the first thickness (e2), and the silicon oxide layer (116;216) has a third thickness (e9) less than the second depth (p2).