Electronic device

Abstract

Electronic Device This description relates to an electronic device (22) comprising: - a first stack (24) of the silicon-on-insulator type, the first stack (24) comprising a first lower semiconductor layer (26), a second upper semiconductor layer (28), and a third insulating layer (30) separating the first lower semiconductor layer (26) and the second upper semiconductor layer (28), the second upper semiconductor layer (28) comprising at least one first portion (28b), each first portion (28b) not comprising an active component; and - a second stack (32) of fourth insulating layers (34, 36) in which conductive tracks (38) and conductive vias are located, the second stack covering the second upper semiconductor layer, at least one first portion (28b) being located opposite a conductive track (38). Figure for the abstract: Fig. 2

Description

Title of the invention: Electronic device technical field

[0001] This description relates generally to electronic devices and more specifically to electronic devices intended for use in telecommunications. Previous technique

[0002] Devices in which radio frequency (RF) signals are transmitted generally include substrates with high resistivity. Indeed, such substrates make it possible to reduce losses and parasitic effects in radio frequency and microwave signal waveguides, for example in telecommunications applications. Summary of the invention

[0003] An embodiment overcomes all or part of the drawbacks of known electronic devices.

[0004] One embodiment provides an electronic device comprising: a first silicon-on-insulator stack, the first stack comprising a first lower semiconductor layer, a second upper semiconductor layer and a third insulating layer separating the first lower semiconductor layer and the second upper semiconductor layer, the second upper semiconductor layer comprising at least a first portion, each first portion not comprising an active component; and a second stack of fourth insulating layers in which conductive tracks and conductive vias are located, the second stack covering the second upper semiconductor layer, at least a first portion being located opposite a conductive track.

[0005] Another embodiment provides for a method of manufacturing an electronic device comprising: a first silicon-on-insulator stack, the first stack comprising a first lower semiconductor layer, a second upper semiconductor layer and a third insulating layer separating the first and second layers, the second layer comprising at least a first portion, each first portion not comprising an active component; and a second stack of fourth insulating layers in which conductive tracks and conductive vias are located, the second stack covering the second upper semiconductor layer, the method comprising the formation of at least a first portion located opposite a conductive track.

[0006] According to one embodiment, the thickness of the third layer is less than 30 nm.

[0007] According to one embodiment, the nominal resistivity of the first layer is greater than 100 Q.cm.

[0008] According to one embodiment, at least a first portion is entirely undoped.

[0009] According to one embodiment, at least a first portion is doped with a single type of conductivity.

[0010] According to one embodiment, the first stack is of the silicon-on-insulator type that is completely depleted.

[0011] According to one embodiment, the second layer comprises at least a second portion in and on which active components are formed.

[0012] According to one embodiment, at least a first portion is located opposite a passive component formed in the stack.

[0013] According to one embodiment, each first portion is configured to be biased by a bias voltage.

[0014] According to one embodiment, the bias voltage is chosen so as to optimize the effective resistivity seen by the passive component.

[0015] According to one embodiment, the bias voltage is chosen so as to control power losses.

[0016] One embodiment provides an electronic device comprising a first silicon-on-insulator stack, the first stack comprising a first lower semiconductor layer, a second upper semiconductor layer and a third insulating layer separating the first lower semiconductor layer and the second upper semiconductor layer, the second upper semiconductor layer comprising at least a first portion, each first portion not comprising an active component; and a second stack of fourth insulating layers in which conductive tracks and conductive vias are located, the second stack covering the second upper semiconductor layer, each first portion being configured to be biased by a bias voltage.

[0017] Another embodiment provides a method for manufacturing an electronic device comprising a first silicon-on-insulator stack, the first stack comprising a first lower semiconductor layer, a second upper semiconductor layer, and a third insulating layer separating the first and second layers, the second layer comprising at least a first portion, each first portion not comprising an active component; and a second stack of fourth insulating layers in which conductive tracks and conductive vias are located, the second stack covering the second upper semiconductor layer, each first portion being configured to be biased by a bias voltage.

[0018] According to one embodiment, at least a first portion is located opposite a third portion of the stack of layers located between two conductive tracks. Brief description of the drawings

[0019] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0020] [Fig.1] represents an example of an electronic device;

[0021] [Fig.2] represents an embodiment of an electronic device;

[0022] [Fig.3] illustrates the operation of the embodiment of [Fig.2];

[0023] [Fig.4] illustrates the operation of the embodiment of [Fig.2];

[0024] [Fig. 5] illustrates the operation of the embodiment of [Fig. 2]; and

[0025] [Fig.6] represents another embodiment of an electronic device. Description of the implementation methods

[0026] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0027] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0028] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0030] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0031] The device is intended, for example, for use in communication equipment, or in computers and peripherals. For example, the device can be used in 5G infrastructure and dedicated data centers. The device includes, for example, silicon-based components such as CMOS field-effect transistors, CMOS bipolar transistors, resistors, electrostatic discharge protection devices, and transient voltage suppression diodes. The device can also be used in satellites, including, for example, integrated passive components for radio frequency applications such as transmission lines, inductors, transformers, filters, and couplers.

[0032] Figure 1 represents an example of an electronic device 10. The device 10 is, for example, a device in which signals are generated and / or transmitted. These signals are, for example, signals having a frequency between 3 kHz and 3 THz.

[0033] The device 10 comprises, in the example of [Fig. 1], a silicon-on-insulator (SOI) substrate 12, for example, a fully depleted silicon-on-insulator (FD-SOI) or partially depleted silicon-on-insulator (PD-SOI) substrate. In other words, the substrate 12 comprises a lower semiconductor layer 12a, an upper semiconductor layer 12b, and an insulating layer 12c (BOX - Buried Oxide). The insulating layer 12c is located between layers 12a and 12b. Layer 12a is, for example, made of silicon. Layer 12b is completely separated from layer 12a by layer 12c. Layer 12b comprises, for example, portions 12b1 of a semiconductor material, for example, silicon, and portions 12b2 of an insulating material. The 12b2 portions correspond for example to insulating walls, for example shallow insulating walls.Electronic components, for example active components, are formed in and on each portion 12b 1. For example, transistors, for example CMOS transistors, can be formed in and on each portion 12bl.

[0034] The device 10 further comprises passive components. For example, the device 10 comprises a stack 14 of insulating layers. The stack 14 corresponds, for example, to an interconnection network. The stack 14 comprises at least one layer 16 of an electrically insulating material and one layer 18 of an electrically insulating material. Layer 16 is the layer of the stack 14 closest to the substrate 12. Layer 16 is in contact with the substrate 12. Layer 18 covers layer 16.

[0035] Layer 18 includes, for example, conductive tracks. Layer 16 includes, for example, conductive vias for electrically connecting the conductive tracks to layer 12b. Stack 14 includes, for example, other insulating layers located on layers 16 and 18, said other layers including for example conductive tracks or conductive vias.

[0036] Figure 1 includes a conductive track 20 located in layer 18. The track 20, in association with a reference plane, constitutes, for example, a coplanar waveguide for conducting radio frequency waves. The reference plane is, for example, another conductive track of the stack 14. The reference plane preferably constitutes the mass of the device.

[0037] In order to limit losses at the waveguide and parasitic effects, it is important that the effective resistivity seen by the waveguide be high, for example greater than 100 Ω·cm, or for example greater than 1000 Ω·cm. The effective resistivity seen by the waveguide is understood to be the resistivity seen by the waveguide in device 10 during the operation of device 10. This effective resistivity depends greatly on the resistivity of the substrate 12.

[0038] One way to attempt to increase the effective resistivity seen by the waveguide is to choose a high-resistivity material to form the substrate 12, and in particular the layer 12a. More precisely, the material of the substrate 12 is chosen so as to have a nominal resistivity greater than 300 Ω·cm. By nominal resistivity, we mean the resistivity of the material alone, independent of the context or device in which the material is located.

[0039] Parasitic fixed charges are formed in layer 12a at the interface with layer 12c. These charges are generated by the substrate manufacturing process or during the fabrication of the electronic devices. These fixed charges induce the creation of an opposite type of charge of free carriers, which modifies the conductivity in the substrate. Thus, positive fixed charges induce the creation of a negative charge of free carriers, and negative fixed charges induce the creation of a positive charge of free charges. This mechanism is known as parasitic surface conduction (PSC). In the example in [Fig. 1], this is represented by a region 13 of layer 12a. Region 13 corresponds to the region of layer 12a in which mobile free charges are present. The concentration of mobile free charges is represented by the shade of gray in region 13.The darker the color, the higher the concentration of charges, for example electrons. A region with a high concentration of free mobile charges, and therefore highly conductive, is thus formed at the interface with layer 12c. The presence of this highly conductive region decreases the local resistivity of the substrate at the interface between layers 12a and 12c, and in particular decreases the effective resistivity seen by the waveguide located in layer 18. For example, the highly conductive region 13 leads to a decrease in the resistivity of substrate 12 at the interface by a... factor between 103 and 106. The effective resistivity seen by the waveguide is consequently reduced by a factor between 10 and 104.

[0040] Thus, the use of a substrate with a high nominal resistivity, for example between 300 Q.cm and 10 kQ.cm, does not result in a significant improvement compared to a substrate with a lower nominal resistivity, for example substantially equal to 10 Q.cm.

[0041] Figure 2 represents an embodiment of an electronic device 22. Device 22 is, for example, a device in which radio frequency signals are generated and / or transmitted.

[0042] The device 22 comprises a substrate, or stack, 24 of the silicon-on-insulator (SOI) type, for example, of the fully depleted silicon-on-insulator (FD-SOI) type or of the partially depleted silicon-on-insulator (PD-SOI) type. In other words, the stack 24 comprises a lower semiconductor layer 26, an upper semiconductor layer 28, and an insulating layer 30 (BOX - Buried Oxide). The insulating layer 30 is located between layers 26 and 28. Layer 26 is, for example, made of silicon. Layer 28 is, for example, made of silicon. Layer 28 is thus completely separated from layer 28 by layer 30. Layer 30 has a thickness of less than 30 nm, preferably less than 25 nm, for example, substantially equal to 25 nm. In other words, the maximum distance between layers 26 and 28 is preferably less than 30 nm, preferably less than 25 nm.

[0043] The lower layer 26 is preferably made of a highly resistive material. The layer 26 has, for example, a nominal resistivity greater than 100 Q.cm, for example greater than 500 Q.cm.

[0044] The upper layer 28 comprises, for example, portions 28a, only one of which is shown in [Fig. 2], in and on which electronic components are formed, for example, active components, for example, transistors, for example, CMOS-type transistors. The portions 28a thus comprise doped regions not shown. The portions 28a thus comprise, for example, P-doped regions and N-doped regions. The portions 28a extend over the entire height of the layer 28. Thus, the portions 28a are in contact with the layer 30 by their lower face and with the stack 32, more precisely with the layer 34, by their upper face.

[0045] The upper face of the lower layer 26, that is, the face in contact with layer 30, is preferably flat. The upper and lower faces of layer 30, that is, the faces in contact with layers 26 and 28, are preferably flat and parallel to each other. The upper and lower faces of layer 28, that is The faces in contact with layers 30 and 34 are preferably flat and parallel to each other.

[0046] The device 22 may include passive components. For example, the device 22 includes a stack 32 of insulating layers. The stack 32 corresponds, for example, to an interconnection network. The stack 32 includes at least one layer 34 made of an electrically insulating material and a layer 36 made of an electrically insulating material, for example, a material different from that of layer 34. Layer 34 is the layer of the stack 32 closest to the stack 24. Layer 34 is preferably in contact with the upper layer 28. Layer 36 covers layer 34 and is preferably in contact with layer 34.

[0047] Layer 36 includes, for example, conductive tracks. Layer 34 includes, for example, conductive vias for electrically connecting the conductive tracks to each other or to layer 28. Stack 32 includes, for example, other insulating layers not shown located on layers 34 and 36, said other layers being separated from stack 24 by layers 34 and 36. The layers not shown include, for example, conductive tracks or conductive vias.

[0048] Figure 2 includes a conductive track 38 located, in the example of Figure 2, in layer 36. More generally, the track 38 can be located in any layer of the stack 32, preferably other than layer 34. The track 38 constitutes, for example, an electrical connection between two active components of the device 22. The track 38 constitutes, for example, a passive component of the device 22. The track 38 is, for example, part of a coplanar waveguide intended to conduct radio frequency waves. The track 38 is, for example, elongated, i.e., having the shape of a rectangular parallelepiped. Alternatively, the track 38 can have a spiral shape. The track 38 can constitute an inductor.

[0049] The layer 28 comprises at least one semiconductor portion 28b. The portion 28b is made of the same material as the portions 28a. The portion 28b extends over the entire height of the layer 28. Thus, the portion 28b is in contact with the layer 30 by its lower face and with the stack 32, more precisely with the layer 34, by its upper face.

[0050] Portion 28b is, for example, undoped. Portion 28b is preferably uniformly undoped. In other words, portion 28b is entirely undoped.

[0051] Alternatively, portion 28b may be doped with a conductivity type, P or N. Preferably, portion 28b is uniformly doped. That is, portion 28b is fully doped, and each region of portion 28b has substantially the same concentration of dopants. Portion 28b does not contain any active components.

[0052] Each portion 28b is surrounded by an electrically insulating region 40. The regions 40 are located within the level of the layer 28. Thus, the regions 40 extend over the entire height of the layer 28. The regions 40 thus extend, for example, only from the upper face of the layer 28 to the lower face of the layer 28. The portions 28b are separated from the portions 28a by the regions 40.

[0053] According to the embodiment of [Fig. 2], at least one portion 28b is located opposite at least a part of a passive component. In other words, at least one portion 28b is located directly above, or vertically aligned with, at least a part of a passive component. In other words, at least one portion 28b is located between at least a part of an active component and layer 26. For example, track 38 is not located opposite a shallow insulating trench (SIT) type insulating region, such as region 40. For example, portion 28b is opposite the entirety of a passive component. For example, portion 28b is located opposite a component intended to generate or transmit electromagnetic waves whose frequencies are in the radio frequency range. For example, a portion 28b is located opposite at least a part of a waveguide, for example opposite the entire waveguide.For example, a portion 28b is located opposite at least part of an inductor, for example, opposite the entire inductor, the inductor being, for example, formed by conductive tracks in a layer of the stack 32. For example, a portion 28b is located opposite at least part of a radio frequency switch. For example, a portion 28b is located opposite at least part of an oscillator. For example, a portion 28b is located opposite at least part of a transmitter, for example, a radio frequency transmitter. For example, in a radio frequency transmitter, a portion 28b is located opposite at least one power amplifier and / or at least one low-noise amplifier and / or at least one switch. For example, a portion 28b is located opposite at least part of an antenna.

[0054] By the expression "a portion 28b is located opposite an element", the element being for example a component or a portion of a circuit, it is understood that said element is separated from layer 26 by the portion 28b, preferably completely separated.

[0055] A portion 28b is, for example, located opposite a single component. Alternatively, the same portion 28b may be located opposite several components. For example, the same portion 28b may be located opposite several components of the same type, for example, opposite several waveguides or several inductors. For example, the same portion 28b may be located opposite several different components. For example, the same portion 28b can be located opposite several components located in different layers of stack 32.

[0056] The portion 28b is for example biased at a voltage Vfe with respect to the layer 26. In other words, the voltage Vfe corresponds to the potential difference between the portion 28b and the layer 26. The device 22 includes for example a set of conductive tracks and conductive vias, one of the conductive vias being in contact with the portion 28b, allowing the portion 28b to be connected to a source of the voltage Vfe.

[0057] Portion 28b enables field-effect passivation, thereby inhibiting the parasitic surface conduction effect. Thus, portion 28b allows for the local depletion of the interface between layer 26 and layer 30. Indeed, the charges form a channel-like structure at the interface between layers 26 and 30. Applying the voltage Vfe to portion 28b modifies the conductivity of the region of layer 26 located opposite portion 28b.

[0058] According to one embodiment, the value of the voltage Vfe is chosen so as to counteract the conductivity of the layer 26 and ensure that the effective resistivity seen by the passive component, i.e. by the component located opposite the portion 28b, for example a waveguide, is maximized, for example is not attenuated by the conductive region of the layer 26. The power transmitted, for example during the transmission of a radio frequency wave, by the conductive track 38 is thus maximized.

[0059] According to another embodiment, the value of the voltage Vfe is chosen so as to modulate, or control, the conductivity of layer 26. The value of the voltage Vfe is thus chosen so as to modulate, by a desired proportion, the power transmitted by track 38.

[0060] Different portions 28b of the device 22 can be biased to different values ​​of Vfe, depending on whether it is desired to counteract or attenuate the effect of the conductivity of the layer 26 on the component opposite portion 28b.

[0061] The manufacturing process for device 22 of [Fig.2] comprises: - the formation of an SOI stack, comprising the lower semiconductor layer 26, the insulating layer 30 completely covering the upper face of the layer 26, and the upper semiconductor layer 28 completely covering the upper face of the layer 30; - the engraving of layer 28 outside the locations of portions 28a and 28b, in particular at the locations of regions 40; - the formation of regions 40; - the formation of active components in portions 28b; and - the formation of the stack 32 on the top face of the layer 28, in particular forming the conductive tracks and conductive vias allowing the portions 28b to be connected to voltage sources and forming the passive components.

[0062] Figure 3 illustrates the operation of the embodiment of Figure 2. More specifically, Figure 3 illustrates the ratio S21 between the transmitted power and the incident power, in dB, relative to a waveguide implemented by conductive tracks 38 of Figure 2, one of the tracks 38 being located opposite portion 28b, as a function of the frequency F, in GHz. Figure 3 includes curves corresponding to several values ​​of the voltage Vfe.

[0063] Figure 3 comprises curves C1, C2, C3, C4, and C5. Curve C1 corresponds to a value of the voltage Vfe, for example -1.6 V, lower than the value of the voltage Vfe, for example -1.2 V, corresponding to curve C2. Curve C2 corresponds to a value of the voltage Vfe, for example -1.2 V, lower than the value of the voltage Vfe, for example -0.8 V, corresponding to curve C3. Curve C3 corresponds to a value of the voltage Vfe, for example -0.8 V, lower than the value of the voltage Vfe, for example -0.4 V, corresponding to curve C4. Curve C4 corresponds to a value of the voltage Vfe, for example -0.4 V, lower than the value of the voltage Vfe, for example 0 V, corresponding to curve C5.

[0064] It can be observed that, in this voltage range, the lower the value of the voltage Vfe, the lower the ratio S21. Furthermore, the curves Cl to C5 are distinct from one another. Therefore, by choosing the value of the voltage Vfe, it is possible to choose the attenuation of the power transmitted in the waveguide implemented by tracks 38.

[0065] Figure 4 illustrates the operation of the embodiment of Figure 2. More Specifically, [Fig.4] illustrates the effective resistivity peff, in Q.cm, seen by the conductive track 38 of [Fig.2], located opposite portion 28b as a function of the frequency F, in GHz, of the signal transmitted by track 38. [Fig.4] includes curves corresponding to several values ​​of the voltage Vfe.

[0066] Figure 4 includes curves D1, D2, D3, D4, D5. Curve D1 corresponds to A value of the voltage Vfe, for example -1.6 V, lower than the value of the voltage Vfe, for example -1.2 V, corresponding to curve D2. Curve D2 corresponds to a value of the voltage Vfe, for example -1.2 V, lower than the value of the voltage Vfe, for example -0.8 V, corresponding to curve D3. Curve D3 corresponds to a value of the voltage Vfe, for example -0.8 V, lower than the value of the voltage Vfe, for example -0.4 V, corresponding to curve D4. Curve D4 corresponds to a value of the voltage Vfe, for example -0.4 V, lower than the value of the voltage Vfe, for example 0 V, corresponding to curve D5. Figure 4 further includes a curve D6 corresponding to the effective resistivity, in Q.cm, seen by the conductive track 38 of [Fig.2] in the absence of the portion 28b.

[0067] Figure 5 illustrates the operation of the embodiment of Figure 2. More specifically, Figure 5 illustrates the power losses α, in dB / mm, during the transmission of a signal in a waveguide implemented by conductive tracks 38 of Figure 2, located opposite portion 28b, as a function of the frequency F, in GHz. Figure 5 includes curves corresponding to several values ​​of the voltage Vfe.

[0068] Figure 5 comprises curves E1, E2, E3, E4, and E5. Curve E1 corresponds to a value of the voltage Vfe, for example -1.6 V, lower than the value of the voltage Vfe, for example -1.2 V, corresponding to curve E2. Curve E2 corresponds to a value of the voltage Vfe, for example -1.2 V, lower than the value of the voltage Vfe, for example -0.8 V, corresponding to curve E3. Curve E3 corresponds to a value of the voltage Vfe, for example -0.8 V, lower than the value of the voltage Vfe, for example -0.4 V, corresponding to curve E4. Curve E4 corresponds to a value of the voltage Vfe, for example -0.4 V, lower than the value of the voltage Vfe, for example 0 V, corresponding to curve E5. [Fig.5] further includes a curve E6 corresponding to the power losses a, in dB / mm, during the transmission of a signal in a waveguide implemented by conductive tracks 38 of [Fig.2] in the absence of portion 28b.

[0069] With reference to Figures 4 and 5, it can be observed that, in this voltage range, the lower the value of the Vfe voltage, the higher the effective resistivity and the lower the transmitted power losses. Therefore, by choosing the value of the Vfe voltage, it is possible to choose the effective resistivity seen by a waveguide implemented with tracks 38 and the power losses during the transmission of a signal in such a waveguide.

[0070] Figure 6 represents another embodiment of an electronic device 42. The device 42 is, for example, a device in which radio frequency signals are generated and / or transmitted.

[0071] Device 42 comprises elements of device 22 of [Fig. 2]. More specifically, device 42 comprises: - the SOI-type stack 24, and therefore includes the upper layer 28 and lower layer 26 and the insulating layer 30; and - stacking 32, including in particular layers 34 and 36.

[0072] Device 42 further includes, like device 22 of [Fig.2], portions 28a and 28b of layer 28, only a portion 28b being shown in [Fig.6].

[0073] Device 42 includes, like device 22 of [Fig. 2], conductive tracks located in the layers of the stack 32. Thus, device 42 [Fig. 6] comprises two conductive tracks 44 and 46. In [Fig. 6], tracks 44 and 46 are in the same layer of the stack 32. More generally, tracks 44 and 46 may be located in different layers of the stack 32 and may be in layers of the stack 32 other than layer 36. In the case where tracks 44 and 46 are in the same layer 36, they are separated by a portion 48 of the layer 36. Portion 48 is made of the insulating material of the layer 36. Portion 48 preferably does not include a conductive track. More generally, portion 28b is preferably located opposite a portion of the stack 32 that does not include a conductive track.

[0074] Device 42 of [Fig. 6] differs from device 22 of [Fig. 2] in that at least one portion 28b is located opposite portion 48. Said portion 28b is not located opposite runways 44 and 46. Preferably, portion 28b is not located opposite any conductive runway. Preferably, the distance D between the portion of portion 48 located opposite portion 28b and runways 46 and 48 is less than 0.5 pm.

[0075] In the embodiment of [Fig. 6], portion 28b allows the conductive tracks 44 and 46 to be isolated. More specifically, portion 28b allows the power ratio transmitted between track 44 and track 46 to be controlled and minimized so as to isolate tracks 44 and 46.

[0076] One advantage of the described embodiments is that they counteract the effects of parasitic surface conduction that lead to the generation of the conductive region of layer 26. This makes it possible to maximize the transmitted power in integrated waveguides. It also makes it possible to minimize resistive losses due to Joule heating in the semiconductor electromagnetic environment of active and passive circuits.

[0077] Another advantage of the described embodiments is that it is possible to attenuate the power transmitted in passive components such as waveguides by choosing the value of the voltage Vfe.

[0078] Another advantage of the described embodiments is that their manufacturing process does not require the use of additional masks compared to the formation of a device comprising an SOI-type stack and components formed in and on the upper semiconductor layer of the stack.

[0079] Another advantage of the described embodiments is that they allow for a reduction in the thickness of the stacks 32. Indeed, one way to compensate for the power loss is to form thick stacks 32. Thanks to the described embodiments, the thickness of the stack 32 can be reduced while maintaining the same efficiency.

[0080] Another advantage of the described embodiments is that it is possible, by using signal attenuation, to compensate for variations between the nominal resistivities of different substrates that can be used to form multiple iterations of the same device.

[0081] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0082] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic device (22) comprising: - a first stack (24) of the silicon-on-insulator type, the first stack (24) comprising a first lower semiconductor layer (26), a second upper semiconductor layer (28) and a third insulating layer (30) separating the first lower semiconductor layer (26) and the second upper semiconductor layer (28), the second upper semiconductor layer (28) comprising at least a first portion (28b), each first portion (28b) not comprising an active component; and - a second stack (32) of fourth insulating layers (34, 36) in which conductive tracks (38) and conductive vias are located, the second stack covering the second upper semiconductor layer, at least a first portion (28b) is located opposite a conductive track (38).

2. Device according to claim 1, wherein the thickness of the third layer (30) is less than 30 nm.

3. Device according to claim 1 or 2, wherein the nominal resistivity of the first layer (26) is greater than 100 Q.cm.

4. Device according to any one of claims 1 to 3, wherein at least a first portion (28b) is entirely undoped.

5. Device according to any one of claims 1 to 3, wherein at least a first portion (28b) is doped with a single type of conductivity.

6. Device according to any one of claims 1 to 5, wherein the first stack is of the fully deserted silicon-on-insulator type.

7. Device according to any one of claims 1 to 6, wherein the second layer (28) comprises at least a second portion (28a) in and on which active components are formed.

8. Device according to any one of claims 1 to 7, wherein at least a first portion (28b) is located opposite a passive component formed in the stack.

9. Device according to any one of claims 1 to 8, wherein each first portion (28b) is configured to be biased by a bias voltage (Vfe).

10. Device according to claim 9, wherein the bias voltage (Vfe) is chosen so as to optimize the effective resistivity seen by the passive component.

11. Device according to claim 9 or 10, wherein the bias voltage (Vfe) is chosen so as to control power losses.

12. A method for manufacturing an electronic device (22) comprising: - a first stack (24) of the silicon-on-insulator type, the first stack (24) comprising a first lower semiconductor layer (26), a second upper semiconductor layer (28) and a third insulating layer (30) separating the first (26) and second (28) layers, the second layer (28) comprising at least one first portion (28b), each first portion (28b) not comprising an active component; and - a second stack (32) of fourth insulating layers (34, 36) in which conductive tracks (38) and conductive vias are located, the second stack covering the second upper semiconductor layer, the method comprising the formation of at least one first portion (28b) located opposite a conductive track (38).

13. The method according to claim 12 applied to the manufacture of a device according to any one of claims 1 to 11.

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