Automatic synchronization circuit for semiconductor memory device and memory device

Abstract

A memory circuit (MEM) comprising a bit cell array (ARR) arranged in rows of bit cells connected to respective word lines (WL) and in columns of bit cells connected to respective bit lines (BL); a detection amplifier circuit (S-Amp) to be connected to the bit lines; an external clock input (In1) supplied by an external clock signal (Ext-Clck) comprising external clock pulses of a first duration; and a synchronization circuit (T-Cntl) to track the load time of one of the bit lines, which is a second duration. The synchronization circuit (T-Cntl) generates an internal clock signal (Int-Clk) comprising internal clock pulses (Int-ClckPulse) and transmits the internal clock signal to the detection amplifier circuit (S-Amp). The internal clock pulses have a width defined as the longer of the first and second durations. Fig. 3

Description

Title of the invention: Automatic synchronization circuit for semiconductor memory device and memory device. FIELD OF THE INVENTION

[0001] The technical field of the invention is that of random access memory (RAM) cells, each of which comprises an element whose state defines a bit of information which is read or written according to sequences of operations. TECHNOLOGICAL BACKGROUND

[0002] In a memory such as random access memory (RAM), precise synchronization of operations is essential to ensure the correct execution of read and write operations. The synchronization and propagation of the various signals directly influence the speed and reliability of data writing or retrieval.

[0003] During a typical read operation, a read word line is activated, causing the connected memory cells to supply their stored data, or bits, as voltages to the respective bit lines. This data is detected by means of detection amplifiers, which must be activated at specific times to ensure that the bit line voltages are detected and processed safely. To this end, a memory synchronization circuit plays a crucial role by generating synchronization signals that determine when the detection amplifiers should be activated.

[0004] However, practical factors such as variations in the manufacturing process and use of memory, known as PVT (Process, Voltage and Temperature) variations, introduce variations in signal propagation and the load of word and bit lines, which affects memory operations, particularly read operations.

[0005] Process variations arise from the manufacturing process of the memory, which consists of a chip embedded in a semiconductor wafer. During wafer processing, unavoidable variations occur depending on the chip's location on the wafer and the difficulty of precisely reproducing the same manufacturing parameters, particularly when considering small technological nodes. Examples include the UV light wavelength, oxide thickness, electric charge carrier mobility, transistor channel lengths, metal thickness, diffusion depths, etc. Voltage variations arise from voltage drops across the electrical network within the memory, noise due to parasitic inductances, irregularities in the voltage supplied by a voltage regulator on the chip, and so on. Example. Temperature variations can be due to the non-uniform density of transistors or to switching throughout the memory.

[0006] Consequently, the circuit components forming the memory can be associated with respective resistances R and capacitances C, so that each component exhibits an individual "RC characteristic." These RC characteristics govern the propagation of signals within the memory, for example, along the bit and word lines. Among chips from the same wafer and thus having undergone nominally identical processing, some chips may therefore propagate signals faster than others. The former are sometimes called "fast corners," while the latter are sometimes called "slow corners." Taking signal propagation speed into account is essential for obtaining high-performance memories, as they rely heavily on time-dependent operations.

[0007] To cope with the consequences of these uncontrolled variations in memory, synchronization circuits that are resistant to PVT variations are required. These circuits must be capable of maintaining precise synchronization of operations despite environmental and operational changes. The synchronization circuits can be designed to track or emulate signals using dummy word lines and / or dummy bit lines to generate appropriate synchronization signals.Reference can be made, for example, to patent documents US 6181626 Bl, US 6646938 B2, US 20150063046 Al, EP 0422939 Bl, US6388931 or US 2008205176 AL. These circuits are widely used to control similar circuits from slow corners and fast corners, so differences in their effective characteristics do not affect how they are controlled, which can then be applied to all memories, regardless of whether they are "fast" or "slow".

[0008] However, it is still necessary to improve and simplify the control of read operations in a memory circuit, taking into account the individual characteristics of the memories, even memories sharing the same design. OBJECT OF THE INVENTION

[0009] In the context described above, it is proposed to improve the control of the width of a synchronization pulse used to control the locking of a detection amplifier in a memory circuit. Description of the invention

[0010] To this end, a first aspect of the invention relates to a memory circuit comprising: a matrix of bit cells arranged in rows of bit cells, each connected to a word row, and in columns of bit cells, each connected to a bit line, the word lines being connected to a word line driver circuit, the bit lines being connected to a multiplexer circuit; a detection amplifier circuit configured to be connected to the bit lines, an external clock input configured to be fed by an external clock signal comprising external clock pulses having a first duration, and a synchronization circuit configured to track the time required to load one of the bit lines and which is a second duration, the synchronization circuit being configured to generate an internal clock signal comprising internal clock pulses and transmit the internal clock signal to the detection amplifier circuit, the internal clock pulses having a width defined as the longer of the first duration and the second duration.

[0011] Advantageously, this memory circuit allows automatic adaptation of an internal clock signal to variations in memories having the same design. This clock signal is used to determine the correct time to activate the detection amplifier circuit, that is, when the bit lines are fully loaded during a read operation.

[0012] The circuit is suitable for use in memory circuits, whether they are "fast-angle" or "slow-angle," meaning that signals propagate through them faster or slower than a typical propagation speed. Furthermore, the circuit can be easily adapted to arrays of bit cells with an arbitrary number of rows and columns.

[0013] Furthermore, this circuit does not require the user to control a clock signal or choose between different clock signals by means of an additional control signal and an additional circuit dedicated to this function, since the circuit according to the invention automatically emits a clock signal adapted to the circumstances.

[0014] According to other non-limiting features of the first aspect of the invention, whether taken in isolation or in any technically possible combination:

[0015] - the memory circuit can be configured to drive respective voltages of the bit lines as a function of the data stored in the bit cells respectively connected to the bit lines during a read operation of the memory circuit;

[0016] - the synchronization circuit can be configured to track the time required to load one of the first lines by following the time required to load a dummy bit line (DBL) and which is representative of the time required to load the bit lines;

[0017] - the memory circuit may include: a dummy word line; and a first dummy line; the synchronization circuit including a reset signal generation circuit configured to generate and send a pulse reset signal when a voltage on the first dummy line reaches a given threshold; a pulse generation circuit having a first input connected to the external clock input and a second input configured to receive the pulse reset signal, the pulse generation circuit is configured (i) to generate and send a trigger signal to load the dummy word line in response to a pulse from the external clock signal and (ii) to generate a pulse generation signal comprising a pulse starting with the pulse from the external clock signal and ending upon receipt of the pulse reset signal; and a pulse width determination circuit configured to receive (i) the external clock signal and (ii) the pulse generation signal, the selection circuit being further configured to generate and output the internal clock signal;

[0018] - the pulse width determination circuit can be configured to execute an OR logic gate function with the external clock signal and the pulse generation signal as inputs and the internal clock signal as output;

[0019] - the memory circuit may further include a line emulation circuit dummy bit connected to the dummy bit line and configured to emulate an environment of one of the bit lines of the bit cell matrix so that the load of the dummy bit line takes substantially the same time as the load of one of the bit lines;

[0020] - the memory circuit may further include a line emulation circuit dummy word connected to the dummy word line and configured to emulate an environment of one of the word lines of the bit cell matrix so that a signal propagates substantially identically along the dummy word line and along one of the word lines;

[0021] - The memory circuit may also include a configured delay circuit to delay the pulse generation signal generated by the pulse generation circuit before the pulse generation signal reaches the pulse width determination circuit; and

[0022] - the memory circuit may be a resistive RAM.

[0023] The present invention extends to an embedded system comprising the memory circuit according to the first aspect of the invention, connected to a microprocessor. BRIEF DESCRIPTION OF THE FIGURES

[0024] Many other features and advantages of the present invention will become apparent from the following detailed description, considered together with the accompanying drawings, in which:

[0025] [Fig.1] The [Fig.1] illustrates a conventional memory;

[0026] [Fig.2] Fig.2 illustrates the conventional memory of Fig.1 equipped with circuits according to the invention;

[0027] [Fig.3] Fig.3 illustrates a functional diagram of the circuits of Fig.2 added to the memory of the [Fig.l];

[0028] [Fig.4] The [Fig.4] illustrates a pulse width determination circuit;

[0029] [Fig.5] The [Fig.5] illustrates part of a bit line emulation circuit;

[0030] [Fig.6] The [Fig.6] illustrates part of a word line emulation circuit;

[0031] [Figure 7 illustrates another part of the bit line emulation circuit;

[0032] [Fig.8] Fig.8 is a time-domain diagram of the circuit operation of the [Fig.3] in a slow corner situation; and

[0033] [Fig.9] Fig.9 is a time-domain diagram of the circuit operation of the [Fig.3] in a fast corner situation; and

[0034] [Fig. 10] The [Fig. 10] illustrates an embedded system integrating a resistive memory MEM.

[0035] The figures are schematic representations which, for the sake of clarity, are not to scale. DETAILED DESCRIPTION OF THE INVENTION

[0036] [Fig. 1] illustrates (A) a generic architecture for random access memory (RAM) with a matrix of bit cells BC arranged in rows of bit cells BC, each connected to a respective word line WL, and in columns of bit cells BC, each connected to a respective pair of lines, designated in this specific example as a first line or bit line, annotated BL, and as a second line or source line, annotated SL, the word lines WL being connected to a word line driver circuit WL-Drv, the bit lines BL and the source lines SL being connected to a multiplexer circuit SL / BL-Mux, a detection amplifier circuit S-Amp being connected to the bit lines via the multiplexer circuit SL / BL-Mux. In a memory matrix such as that illustrated in [Fig. 1]l](A), a bit line is a circuit component that is strongly driven to a desired value to read or write data stored in bit cells connected to it.

[0037] The adjustment, reset, and read operations can be applied to the bit cells integrated into an ARR matrix of a resistive RAM (ReRAM) memory. Figure 1(A) is representative of the conventional structure of a resistive RAM memory, or ReRAM. Such a resistive RAM memory is described, for example, in US patent 11735260B2.

[0038] In the RAM of [Fig. 1], each bit cell BC of the ARR matrix comprises a resistor ReRAM VarR composed of a pair of electrodes ELI and EL2 sandwiching, for example, an oxide layer OL, and a SelTrayant selection transistor a source and a drain connected in series with the ReRAM resistor, as illustrated in [Fig.1](B).

[0039] An ARR bit cell matrix comprises columns and rows of bit cells. Each column comprises (i) a bit line BL connected to a source and drain of the SelTr transistor via the ReRAM VarR resistor for each bit cell in the column, and (ii) a source line SL connected to the bit line BL via the source and drain of the SelTr transistor and the ReRAM VarR resistor. Each row of bit cells comprises a word line WL connected to the gate of the SelTr selector transistor for each bit cell in the row. The bit lines BL and the source lines SL are each connected to and controlled by a column multiplexer circuit SL / BL-Mux. The word lines WL are each connected to and controlled by a line driver circuit WL-Drv.

[0040] In [Fig. 1](A), each intersection between a word line WL and a bit line BL corresponds to a bit cell BC. [Fig. 1](C) illustrates two adjacent bit cells BC1 and BC2 belonging to the same row and therefore connected to the same word line WL.

[0041] The generic architecture illustrated in [Fig.1] does not, by itself, allow the problems related to variations in the PVT to be solved.

[0042] Figure 2 illustrates the MEM memory circuit of Figure 1, into which a dummy bit line (DBL), a dummy word line (DWL), and a T-Cntl synchronization circuit connected to the dummy bit line, the dummy word line, and the S-Amp detection amplifier circuit have been integrated. The T-Cntl synchronization circuit is also connected to the memory lines necessary for the normal operation of the circuit (clock signal transmission lines, high or low voltage lines, ground, control signal lines, etc.). In particular, a clock signal external to the T-Cntl synchronization circuit is identified as an external clock signal and comprises pulses of a given and constant width generated at constant intervals. It goes without saying that the intervals and the pulse width represent respective durations and can be expressed in nanoseconds.

[0043] The dummy lines and the synchronization circuit are configured to (i) track the time required to load one of the bit lines and (ii) generate an internal clock signal Int-Clk comprising internal clock pulses and to transmit the internal clock signal to the detection amplifier circuit S-Amp and other signals which are clock-dependent, the internal clock pulses having a width defined as the longer of the pulse widths of the external clock signal and the time required to load one of the bit lines.

[0044] Indeed, due to variations in PVT, the time required to load the bit lines can vary from one memory to another, hence the need to evaluate the time This is indeed necessary to load the bit lines and thus reliably perform a read operation. Specifically, if the detection amplifier circuit is activated before the bit lines are fully loaded, there is a risk of an incomplete read of the memory contents. Conversely, if the clock signal is slowed down to prevent incomplete loading of the bit lines, memory reading will be slower than necessary in many cases.

[0045] The synchronization control circuit resolves this problem by lengthening the read operation time only when necessary, by lengthening the pulses of an internal clock signal when the pulses of the external clock line are too short to allow complete loading of the bit lines, as evaluated by monitoring the actual time required to load a bit line. In this embodiment, the monitoring is performed on the dummy bit line DBL, which is not connected to the bit cells of the memory bit cell array. This dummy bit line is loaded by means of the dummy word line DWL, which is not connected to the bit cells of the memory bit cell array.In other words, the dummy bit line and the dummy word line operate independently of the bit cells, except that their operation depends on the external clock signal and the voltages supplying the bit cell array and the circuits connected to it.

[0046] The dummy bit line and the dummy word line preferably behave similarly to the bit lines and word lines of the bit cell matrix with respect to signal propagation along these lines. To this end, the environments of the dummy lines are arranged as follows: a bit line emulation circuit Emul.BL is preferably connected to the dummy bit line DBL. Similarly, a word line emulation circuit Emul.WL is preferably connected to the dummy word line DWL. More specifically, these emulation circuits can reproduce the electrical capacitances that are connected to any circuit in any real implementation of that circuit, and represent, for example, the parasitic capacitances that must be charged when the bit lines and word lines are to be loaded.

[0047] Thus, the Emul.WL word line emulator circuit and the Emul.WL word line emulator circuit emulate the capacitances connected to a bit line and a word line of the bit cell array, respectively. The capacitances depend on the exact characteristics (dimensions, thicknesses, geometries, etc.) of the components connected to the bit line, such as connecting lines and transistors. These capacitances may vary from one memory to another due to slight variations occurring during the manufacturing processes, even if their design is strictly identical.

[0048] Fig. 3 illustrates the T-Cntl synchronization circuit, as well as the DBL dummy bit line, the DWL dummy word line, the S-Amp detection amplifier circuit (all clock-dependent circuits), the Emul.BL bit line emulation circuit and the Emul.WL word line emulation circuit.

[0049] The bit-line emulation circuit may include dummy bit cells DBCbl, as illustrated in [Fig. 5]. The dummy bit cells DBCBL preferably correspond in number to the bit cells BC connected to one of the bit lines BL in the ARR matrix and are preferably connected along the dummy bit lines DBL to match the connections of the bit cells BC to the bit lines BL. Each dummy bit cell DBCBL may include a TrBL transistor, the TrBL transistors being connected to the dummy bit line DBL via one of their sources and drains so as to emulate the electrical environment of a bit line BL of the ARR matrix. The gates and the other part of the source and drain may be connected to ground.In this way, the capacity actually connected to any one of the bit lines can be closely approximated, and an emulating environment, for the dummy bit line, the environment of the bit lines is reproduced.

[0050] Furthermore, as illustrated in [Fig. 7], the dummy bit line emulation circuit may optionally include TrAdj pmos transistors arranged to selectively connect the dummy bit line DBL to a voltage Vdd. As illustrated, the dummy bit line DBL may be connected to one of the sources and one of the drains of each of the TrAdj transistors, and the body and the other source and drain of each of the TrAdj transistors may be connected to a line at the voltage Vdd. All or some of the TrAdj transistors may be controlled by a user, in this example by means of three inputs In1, In2, and In3 into respective LG control logic gates (in this example, OR logic gate). More generally, n inputs may be used when n is a natural number, depending on the number of TrAdj transistors to be controlled. The circuit in [Fig.[7] includes a TrAdj transistor with a gate connected to the dummy word line DWL via an INV inverter to provide a basic capacitance to the dummy bit line DBL. A second Dwl_neg input of each of the LG control logic gates is connected to the dummy word line (not shown in the figure) via the INV inverter in this example. The outputs of the control logic gates are connected to the gates of the TrAdj transistors. The total amount of capacitance actually connected to the dummy bit line can therefore be controlled, allowing adjustment of the bit line rise time for a given memory and compensating for variations between memories, even if they have the same design.

[0051] Similar to the bit-line emulation circuit, the word-line emulation circuit may include dummy bit cells DBCWL, as illustrated in [Fig. 6]. The number of DBCWL dummy bit cells preferably corresponds to the number of BC bit cells connected to a WL word line in the ARR matrix, and they are preferably connected along the DWL dummy word lines to match the connections of the BC bit cells to the WL word lines. Each DBCWL dummy bit cell may include a TrWL transistor, the TrWL transistors being connected to the DWL dummy word line by their gates so as to emulate the electrical environment of a WL word line in the ARR matrix. The source and drain of the TrWL transistors may be connected.In this way, the capacity actually connected to any one of the word lines can be closely approximated, and an emulating environment, for the dummy word line, the environment of the word lines is reproduced.

[0052] The TrBL and TrWL transistors of the Emul.BL and Emul.WL emulation circuits preferably correspond, in terms of characteristics (geometry, dimensions...), to the transistors of the bit cells BC of the ARR matrix, in order to better reproduce the electrical environment of the bit lines and word lines.

[0053] More generally, the emulation circuits reproduce the RC characteristics of the bit lines and word lines as perceived by the memory circuit when it loads the bit lines during a read operation.

[0054] In the present example, the bit-line emulation circuit Emul.BL includes a control transistor TrCnt, which may be an NMOS transistor, one of whose sources and drain are connected to ground (GND), the other source and drain are connected to the dummy bit line (DBL), and one gate is connected to the dummy word line (DWL) via the inverter (INV). When the dummy word line is at a low voltage, the NMOS control transistor TrCnt connects the dummy bit line to ground, thus allowing it to discharge. When the dummy word line is at a high voltage, at least one of the PMOS transistors TrAdj charges the dummy bit line to Vdd.

[0055] As illustrated in [Fig.3], the T-Cntl synchronization circuit may include a Reset-Gen reset signal generation circuit, a Pulse-Gen pulse generation circuit and a Pulse-Width pulse width determination circuit, as well as a Del delay circuit.

[0056] The T-Cntl synchronization circuit has an Inl input to receive an external clock signal Ext-Clck, an In2 input to be connected to the dummy bit line DBL, and an Outl output to send the internal clock signal Int-Clck to the S-Amp detection amplifier circuit and other circuits that are functions of the clock.

[0057] The Reset-Gen signal generation circuit, connected to the dummy bit line DBL via input In2, is configured to generate and send a Pulse-Reset signal when a voltage on the first dummy line reaches a given threshold. This threshold can be predetermined and adjusted conventionally, for example by the dimensions of a transistor and / or the use of buffer circuits, etc.

[0058] The Reset-Gen signal generation circuit can also be configured to connect the dummy bit line (DBL) to a line set at voltage Vdd during a dummy bit line loading operation, for example, when a Stp-Trig trigger signal sent by the dummy word line (DWL) is at a logic high level. The Reset-Gen signal generation circuit can also be configured to connect the dummy bit line (DBC) to ground GND when the Stp-Trig trigger signal sent by the dummy word line (DWL) is at a logic low level. These functions can be achieved by connecting the dummy word line to the gate of a transistor that connects, via its source and drain, the dummy bit line to a line itself set at voltage Vdd or connected to ground GND.

[0059] The Pulse-Gen pulse generation circuit has a third input In3 connected to the external clock input In1 and a fourth input In4 configured to receive the Pulse-Reset pulse signal generated by the Reset-Gen signal generation circuit. The Pulse-Gen circuit can be configured (i) to generate a Stp-Trig trigger signal in response to a pulse from the external clock signal to load the dummy word line and (ii) to generate a Pulse-Gen-Clck pulse generation signal comprising a pulse starting with the pulse from the external clock signal Ext-Clck and ending upon receipt of the Pulse-Reset pulse signal. The Stp-Trig trigger signal and the Pulse-Gen-Clck pulse generation signal are output by the Pulse-Gen pulse generation circuit via the second and third outputs Out2 and Out3, respectively.

[0060] The Pulse-Width control circuit is configured to perform an OR logic gate function with the external clock signal Ext-Clck and the pulse-generating signal Pulse-Gen-Clck as inputs and the internal clock signal Int-Clck as output. To this end, the Pulse-Width control circuit has a fifth input In5 connected to the third output Out3 and a sixth input In6 connected to the first input Inl.

[0061] As illustrated in [Fig. 4], the pulse-width determination circuit may consist of an OR logic gate input with the clock signal external Ext-Clck and the pulse generation signal Pulse-Gen-Clck, the output being the internal clock signal Int-Clck.

[0062] According to the interaction between the elements mentioned above, a pulse of the internal clock signal Int-Clck emitted by the pulse-width determination circuit Pulse-Width begins with a rise of a pulse of the external clock signal and ends with the longer of the following two durations: (i) a duration for the end of the pulse of the external clock signal and (ii) a duration for the charging of the dummy bit line up to a predetermined threshold.

[0063] The Del delay circuit is optional and can be inserted between the third output of the Pulse-Gen pulse generation circuit and the fifth input of the Pulse-Width pulse determination circuit. The Del delay circuit includes inputs (not shown) that can be used by the user to fine-tune the delay.

[0064] However, the invention is not limited to the specific examples illustrated by Figures 3 to 7, and the functions of the individual circuits forming the timing control circuit can of course be implemented in various ways.

[0065] Figures 8 and 9 are time-domain diagrams illustrating the operation of the T-Cntl synchronization circuit, which takes into account the effective charging time of a dummy bit line DBL, considered representative of the charging time of the bit lines BL, to generate an internal clock signal Int-Clck. In the graphs, voltages are expressed in volts (V) and time is expressed in nanoseconds (ns). These graphs are the results of simulations of the circuit's operation illustrated in Figures 3 to 7.

[0066] Figure 8 illustrates the situation in which the MEM memory circuit originates from a slow corner, implying that the bit lines are likely not to be fully loaded at the end of an external clock pulse, which is intended to control the bit line loading time, and at the instant the detection amplifier circuit is activated. In this case, without correction, the detection amplifier circuit may be deactivated (detection amplifier detecting during the high clock) too early to reliably evaluate the logic level of a bit cell, which is evaluated by the bit line.

[0067] However, according to the invention, the T-Cntl synchronization circuit controls the length of a pulse of the internal clock signal so that it corresponds to the time required to load the dummy bit line, so that the detection amplifier circuit is automatically deactivated when the dummy bit line and therefore a bit line of the matrix are sufficiently loaded.

[0068] As illustrated in the timing diagram, when an Ext-ClckPush pulse from the external clock signal Ext-Clck rises, the Pulse-Gen pulse generation circuit generates a pulse of the Stp-Trig trigger signal and a Pulse-GenPuke pulse of the Pulse-Gen-Clck pulse generation signal. The Ext-ClckPuke pulse also triggers an Int-ClckPuised pulse of the internal clock signal Int-Clk.

[0069] The rise of the Stp-Trig trigger signal causes the rise of the dwl-clk voltage of the DWL dummy word line, which is returned to the T-Cntl synchronization circuit, more specifically to the Reset-Gen reset signal generation circuit.

[0070] Increasing the dwl-clk voltage of the dummy word line DWL causes an increase in the dbl voltage of the dummy bit line DBL, which makes it possible to track the time required to load a bit line.

[0071] When the dbl voltage of the dummy bit line reaches a given threshold, the Reset-Gen signal generation circuit generates a pulse in the Pulse-Reset pulse signal.

[0072] The pulse of the Pulse-Reset signal triggers the drop in the pulse of the Pulse-Gen-Clck signal. At that moment, since the pulse of the external clock signal has already terminated (we are assuming a slow corner, the dummy bit line loading more slowly than the time it takes for a pulse of the external clock signal to terminate) and therefore the external clock signal is low, only the Pulse-Gen-Clck signal was keeping the internal clock signal Int-Clck at a high level. It is therefore the drop in the pulse of the Pulse-Gen-Clck signal that triggers the drop in the pulse of the internal clock signal Int-Clck and deactivates the S-Amp detection amplifier circuit.

[0073] In this situation, the T-Cntl synchronization circuit lengthened the pulse allowing the detection amplifier circuit to provide the time necessary for the dummy bit line and the bit line to be read to be sufficiently loaded.

[0074] Figure 9 illustrates the situation in which the MEM memory circuit originates from a fast corner, which implies that the bit lines are likely to be fully loaded before the end of an external clock pulse that controls the bit line loading time and the instant the detection amplifier circuit is activated.

[0075] As illustrated in the timing diagram, when an Ext-ClckPuke pulse of the external clock signal Ext-Clck rises, the Pulse-Gen pulse generation circuit generates a pulse of the Stp-Trig trigger signal and a Pulse-GenPuke pulse of the Pulse-Gen-Clck pulse generation signal. The Ext-ClckPuke pulse also triggers an Int-ClckPuke pulse of the internal clock signal Int-Clk.

[0076] The rise in the Stp-Trig trigger signal causes the dwl-clk voltage of the DWL dummy word line to rise, which is fed back to the synchronization circuit T-Cntl, more specifically to the Reset-Gen signal generation circuit.

[0077] Increasing the dwl-clk voltage of the dummy word line DWL causes an increase in the dbl voltage of the dummy bit line DBL, which makes it possible to track the time required to load a bit line.

[0078] When the dbl voltage of the dummy bit line reaches a given threshold, the Reset-Gen signal generation circuit generates a pulse in the Pulse-Reset signal.

[0079] The pulse of the pulse-reset signal triggers the falling pulse of the pulse-generating signal, Pulse-Gen-Clck. At that moment, since the pulse of the external clock signal is still high (we are assuming a fast corner, the dummy bit line loading faster than the time it takes for a pulse of the external clock signal to complete), and therefore the external clock signal is high, the pulse of the external clock signal is also high. It is therefore the falling pulse of the external clock signal, Ext-Clck, that triggers the falling pulse of the internal clock signal, Int-Clck, and deactivates the detection amplifier circuit, S-Amp.

[0080] In this situation, the T-Cntl synchronization circuit lets the external clock signal define the activation time of the S-Amp detection amplifier circuit: the internal clock signal Int-Clck is substantially identical to the clock signal of the external signal Ext-Clck.

[0081] It can be seen that the timing control circuit according to the invention allows for automatic adaptation of the MEM memory control, independently of the exact characteristics of the memory with regard to the loading time of the bit lines and / or word lines. More specifically, an Int-ClckPuke pulse of the internal clock signal Int-Clk has a width defined as the longer of the lengths of (i) a pulse of the external clock signal Ext-ClckPuise and (ii) a Pulse-Gen(Puke) pulse of the pulse-generating clock signal Pulse-Gen-Clk.

[0082] In the present description, the memory arrays illustrated in Figures 1(A) and 2 are considered to be resistive random-access memory arrays. However, the invention is not limited to this type of memory. Other examples of memories to which the memory circuit according to the invention can be applied include static random-access memories. In this case, the two lines connecting a column of bit cells BC to an SL / BL-Mux multiplexer circuit are often called a bit-line pair consisting of a first bit line and a second bit line. It can also be said that embodiments of the invention may relate to memories in which the value of the data stored by A given bit cell is determined by the voltage of a corresponding single bit line signal, or memories using a pair of two bit lines to determine the data stored by a given bit cell, the data value being determined by detecting a voltage difference between the two bit lines. More generally, any architecture can be used for the ARR bit cell matrix and for BC bit cells.

[0083] Each of the examples mentioned in this document can be freely combined within the technical limits understood by the practitioner in the field of the invention.

[0084] Other variants of the disclosed design can be understood and implemented by persons competent in the practice of the claimed invention, from the study of the drawings, the disclosure and the attached claims.

Claims

Demands

1. A memory circuit (MEM) comprising: - an array (ARR) of bit cells (BC) arranged in rows of bit cells each connected to a word line (WL) and in columns of bit cells each connected to a bit line (BL), the word lines being connected to a word line driver circuit (WL-Drv), the bit lines being connected to a multiplexer circuit (SL / BL-Mux);- a detection amplifier circuit (S-Amp) configured to be connected to the bit lines, - an external clock input (Inl) configured to be fed by an external clock signal (Ext-Clck) comprising external clock pulses having a first duration, and - a synchronization circuit (T-Cntl) configured to track the time required to load one of the bit lines and which is a second duration, the synchronization circuit (T-Cntl) being configured to generate an internal clock signal (Int-Clk) comprising internal clock pulses (Int-Clck(Puise)) and transmit the internal clock signal to the detection amplifier circuit (S-Amp), the internal clock pulses having a width defined as the longer of the first duration and the second duration.;

2. The memory circuit according to claim 1, the memory circuit being configured to drive respective voltages of the bit lines as a function of the data stored in the bit cells respectively connected to the bit lines during a read operation of the memory circuit.

3. The memory circuit according to claim 1 or claim 2, wherein the synchronization circuit (T-Cntl) is configured to track the time required to load one of the first lines by tracking the time required to load a dummy bit line (DBL) and which is representative of the time required to load the bit lines.

4. The memory circuit according to any one of claims 1 to 3, comprising: - a dummy word line (DWL); and - a dummy first line (DBL); the synchronization circuit comprising - a Reset-Gen signal generation circuit configured to generate and send a Pulse-Reset signal when a voltage on the first dummy line reaches a given threshold; - a pulse-generator circuit having a first input (In3) connected to the external clock input (Inl) and a second input (In4) configured to receive the pulse-reset signal, the pulse-generator circuit is configured (i) to generate and send a trigger signal (Stp-Trig) to load the dummy word line in response to a pulse from the external clock signal and (ii) to generate a pulse-generator signal (Pulse-Gen-Clck) comprising a pulse starting with the pulse from the external clock signal (Ext-Clck) and ending upon receipt of the pulse-reset signal;and - a pulse-width determination circuit configured to receive (i) the external clock signal (Ext-Clck) and (ii) the pulse-generation signal (Pulse-Gen-Clck), the selection circuit being further configured to generate and emit the internal clock signal (Int-Clck).

5. The memory circuit according to claim 4, the pulse-width determination circuit being configured to perform an OR logic gate function with the external clock signal (Ext-Clck) and the pulse-gen-Clck signal (Pulse-Gen-Clck) as inputs and the internal clock signal (Int-Clck) as output.

6. The memory circuit according to claim 4 or 5, further comprising a dummy bit line emulation circuit (Emul.BL) connected to the dummy bit line (DBL) and configured to emulate an environment of one of the bit lines (BL) of the bit cell (BC) array (ARR) such that loading the dummy bit line (DBL) takes substantially the same time as loading one of the bit lines (BL).

7. Memory circuit according to any one of claims 4 to 6, further comprising a dummy word line (WL) emulation circuit connected to the dummy word line (DWL) and configured to emulate an environment of one of the word lines (WL) of the matrix (ARR) of bit cells (BC) so that a signal propagates substantially identically along the dummy word line (DWL) and along one of the word lines (WL).

8. Memory circuit according to any one of claims 4 to 7, further comprising a delay circuit (Del) configured to delay the pulse-gen-clck signal generated by the pulse-gen-clck circuit before the pulse-gen-clck signal reaches the pulse-width determination circuit.

9. Memory circuit according to any one of claims 1 to 8, wherein the memory circuit (MEM) is a resistive RAM.

10. Embedded system (EmbSys) comprising the memory circuit according to any one of claims 1 to 9, connected to a microprocessor (CPU).

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