Monolithic manufacturing process for a bidirectional double-gate power transistor with alternating control

Abstract

The invention relates to a method for manufacturing an integrated circuit (IC) comprising a bidirectional field-effect transistor (1) comprising the following steps: (I) providing a stack of layers (EC) deposited on a substrate (SUB); (II) manufacturing the bidirectional transistor (T1) by forming: at least two gates (G1, G2) in the barrier layer (C1); a first source (S1) and a second source (S2); and a channel zone (ZC) formed in the channel layer (C2); (III) manufacturing, on the same stack of layers (EC), a first biasing transistor (Ta) and a second biasing transistor (Tb), the bidirectional transistor, the first biasing transistor (Ta) and the second biasing transistor (Tb) being monolithic; (IV) electrically connecting: the source (Sa) of the first biasing transistor (Ta) to the substrate and the source (Sb) of the second biasing transistor (Tb) to the substrate (SUB). Figure from the summary: Fig. 3f

Description

Title of the invention: Monolithic manufacturing method for a bidirectional, double-gate power transistor with alternating control. Scope of application

[0001] The invention relates to the monolithic integration of common-drain, heterojunction, bidirectional power transistors on a single substrate. More particularly, the invention relates to a method for manufacturing such transistors with alternating biasing of the bidirectional transistor sources to the substrate.

[0002] The invention is particularly applicable to electrical power conversion circuits and systems, especially in the field of electric vehicles, where high-performance power electronics components are required to minimize losses and operate efficiently at high frequencies. In this context, power electronics components based on GaN-on-silicon technology are among the most promising solutions in terms of performance and cost. This technology relies on the epitaxial growth of GaN layers on silicon substrates, a well-established technological process that allows for the production of GaN layers of optimal thickness at low cost. The physical properties of GaN, particularly its low specific resistance, allow for higher densities than silicon, thus significantly improving component efficiency.High electron mobility field-effect transistors (HEMTs), based on the AlGaN / GaN heterojunction, are distinguished by their improved performance, making them well-suited for power electronics. They enable high switching frequencies, allowing for smaller passive components and increased power density. Furthermore, high-frequency, high-power systems often utilize HEMT-type side structures. These structures allow for the integration of a second gate region within the transistor without complicating the design or fabrication. Dual-gate HEMTs thus enable the use of compact and efficient matrix topologies, offering excellent conversion efficiency.

[0003] To better understand the technical problem raised, [Fig. 1] illustrates a cross-sectional view of a state-of-the-art dual-gate, common-drain power transistor 1'. The transistor T1' is fabricated on a silicon substrate SUB' acting as a support. The transistor T1' comprises the following stack of layers, starting from the substrate SUB': - a C3' buffer layer to adjust the crystal structure during epitaxial growth. For example, the C3 buffer layer is made of gallium nitride alloy with aluminum GaN / AlGaN. - a C2' channel layer corresponding to the transistor channel. It is made of a high electron mobility semiconductor material, such as gallium nitride GaN. - a confinement layer Cl' to generate charge carriers in the channel layer. The confinement layer Cl' is made of a semiconductor material with a higher energy gap than the semiconductor material of the channel layer C2'. For example, the confinement layer Cl' is made of a quaternary alloy of type III-V semiconductors.

[0004] The confinement layer Cl' forms a heterojunction with the channel layer C2'. The band gap difference forms a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional electron gas (2DEG) which constitutes the conduction channel located at said interface. The transistor Tl' comprises two laterally spaced ohmic electrodes SI and S2. Two control electrodes, commonly called gates, G1 and G2 respectively, are arranged between the two ohmic electrodes SI and S2. The central node between the two gates G1, G2 constitutes a common drain. According to the chosen common-drain architecture, the current and voltage are therefore managed by a single channel.

[0005] In the case of dual-gate heterojunction transistors as illustrated in [Fig. 1], the silicon substrate SUB' must be connected to one of the two sources SI, S2, depending on the direction of the blocked electric field. In this context, dual-gate power transistors fabricated on a common semiconductor substrate are subject to gate-back effects leading to current collapse and degraded operating characteristics depending on the bias of the applied substrate. Therefore, appropriate substrate biasing is essential to ensure efficient and symmetrical bidirectional operation, particularly in the state-of-the-art transistor architecture T1'.

[0006] French patent FR3053832 proposes a two-gate power transistor in a common-drain configuration, in which the rear face of the substrate includes an aperture filled with a dielectric material separating two PN diodes made in the substrate by doping. Each diode is configured to connect the substrate to an associated source contact of the transistor. The drawback of this solution is the complexity of its implementation and the resulting fragility of the structure. Indeed, the solution proposed by this patent requires etching operations on the rear face of the transistor and doping operations also performed on the rear face opposite the transistor. This makes The process is more complex and requires inverting the semiconductor wafer, thus introducing greater reliability risks during manufacturing. Furthermore, creating openings in the substrate body for each transistor in an integrated circuit significantly weakens the overall circuit reliability from both a mechanical and electronic standpoint. In addition, the presence of the dielectric-filled opening makes biasing the entire substrate impossible.

[0007] To overcome the limitations of existing solutions, the invention proposes a method for manufacturing a common-drain, two-gate power transistor in which a first biasing transistor connects the first source to the substrate and a second biasing transistor connects the second source to the substrate. The biasing transistors allow the substrate bias of the bidirectional two-gate transistor to be dynamically adapted by automatically connecting it to the active source (S1 or S2) depending on the direction of the current. The biasing transistors are monolithically integrated with the bidirectional transistor and are manufactured in parallel with the bidirectional transistor during the same manufacturing process.This monolithic solution simplifies manufacturing by integrating the biasing transistors directly with the transistor, eliminating back-etching and back-doping steps, thereby improving mechanical and electrical robustness. The device according to the invention also optimizes substrate biasing, reducing the on-state resistance R0N by 20% and enabling faster, higher-frequency operation compared to conventional solutions.

[0008] The invention relates to a method for manufacturing an integrated circuit comprising a bidirectional field-effect transistor, comprising the following steps: - provide a stack of layers deposited on a substrate in a stacking direction orthogonal to the plane of the substrate; the stack of layers comprising: a barrier layer made of a first IILV type semiconductor material disposed on a channel layer made of a second IILV type semiconductor material having an energy gap lower than that of the first semiconductor material; the interface between the barrier layer and the channel layer forming a heterojunction; - to manufacture the bidirectional transistor by forming: • at least two grids in the barrier layer; • a first source and a second source; • and a channel zone formed in the channel layer; the two grids being arranged between, on the one hand, the first source and, on the other hand, the second source; - fabricate, on the same stack of layers, a first biasing transistor having a gate, a source and a drain; and fabricate, on the same stacking of layers, a second biasing transistor having a gate, a source and a drain so that the bidirectional transistor, the first biasing transistor and the second biasing transistor are monolithic; - connect electrically: • the source of the first biasing transistor to the substrate; • the source of the second biasing transistor to the substrate; • the drain of the first biasing transistor to the first source; • and the drain of the second biasing transistor to the second source.

[0009] According to a particular aspect of the invention, during step (III), the first biasing transistor and the second biasing transistor are placed so that the bidirectional transistor is arranged between the first biasing transistor on one side and the second biasing transistor on the opposite side in a direction parallel to the plane of the substrate.

[0010] According to a particular aspect of the invention, the formation of the grids of the bidirectional transistor is carried out simultaneously with the formation of the grid of the first biasing transistor and the grid of the second biasing transistor.

[0011] According to a particular aspect of the invention, the formation of the sources of the bidirectional transistor is carried out simultaneously with the formation of the source and drain of the first biasing transistor and of the source and drain of the second biasing transistor.

[0012] The invention relates to a monolithic integrated circuit fabricated on a substrate comprising: - a bidirectional field-effect transistor comprising: • a heterojunction formed by a barrier layer in a first type III-V semiconductor material disposed on a channel layer in a second type III-V semiconductor material having an energy gap lower than that of the first semiconductor material; • a first source and a second source; • two grids arranged between the first source on one side and the second source on the other side; - a first biasing transistor having a drain electrically connected to the first source of the bidirectional transistor and a source electrically connected to the substrate; - a second biasing transistor having a drain electrically connected to the second source of the bidirectional transistor and a source electrically connected to the substrate; the bidirectional transistor, the first biasing transistor and the second biasing transistor being monolithic.

[0013] According to a particular aspect of the invention, the bidirectional transistor is arranged between the first biasing transistor on one side and the second biasing transistor on the opposite side in a direction parallel to the plane of the substrate.

[0014] According to a particular aspect of the invention, the circuit further comprises control means configured to: - apply a first bias voltage on the first source and a second bias voltage on the second source greater than the first bias voltage; - and put the first bias transistor in a conducting state and the second bias transistor in a blocking state.

[0015] According to a particular aspect of the invention, the circuit further comprises control means configured to: - apply a first bias voltage on the first source and a second bias voltage on the second source lower than the first bias voltage; - and put the first bias transistor in a blocking state and the second bias transistor in a conducting state.

[0016] According to a particular aspect of the invention, the geometric width-to-length ratio of the first biasing transistor or the second biasing transistor is less than 5% of the geometric width-to-length ratio of the bidirectional transistor.

[0017] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0018] Figure 1 illustrates a cross-sectional view of a state-of-the-art dual-gate power lateral transistor. This figure has already been described.

[0019] Figure [Fig.2] illustrates the flowchart of a manufacturing process according to the invention.

[0020] Figures 3a to 3f illustrate an example of the steps in the manufacturing process according to the invention.

[0021] Fig. 4a illustrates a top view of the integrated circuit according to the invention.

[0022] Figure 4b illustrates an electrical diagram of the integrated circuit according to the invention.

[0023] In the figures illustrating the invention, the horizontal is represented by the X and Y directions of an orthogonal coordinate system (X,Y,Z). The Z direction of this orthogonal coordinate system represents the vertical direction. Subsequently, terms such as "superior," "inferior," "above," "below," "top," and "bottom" are defined with respect to this Z direction. The terms "left" and "right" are defined with respect to the X direction. The terms "front" and "back" are defined with respect to the direction Y. Hereafter, the term "thickness" refers to the maximum thickness of an element along the Z direction, also known as the stacking direction. The term "width" refers to the dimension of a layer along the X direction.

[0024] Figure [Fig.2] illustrates the flowchart of a manufacturing process according to the invention.

[0025] The first step (I) consists of providing or manufacturing a stack of layers EC stacks are deposited on a semiconductor substrate, advantageously silicon. The EC stack comprises a barrier layer C1 made of a first type III-V semiconductor material deposited on a channel layer C2 made of a second type IILV semiconductor material. The second semiconductor material has a smaller energy gap than the first semiconductor material such that the interface between the barrier layer C1 and the channel layer C2 forms a heterojunction. For example, the barrier layer C1 is made of AlGaN and the channel layer C2 is made of GaN. Advantageously, the EC stack further comprises a passivation layer C4 made of a dielectric material such as SiO2 deposited on the barrier layer C1 to electrically insulate and protect it during the fabrication process. Advantageously, the stack also comprises a buffer layer C3 confined between the channel layer C2 and the silicon substrate.The C3 buffer layer allows for adjustment of the crystal lattice during epitaxial growth of the C2 channel layer on a silicon substrate.

[0026] The second step (II) consists of manufacturing the bidirectional transistor T1 by carrying out the following substeps without any chronological order requirement: forming at least two gates G1, G2 in the barrier layer C1; forming a first ohmic contact S1 in the barrier layer C1 acting as a first source; and forming a second ohmic contact S2 in the barrier layer C1 acting as a second source. The two gates G1, G2 are arranged between, on the one hand, the first ohmic contact S1 and, on the other hand, the second ohmic contact S2. The substeps of manufacturing the bidirectional transistor T1 are not necessarily performed consecutively during the execution of the various steps of the manufacturing process according to the invention.The conduction channel formation zone when the bidirectional transistor is in the conducting state is located in the channel layer C2 below the theterojunction of said layer with the barrier layer CL.

[0027] The third step (III) consists of fabricating, on the same stack of EC layers, a first biasing transistor Ta and a first biasing transistor Ta configured to control the biasing of the substrate SUB according to the direction of the current in the bidirectional transistor TL. The third step is carried out by implementing the following substeps: forming, for the first biasing transistor Ta, a gate Ga next to the first source SI of the bidirectional transistor Tl; forming, for the second biasing transistor Tb, a gate Gb next to the second source S2 of the bidirectional transistor T1; fabricate the drain Da and the source Sa of the first biasing transistor Ta by placing the drain Da between the gate Ga and the first source S1; and fabricate the drain Db and the source Sb of the second biasing transistor Tb by placing the drain Db between the gate Gb and the second source S2. The fabrication of the sources Sa, Sb and the drains Da, Db is achieved by etching several cavities in the stack up to the channel layer C2 and filling them with an electrical conductor forming a plurality of ohmic contacts.

[0028] The fourth step (IV) consists of electrically connecting the source Sa of the first biasing transistor Ta to the substrate SUB; connecting the source Sb of the second biasing transistor Tb to the substrate SUB; connecting the drain Da of the first biasing transistor Ta to the first source SI; and finally, connecting the drain Db of the second biasing transistor Tb to the second source S2. The connections to the sources SI and S2 are made by depositing metallic traces. The connections of the biasing transistors Ta and Tb to the substrate SUB are made by connecting trenches extending through the stack of EC layers to the substrate SUB.

[0029] The biasing transistors Ta, Tb allow the biasing of the SUB substrate to be adapted according to the direction of conduction in the bidirectional transistor Tl, such that the SUB substrate is common to both gates G1, G2. The method according to the invention thus allows for a monolithic assembly of the bidirectional two-gate transistor Tl while overcoming the problems associated with the variable biasing of the SUB substrate depending on the direction of the current in the transistor. Monolithic integration makes it possible to reduce the size of the integrated circuit (IC) comprising a plurality of dual-gate transistors compared to state-of-the-art solutions. Furthermore, monolithic integration allows for faster transistor switching and thus enables high-frequency operation.The biasing transistors Ta and Tb allow for integrated control of the SUB substrate's bias: When electrons in the conduction channel move from the first source SI to the second source S2, the first biasing transistor Ta is switched on and the second biasing transistor Tb is switched off, so that the SUB substrate is connected to the first source SL. Conversely, the first biasing transistor Ta is switched off and the second biasing transistor Tb is switched on, so that the SUB substrate is connected to the second source S2. This configuration minimizes the on-state resistance after the bidirectional transistor T1 is switched off, compared to state-of-the-art solutions.For example, a 20% reduction in resistance R0N is observed compared to a bidirectional two-gate transistor in which the substrate is short-circuited simultaneously with the first and second sources S1,S2.

[0030] The monolithic implementation of the Ta,Tb bias transistors allows them to be manufactured simultaneously with the fabrication of the Tl transistor. The use of the Ta,Tb bias transistors in the context of the invention avoids etching and doping operations on the SUB substrate, which offers several advantages: simplifying the manufacturing process by reducing the number of steps, improving the mechanical and electrical robustness of the integrated circuit by avoiding etching of the SUB substrate; and ensuring physical and electrical continuity of the SUB substrate, simplifying its biasing.

[0031] To better understand the invention, Figures 3a to 3f illustrate an example of the steps in the manufacturing process according to the invention. The chronological order of the substeps is for illustrative purposes only and is not limiting.

[0032] The first step (i), illustrated in [Fig. 3a], consists of providing or fabricating the stack of EC layers deposited on a semiconductor SUB substrate described in the first step (I) of [Fig. 2]. The interface between the barrier layer Cl and the channel layer C2 creates a discontinuity in the energy bands, which leads to the formation of a two-dimensional (2DEG) electron gas in the channel layer C2 near the junction. This gas is a region where electrons can move with very high mobility because they do not undergo collisions with atoms, unlike in a conventional conductor. When the transistor T1 is in a conducting state, the two-dimensional electron gas forms a conduction channel under the C1 / C2 interface, through which electrons can move rapidly. The Cl and C2 layers, made of IILV-type semiconductor materials, are fabricated by epitaxial growth on the silicon SUB substrate.

[0033] The second step (ii), illustrated in [Fig. 3b], consists of forming two gates G1, G2 in the barrier layer CL. Simultaneously, during the second step (ii), the gate Ga of the first biasing transistor Ta and the gate Gb of the second biasing transistor are fabricated. The formation of the gates G1, G2, Ga, and Gb is achieved by etching the stack EC on the side of the passivation layer C4 to create four cavities extending to the channel layer C2. An oxidation operation deposits a dielectric layer on the inner walls of these cavities. Then, the remaining volume of each cavity is filled with a metal, such as titanium nitride or a copper-aluminum alloy. This yields the two gates G1, G2 of the bidirectional transistor T1, surrounded by the gate Ga on one side and the gate Gb on the other.This simultaneous realization of the four grids means that the second step (ii) is at the same time a sub-step of step (III) of manufacturing the biasing transistors Ta,Tb and of the second step (II) of manufacturing the transistor Tl of the process according to the invention.

[0034] The third step (iii), illustrated in [Fig. 3c], consists of forming the drain / source pair for each biasing transistor Ta,Tb and simultaneously fabricating the first source SI and the second source S2. Each of these fabricated electrodes is made by an ohmic contact with at least the heterojunction C1 / C2 and, more advantageously, up to the channel layer C3. The formation of each ohmic contact is achieved by etching the stack EC on the side of the passivation layer C4 to create six cavities extending at least to the channel layer C2. The depth of each cavity does not exceed 1000 nm relative to the heterojunction formed by the Cl and C2 layers. The location of the cavities is chosen so as to obtain the following arrangement: the two grids G1,G2 are arranged between on the one hand a first pair of cavities and on the other hand a second pair of cavities according to the (X,Y) plane of the substrate SUB.The Ga grid is positioned between the first pair of cavities and a cavity. The Gb grid is positioned between the second pair of cavities and a cavity. Each cavity is then filled with an electrically conductive material having an electron affinity lower than that of the first semiconductor material in the Cl barrier layer and lower than that of the second semiconductor material in the C2 channel layer. More specifically, when the Cl barrier layer is AlGaN and the C2 channel layer is GaN, the second electrically conductive material in each ohmic contact has a work function of 4 eV or less. For example, the second electrically conductive material in each ohmic contact is chosen from titanium or a titanium-containing alloy such as a titanium-aluminum alloy.

[0035] Alternatively, each fabricated ohmic contact is formed by a stacking of a plurality of layers all made of conductive materials with an output work lower than the electronic affinity of the first semiconductor material of the barrier layer Cl and lower than the electronic affinity of the second semiconductor material of the channel layer C2.

[0036] By way of example, the deposition of the first electrically conductive material in the cavity is carried out by thermal evaporation or sputtering. The thickness of each ohmic contact is between 50 nm and 100 nm.

[0037] The ohmic contact adjacent to the first gate G1 forms the first source SI of the transistor TL. The ohmic contact adjacent to the second gate G2 forms the second source S2 of the transistor TL. The ohmic contact adjacent to the first source SI forms the drain Da of the first biasing transistor Ta. The ohmic contact adjacent to the second source S2 forms the drain Db of the second biasing transistor Tb. The ohmic contact adjacent to the gate Ga and opposite the drain Da forms the source Sa of the first biasing transistor Ta. The ohmic contact adjacent to the gate Gb and opposite the drain Db forms the source Sb of the second biasing transistor Ta. This simultaneous realization of the six electrodes means that the third step (iii) is at the same time a sub-step of step (III) of manufacturing the biasing transistors Ta,Tb and of the second step (II) of manufacturing the transistor Tl of the process according to the invention.

[0038] The fourth step (iv), illustrated in [Fig.3d], consists of depositing a dielectric ENC encapsulation layer on the structure obtained to protect it mechanically and insulate it electrically.

[0039] The fifth step (v), illustrated in [Fig. 3e], consists of fabricating a VI, V2 connection trench for each associated biasing transistor. The first VI connection trench is adjacent to the Sa source of the first biasing transistor Ta. The second V2 connection trench is adjacent to the Sb source of the second biasing transistor Tb. The fabrication of each VI, V2 connection trench comprises the following substeps: a first substep (va) which consists of etching a cavity along the Z stacking direction and through the EC stacking layers until reaching the SUB substrate. The cavity has a width between 10pm and 100pm and a depth between 2pm and 20pm. The second substep (vb) consists of depositing a dielectric layer on the inner side walls of said cavity. The third substep (v.c) consists of etching the dielectric layer deposited on the surface of the cavity bottom to create an opening that leads to the SUB substrate. The fourth substep (vd) consists of filling the cavity with an electrically conductive material, for example, a metallic deposit. In the fifth substep (ve), the excess metal deposited in the cavity is planarized by chemical-mechanical polishing to obtain a thickness equal to the thickness of the ENC encapsulation layer.

[0040] The sixth step (vi), illustrated in [Fig. 3f], consists of depositing a first electrically conductive track PI, for example made of copper or titanium, interconnecting the first connection trench VI and the source Sa of the first biasing transistor Ta. Simultaneously, the sixth step further comprises the depositing of a second electrically conductive track P2, for example made of copper or titanium, interconnecting the first source SI and the drain Da of the first biasing transistor Ta. Simultaneously, the sixth step further comprises the depositing of a third electrically conductive track P3, for example made of copper or titanium, interconnecting the second connection trench V2 and the source Sb of the second biasing transistor Tb.Simultaneously, the sixth step further comprises the deposition of a fourth electrically conductive track P4, for example of copper or titanium, interconnecting the second source S2 and the drain Db of the second biasing transistor Tb. The fifth and sixth steps together form step (III) of the method according to the invention.

[0041] Optionally, the sixth step further includes the deposition of a metallic electrode, for example copper or titanium, on the first grid Gl, on the second grid G2 and on the grids Ga,Gb of biasing transistors Ta,Tb.

[0042] The method according to the invention thus makes it possible to manufacture an integrated circuit comprising a monolithic dual-gate power transistor in which the biasing of the substrate with respect to the first source SI or the second source S2 is better controlled. The manufacturing method according to the invention does not require etching operations on the back side of the substrate, which solves the substrate biasing problem while ensuring mechanical and electronic robustness of the integrated circuit IC and without complicating the manufacturing process.

[0043] Figure 4a illustrates a top view of the integrated circuit (IC) according to the invention along the (X,Y) plane parallel to the substrate plane. The bidirectional transistor T1 and the biasing transistors Ta, Tb are implemented using a plurality of identical microstructures called "fingers." A finger corresponds to a multiplication of the effective channel width of a transistor by distributing the total width W over several smaller parallel "fingers" dgl, each having an identical channel length. Thus, for each transistor, the geometric width-to-length ratio is proportional to the number of fingers used. The integrated circuit according to the invention allows dynamic control of the substrate biasing while maintaining a compact surface area compared to prior art solutions.Indeed, in the integrated circuit (IC) according to the invention, the number of fingers of any one of the biasing transistors Ta or Tb is less than 5% of the number of fingers of the bidirectional transistor Tl, and more advantageously less than 2.5% of the number of fingers of the bidirectional transistor TL. This implies that the area occupied along the (X,Y) plane increases by only 5% compared to a solution in which the substrate bias is not controlled. In other words, the circuit according to the invention allows dynamic adjustment of the substrate bias according to the direction of the current, with a width-to-length ratio WTa / LTa of the first biasing transistor Ta that is less than 5% of the width-to-length ratio Wn / Ln of the bidirectional transistor Tl, and advantageously less than 2.5%.Similarly, the geometric width-to-length ratio WTb / LTb of the second biasing transistor Tb is less than 5% of the geometric width-to-length ratio Wn / Ln of the bidirectional transistor Tl, and advantageously less than 2.5%.

[0044] Figure 4b illustrates an electrical diagram of the integrated circuit IC according to the invention. The integrated circuit IC comprises a bidirectional transistor T1 with dual gates G1, G2, the first biasing transistor Ta, and the second biasing transistor Tb, monolithic and connected as described according to the invention. The integrated circuit IC includes further control means CONT configured to bias the sources S1,S2 of the bidirectional transistor Tl and control the state of the biasing transistors Ta,Tb according to the direction of the current in the conduction channel of the bidirectional transistor Tl.

[0045] More specifically, when the bidirectional transistor Tl is intended to conduct current from the first source S1 to the second source S2, the control means CONT are configured to apply a first bias voltage VS1 to the first source S1 and a second bias voltage VS2 to the second source S2 that is lower than the first bias voltage VS1. The control means CONT are also configured to put the first bias transistor Ta in a blocking state and the second bias transistor Tb in a conducting state. This allows the substrate SUB to be connected to the second source S2, which has the lowest potential. This configuration allows for a considerable reduction in the on-state resistance after the bidirectional transistor Tl is blocked, compared to prior art solutions.Conversely, when the bidirectional transistor Tl is intended to conduct current from the second source S2 to the first source SI, the control means CONT are configured to apply a first bias voltage VSi to the first source SI and a second bias voltage VS2 to the second source S2 that is higher than the first bias voltage VS1. The control means CONT are also configured to set the first bias transistor Ta to a conducting state and the second bias transistor Tb to a blocking state. This allows the substrate SUB to be connected to the first source SI, which has the lowest potential. This configuration results in a considerable reduction in the on-state resistance after the bidirectional transistor Tl is blocked, compared to state-of-the-art solutions.

Claims

Demands

1. A method for manufacturing an integrated circuit (IC) comprising a bidirectional field-effect transistor (1) comprising the following steps: (I) provide a stack of layers (EC) deposited on a substrate (SUB) along a stacking direction (Z) orthogonal to the plane of the substrate (X,Y); the stack of layers (EC) comprising: a barrier layer (Cl) made of a first type III-V semiconductor material disposed on a channel layer (C2) made of a second type III-V semiconductor material having an energy gap lower than that of the first semiconductor material; the interface between the barrier layer (Cl) and the channel layer (C2) forming a heterojunction; (II) fabricate the bidirectional transistor (Tl) by forming: • at least two grids (Gl, G2) in the barrier layer (Cl); • a first source (SI) and a second source (S2); • and a channel zone (CZ) formed in the channel layer (C2); the two grids (G1,G2) being arranged between on the one hand the first source (SI) and on the other hand the second source (S2); (III) fabricate, on the same stack of layers (EC), a first biasing transistor (Ta) having a gate (Ga), a source (Sa) and a drain (Da); and fabricate, on the same stack of layers (EC), a second biasing transistor (Tb) having a gate (Gb), a source (Sb) and a drain (Db) so that the bidirectional transistor, the first biasing transistor (Ta) and the second biasing transistor (Tb) are monolithic; (IV) electrically connect: • the source (Sa) of the first biasing transistor (Ta) to the substrate; • the source (Sb) of the second biasing transistor (Tb) to the substrate (SUB); • the drain (Da) of the first biasing transistor (Ta) to the first source (SI); • and the drain (Db) of the second biasing transistor (Tb) to the second source (S2).

2. A manufacturing method according to claim 1 wherein in step (III) the first biasing transistor (Ta) and the second biasing transistor (Tb) are placed so that the bidirectional transistor (Tl) is arranged between on one side the first biasing transistor (Ta) and on the opposite side the second biasing transistor (Tb) in a direction parallel (X) to the plane of the substrate (SUB).

3. A manufacturing method according to any one of claims 1 or 2 wherein the formation of the gates (G1,G2) of the bidirectional transistor (T1) is carried out simultaneously with the formation of the gate (Ga) of the first biasing transistor (Ta) and the gate (Gb) of the second biasing transistor (Tb).

4. A manufacturing method according to any one of claims 1 to 3 wherein the formation of the sources (S1,S2) of the bidirectional transistor (Tl) is carried out simultaneously with the formation of the source (Sa) and the drain (Da) of the first biasing transistor (Ta) and with the source (Sb) and the drain (Db) of the second biasing transistor (Tb).

5. A monolithic integrated circuit (IC) fabricated on a substrate (SUB) comprising: - a bidirectional field-effect transistor (T1) comprising: • a heterojunction formed by a barrier layer (Cl) of a first III-V semiconductor material disposed on a channel layer (C2) of a second III-V semiconductor material having a lower energy gap than the first semiconductor material; • a first source (SI) and a second source (S2); • two gates (G1, G2) disposed between, on the one hand, the first source (SI) and, on the other hand, the second source (S2); - a first biasing transistor (Ta) having a drain (Da) electrically connected to the first source (SI) of the bidirectional transistor (Tl) and a source (Sa) electrically connected to the substrate (Sub); - a second biasing transistor (Tb) having a drain (Db) electrically connected to the second source (S2) of the bidirectional transistor (Tl) and a source (Sb) electrically connected to the substrate (Sub); the bidirectional transistor, the first biasing transistor (Ta) and the second biasing transistor (Tb) being monolithic.

6. Integrated circuit (IC) according to claim 5 in which the bidirectional transistor (Tl) is arranged between on one side the first biasing transistor (Ta) and on the opposite side the second biasing transistor (Tb) in a direction parallel (X) to the plane of the substrate (SUB).

7. Integrated circuit (IC) according to any one of claims 5 or 6 further comprising control means (CONT) configured to: - apply a first bias voltage (VSi) on the first source (SI) and a second bias voltage (VS2) on the second source (S2) greater than the first bias voltage (VSi); - and put the first bias transistor (Ta) into a conducting state and the second bias transistor (Tb) into a blocking state.

8. Integrated circuit (IC) according to any one of claims 5 or 6 further comprising control means (CONT) configured to: - apply a first bias voltage (VSi) on the first source (SI) and a second bias voltage (VS2) on the second source (S2) lower than the first bias voltage (VSi); - and put the first bias transistor (Ta) into a blocking state and the second bias transistor (Tb) into a conducting state.

9. Integrated circuit (IC) according to any one of claims 5 to 8 wherein the geometric width-to-length ratio (Wia / LTaWit / Lyb) of the first biasing transistor (Ta) or of the second biasing transistor (Ta) is less than 5% of the geometric width-to-length ratio (WTi / LTi) of the bidirectional transistor (Tl).

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