LOGIC COMPONENT INTEGRITY MONITORING
FR3171284A1Pending Publication Date: 2026-07-17SAFRAN ELECTRONICS & DEFENSE (FR)
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Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- SAFRAN ELECTRONICS & DEFENSE (FR)
- Filing Date
- 2025-01-14
- Publication Date
- 2026-07-17
Abstract
The present invention relates to an electronic device (100) comprising: - one or more logic components (102-1); - for each logic component (102-1), a test interface (106-1) designed to: receive input data (TDI1), transmit the input data (TDI1) to the logic component (102-1) so that the latter provides output data (TDO1), and provide a physical output signal (S[TDO1]), such as, for example, a square wave electrical signal, carrying the output data (TDO1). The electronic device (100) further comprises, for each test interface (106-1), a monitoring module (108-1) designed to: - receive the physical output signal (S[TDO1]) provided by the test interface (106-1), and - provide a response (R1) dependent on the physical characteristics of the received physical output signal (S[TDO1]). Figure for the abstract: Fig. 1
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