Display panel and display device

Abstract

Embodiments of the present disclosure provide a display panel and a display device. The display panel comprises: a driving backplate, comprising a substrate, a plurality of driving circuits distributed on the substrate in an array, and a plurality of positive electrode pads located on the side of the driving circuits away from the substrate; a plurality of pixel islands located on the driving backplate, wherein each pixel island comprises a plurality of first sub-pixels; and a plurality of first electrode pad groups located between the pixel islands and the driving backboard, wherein the orthographic projections of the first electrode pad groups on the substrate are located within the orthographic projections of the corresponding pixel islands on the substrate; each first electrode pad group comprises a plurality of first electrode pads; the first electrode pads are connected to the positive electrode pads by bonding; the number of rows of the first electrode pads in the first electrode pad groups is greater than the number of rows of the first sub-pixels in the pixel islands; the number of columns of the first electrode pads in the first electrode pad groups is less than the number of columns of the first sub-pixels in the pixel islands; the first electrode pads are electrically connected to the first sub-pixels by means of first leads; and the positive electrode pads are electrically connected to the driving circuits by means of second leads.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As a new display technology, light-emitting diode (LED) displays offer significant advantages over liquid crystal (LCD) and organic light-emitting diode (OLED) displays in terms of image quality, refresh rate, power consumption, and brightness. This makes LED displays widely applicable, for example, in traditional displays, near-eye displays, 3D displays, and transparent displays. However, due to the limitations of mass transfer technology, LED displays face certain constraints, especially for high-resolution (PPI) displays.

[0003] Light-emitting diode chips can include submillimeter light-emitting diode (Mini LED) chips and micro light-emitting diode (Micro LED) chips. Subdividing the Mini LED pixel islands involves etching the P-electrode and P-type semiconductor layer in the Mini LED pixel islands to subdivide a single Mini LED pixel island into multiple sub-pixels, each of which is Micro LED-sized. Subdividing the Mini LED pixel islands enables high PPI display. The subdivided Mini LED pixel islands need to be transferred to the driver backplane to form an LED display panel for display.

[0004] Summary of the Invention

[0005] The present disclosure provides a display panel and a display device, and the specific solutions are as follows:

[0006] An embodiment of the present disclosure provides a display panel having a display area, wherein the display area includes:

[0007] A driving backplane, comprising a substrate, a plurality of driving circuits arrayed on the substrate, and a plurality of positive electrode pads located on a side of the driving circuits facing away from the substrate;

[0008] A plurality of pixel islands are located on the driving backplane, each of the pixel islands comprising a plurality of first sub-pixels of the same color;

[0009] A plurality of first electrode pad groups are located between the plurality of pixel islands and the driving backplane, the first electrode pad groups correspond to the pixel islands one-to-one, and the orthographic projections of the first electrode pad groups on the substrate are located within the orthographic projection range of the corresponding pixel islands on the substrate; each first electrode pad group includes a plurality of first electrode pads, and the first electrode pads are bound and connected to the positive electrode pad; wherein,

[0010] The number of rows of the first electrode pads in each of the first electrode pad groups is greater than the number of rows of the first sub-pixels in each of the pixel islands, and the number of columns of the first electrode pads in each of the first electrode pad groups is less than the number of columns of the first sub-pixels in each of the pixel islands;

[0011] The first electrode pad is electrically connected to the first sub-pixel through a first lead, and the positive electrode pad is electrically connected to the driving circuit through a second lead.

[0012] In a possible implementation, in the display panel provided by an embodiment of the present disclosure, the plurality of positive electrode pads are divided into a plurality of positive electrode pad groups, and the positive electrode pad groups correspond one-to-one to the first electrode pad groups;

[0013] The multiple driving circuits are divided into multiple driving circuit groups, each of the driving circuit groups corresponds to the positive electrode pad groups one by one, and the orthographic projection area of ​​each of the positive electrode pad groups on the substrate is smaller than the orthographic projection area of ​​the driving circuit group on the substrate.

[0014] In one possible implementation, in the above-mentioned display panel provided in an embodiment of the present disclosure, the orthographic projection of the second lead on the substrate is located within the orthographic projection range of the gap between two adjacent rows of the first sub-pixels on the substrate, and / or the orthographic projection of the second lead on the substrate is located within the orthographic projection range of the gap between two adjacent columns of the first sub-pixels on the substrate.

[0015] In one possible implementation, in the above-mentioned display panel provided by an embodiment of the present disclosure, at least some of the second leads have an overlapping area with other second leads, and for two second leads with the overlapping area, one of the second leads is bridged in the overlapping area.

[0016] In a possible implementation, in the display panel provided in an embodiment of the present disclosure, the driving backplane further includes a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer stacked in sequence between the driving circuit and the positive electrode pad, wherein the first insulating layer is close to the driving circuit;

[0017] A portion of the second lead is located on the first metal layer;

[0018] The other part of the second lead includes a first sub-lead, the bridging portion and a second sub-lead, the first sub-lead and the second sub-lead are both located in the first metal layer, and the bridging portion is located in the second metal layer; wherein, one end of the first sub-lead is electrically connected to the drive circuit through a via hole passing through the first insulating layer, the other end of the first sub-lead is electrically connected to one end of the bridging portion through a via hole passing through the second insulating layer, one end of the second sub-lead is electrically connected to the other end of the bridging portion through a via hole passing through the second insulating layer, and the other end of the second sub-lead is electrically connected to the positive electrode pad.

[0019] In one possible implementation, in the above-mentioned display panel provided in an embodiment of the present disclosure, the driving backplane further includes: a first flat layer located between the second metal layer and the positive electrode pad, and a third insulating layer located between the first flat layer and the positive electrode pad; the other end of the second sub-lead is electrically connected to the positive electrode pad through a via hole that sequentially passes through the second insulating layer, the first flat layer and the third insulating layer.

[0020] In a possible implementation, in the display panel provided by an embodiment of the present disclosure, each of the first sub-pixels includes a first electrode, a first semiconductor layer, a quantum well layer, a second semiconductor layer, and a second electrode that are stacked, and the first electrode is close to the driving backplane;

[0021] The display panel further includes a fourth insulating layer located between the first electrode and the first electrode pad, one end of the first lead is electrically connected to the first electrode pad, and the other end of the first lead is electrically connected to the first electrode through a via hole penetrating the fourth insulating layer.

[0022] In a possible implementation, in the display panel provided in an embodiment of the present disclosure, the first electrode pad and the first lead are provided in the same layer.

[0023] In a possible implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, the quantum well layer of each of the first sub-pixels in the same pixel island is an integrated structure, the second semiconductor layer of each of the first sub-pixels in the same pixel island is an integrated structure, and the second electrode of each of the first sub-pixels in the same pixel island is an integrated structure.

[0024] In a possible implementation, the above-mentioned display panel provided in the embodiment of the present disclosure further includes a second electrode pad arranged in the same layer as the first electrode pad, the second electrode in the same pixel island is electrically connected to the same second electrode pad, and the second electrodes in different pixel islands are electrically connected to different second electrode pads.

[0025] In a possible implementation, in the display panel provided by an embodiment of the present disclosure, the second electrode pad is located in a region between two adjacent columns of the first electrode pad groups.

[0026] In a possible implementation, in the display panel provided in the embodiment of the present disclosure, the driving backplane further includes a negative electrode pad provided in the same layer as the positive electrode pad, and the negative electrode pad is bound and connected to the second electrode pad.

[0027] In one possible implementation, in the above-mentioned display panel provided in an embodiment of the present disclosure, the driving backplane further includes: a fifth insulating layer located on the side of the positive electrode pad facing away from the substrate, and a second flat layer located on the side of the fifth insulating layer facing away from the substrate; the fifth insulating layer and the second flat layer have a first exposed area exposing the positive electrode pad and a second exposed area exposing the negative electrode pad, the first electrode pad is bound and connected to the positive electrode pad through the first exposed area, and the second electrode pad is bound and connected to the negative electrode pad through the second exposed area.

[0028] In one possible implementation, in the above-mentioned display panel provided by the embodiment of the present disclosure, the driving circuit includes a first gate, a first gate insulation layer, an active layer, a second gate insulation layer, a second gate, an interlayer insulation layer and a source-drain electrode stacked in sequence between the substrate and the first insulating layer; one end of the first sub-lead is electrically connected to the drain electrode of the driving circuit through a via hole passing through the first insulating layer, the drain electrode is electrically connected to the active layer, and the source electrode of the driving circuit is electrically connected to the first gate and the second gate, respectively.

[0029] In a possible implementation, in the display panel provided in an embodiment of the present disclosure, the driving backplane further includes: a first conductive connection portion and a second conductive connection portion located on the first metal layer, a low-voltage power line and a high-voltage power line provided on the same layer as the source and drain electrodes, a third conductive connection portion and a fourth conductive connection portion provided on the same layer as the second gate electrode, and a shielding electrode provided on the same layer as the first gate electrode;

[0030] The negative electrode pad is electrically connected to the first conductive connection portion through a via penetrating the third insulating layer, the first flat layer and the second insulating layer, the first conductive connection portion is electrically connected to the low voltage power line through a via penetrating the first insulating layer, the low voltage power line is electrically connected to the third conductive connection portion through a via penetrating the interlayer insulating layer, the second conductive connection portion is electrically connected to the high voltage power line through a via penetrating the first insulating layer, the high voltage power line is electrically connected to the fourth conductive connection portion through a via penetrating the interlayer insulating layer, and the high voltage power line is electrically connected to the shielding electrode through a via penetrating the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

[0031] In a possible implementation, in the above-mentioned display panel provided by an embodiment of the present disclosure, the multiple pixel islands are arranged at intervals along the row direction and the column direction, the negative electrode pads electrically connected to the pixel islands in the same column are electrically connected to the same low-voltage power line, the driving circuits electrically connected to the pixel islands in the same column are electrically connected to the same high-voltage power line, and a high-voltage power line and a low-voltage power line are arranged in the gap between the pixel islands in two adjacent columns.

[0032] In one possible implementation, the display panel provided in the embodiment of the present disclosure includes multiple rows and columns of pixel units with different luminous colors, wherein the pixel units in the same row have the same luminous color, and the pixel units in the same column with different luminous colors are alternately arranged.

[0033] Each of the pixel units includes at least two pixel islands spaced apart from each other, at least two pixel islands within each pixel unit are staggered along a row direction, and the outermost adjacent first sub-pixels of adjacent pixel islands within each pixel unit are staggered along a row direction.

[0034] In one possible implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, the multiple first sub-pixels in each pixel island are arranged at intervals along the row direction and the column direction, the first sub-pixels in each row in each pixel island are staggered in sequence along the row direction, and the distance between adjacent first sub-pixels in the same row is less than the width of the first sub-pixel along the row direction.

[0035] In a possible implementation, in the display panel provided by an embodiment of the present disclosure, the distance between the center lines of any two adjacent first sub-pixels along the column direction is equal.

[0036] In a possible implementation, the display panel provided in the embodiment of the present disclosure further includes a GOA driving circuit, an EOA driving circuit, and a MUX circuit. The GOA driving circuit and the EOA driving circuit are respectively arranged between two different adjacent columns of pixel units, and the MUX circuit is arranged between two adjacent rows of pixel units.

[0037] In a possible implementation, in the above-mentioned display panel provided in an embodiment of the present disclosure, the pixel island includes a Mini LED pixel island.

[0038] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising at least one of the above-mentioned display panels provided by an embodiment of the present disclosure.

[0039] In a possible implementation, the display device provided in the embodiment of the present disclosure further includes a plurality of lenses located on the light-emitting side of the display panel;

[0040] The plurality of lenses correspond one-to-one to the plurality of pixel islands, or each of the lenses corresponds one-to-one to each of the first sub-pixels in each of the pixel islands;

[0041] The light emitted by each first sub-pixel in each pixel island is incident on the corresponding lens.

[0042] In one possible implementation, in the above-mentioned display device provided in an embodiment of the present disclosure, the display panel further includes a splicing area arranged around the display area, and the display device includes at least two display panels spliced ​​together, and the splicing area of ​​at least two display panels is provided with a plurality of second sub-pixels arranged in the same manner as the first sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic diagram of a structure of a first sub-pixel in a Mini LED pixel island subdivided in the related art;

[0044] FIG2 is a plan view of Mini LED pixel islands in a display panel according to an embodiment of the present disclosure;

[0045] FIG3 is an enlarged schematic diagram of the dotted box A in FIG2 ;

[0046] FIG4 is a schematic plan view of a pixel island in FIG3 ;

[0047] FIG5 is a schematic cross-sectional view corresponding to a pixel island in a display panel provided by an embodiment of the present disclosure;

[0048] FIG6 is a plan view of specific film layers within the pixel island corresponding to the three pixel units (R, G, B) in FIG2 ;

[0049] FIG7 is a schematic plan view corresponding to a pixel island in FIG6 ;

[0050] FIG8 is a plan view of a portion of the film layer within the driving backplane corresponding to the pixel island shown in FIG2 ;

[0051] FIG9 is an enlarged schematic diagram of the dotted box B in FIG8 ;

[0052] FIG10 is a partial enlarged schematic diagram of FIG9;

[0053] FIG11 is a partial structure of FIG5;

[0054] FIG12 is a partial structure of FIG5;

[0055] FIG13 is a plan view schematically illustrating the driving circuit 12 in FIG10 ;

[0056] FIG14 is a schematic plan view of a second lead, a first sub-lead, and a second sub-lead included in the first metal layer of FIG10 provided on the basis of FIG13;

[0057] FIG15 is a plan view showing a second metal layer (bridge portion) in FIG10 provided on the basis of FIG14;

[0058] FIG16 is another schematic plan view corresponding to a pixel island in FIG6 ;

[0059] FIG17 is a schematic plan view of another display panel provided by an embodiment of the present disclosure;

[0060] FIG18 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0061] FIG19 is a schematic structural diagram of another display device provided by an embodiment of the present disclosure;

[0062] FIG20 is a schematic structural diagram of a spliced ​​display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0065] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0066] As shown in Figure 1, a schematic diagram of a structure for subdividing a Mini LED pixel island into a first sub-pixel in the related art is shown. A Mini LED pixel island can be subdivided into multiple first sub-pixels 21. Specifically, an etching process can be used to divide the P-electrode layer of the Mini LED chip into multiple first electrodes 211 of the first sub-pixels 21, and the P-type semiconductor layer is divided into multiple first semiconductor layers 212 of the first sub-pixels 21. The multiple first sub-pixels 21 can share an N-type semiconductor layer (second semiconductor layer 214) and a quantum well layer (MQW) 213. In this way, a Mini LED pixel island is subdivided into multiple first sub-pixels 21, each of which is Micro LED-level in size. After the first sub-pixels 21 are subdivided, the Mini LED pixel island needs to be transferred to the driver backplane of the glass substrate. The P-electrode pad (first electrode pad 31) and the common N-electrode pad (second electrode pad 31') of each first sub-pixel on the Mini LED pixel island are respectively bonded to the positive and negative electrode pads reserved on the driver backplane.

[0067] In the related art, multiple first sub-pixels of the same luminous color in the same row are usually regarded as a pixel island. Since the pixel islands need to be transferred to the driver backplane, the difficulty of alignment during the transfer process is undoubtedly increased. As shown in Figures 2 and 3, Figure 2 is a planar schematic diagram of each Mini LED pixel island in a display panel provided by an embodiment of the present disclosure, and Figure 3 is an enlarged schematic diagram within the dotted box A in Figure 2, including multiple rows and columns of pixel units (R, G, B) of different luminous colors. The pixel units in the same row have the same luminous color, and the pixel units of different luminous colors in the same column (R, G, B) are arranged alternately. For example, the pixel units in the same column are arranged in the order of R, G, B, R, G, B, R, G, B...; each pixel unit (for example, R) includes at least two pixel islands 2 (for example, three) arranged at intervals. The at least two pixel islands 2 in each pixel unit (for example, R) are staggered along the row direction X, and the outermost adjacent first sub-pixels 21 of adjacent pixel islands 2 in each pixel unit (for example, R) are staggered along the row direction X. The arrangement of the pixel islands 2 shown in FIG. 2 provided by the embodiment of the present invention can reduce the difficulty of alignment when the pixel islands 2 are transferred to the driving backplane for binding connection.

[0068] FIG2 takes the example of each pixel island 2 being subdivided into 17 first sub-pixels 21. In actual manufacturing, the number of first sub-pixels 21 subdivided into each pixel island 2 is greater. For example, as shown in FIG4 , each pixel island 2 is subdivided into 65 sub-pixels 21. Theoretically, a P-electrode pad as shown in FIG1 should be provided vertically above each first sub-pixel 21. However, since the spacing along the row direction X of the subdivided first sub-pixels 21 in each pixel island 2 is very small, generally less than 10 μm, and the width of the P-electrode pad of each first sub-pixel 21 is generally greater than the width of the P electrode, it is insufficient to form a P-electrode pad corresponding to each first sub-pixel 21 vertically above each first sub-pixel 21. In addition, the P-electrode pad must be bound and connected to the positive electrode pad on the driving backplane in a one-to-one correspondence. The positive electrode pad on the driving backplane needs to be electrically connected to the driving circuit in a one-to-one correspondence. Since the number of first sub-pixels 21 subdivided into each pixel island 2 is large, the number of driving circuits on the driving backplane also increases, and the area occupied by the driving circuit is large. Therefore, each positive electrode pad cannot be formed vertically above each driving circuit. Therefore, for the current solution of subdividing each pixel island into a number of first sub-pixels, how to achieve an effective binding connection between the pixel island and the driving backplane is a problem that those skilled in the art urgently need to solve.

[0069] In view of this, an embodiment of the present disclosure provides a display panel having a display area, as shown in FIG2 and FIG5-FIG10. FIG2 and FIG5-FIG10 only illustrate the display area. FIG5 is a cross-sectional schematic diagram corresponding to a pixel island in the display panel. FIG6 is a plan schematic diagram of specific film layers in a pixel island corresponding to three pixel units (R, G, B) in FIG2 (taking the number of first sub-pixels in a pixel island as 65 as an example). FIG7 is a plan schematic diagram corresponding to a pixel island in FIG6. FIG8 is a plan schematic diagram of a portion of the film layers in a driver backplane corresponding to the pixel island shown in FIG2. FIG9 is an enlarged schematic diagram within the dotted box B in FIG8. FIG10 is a partially enlarged schematic diagram of FIG9. The display area of ​​the display panel includes:

[0070] The driving backplane 1, as shown in FIG5 and FIG8-FIG10, includes a substrate 11, a plurality of driving circuits 12 arrayed on the substrate 11, and a plurality of positive electrode pads 13 located on a side of the driving circuits 12 away from the substrate 11;

[0071] A plurality of pixel islands 2, as shown in FIG2 and FIG5 to FIG7, are located on the driving backplane 1, and each pixel island 2 includes a plurality of first sub-pixels 21 of the same color;

[0072] Multiple first electrode pad groups 3, as shown in Figures 5 to 7, are located between multiple pixel islands 2 and the driving backplane 1. The first electrode pad groups 3 correspond to the pixel islands 2 one by one, and the orthographic projections of the first electrode pad groups 3 on the substrate 11 are located within the orthographic projection range of the corresponding pixel islands 2 on the substrate 11. Each first electrode pad group 3 includes multiple first electrode pads 31, and the first electrode pads 31 are bound and connected to the positive electrode pad 13.

[0073] As shown in FIG6 and FIG7, the number of rows of the first electrode pads 31 in each first electrode pad group 3 is greater than the number of rows of the first sub-pixels 21 in each pixel island 2, and the number of columns of the first electrode pads 31 in each first electrode pad group 3 is less than the number of columns of the first sub-pixels 21 in each pixel island 2;

[0074] As shown in FIG5-FIG7 , the first electrode pad 31 is electrically connected to the first sub-pixel 21 through the first lead 4 ; as shown in FIG5 , FIG9 and FIG10 , the positive electrode pad 13 is electrically connected to the driving circuit 12 through the second lead 5 .

[0075] The display panel provided by the embodiment of the present disclosure arranges the number of rows of the first electrode pads 31 in the first electrode pad group 3 corresponding to each pixel island 2 to be greater than the number of rows of the first sub-pixels 21 in each pixel island 2, and arranges the number of columns of the first electrode pads 31 in the first electrode pad group 3 corresponding to each pixel island 2 to be less than the number of columns of the first sub-pixels 21 in each pixel island 2. In this way, the plurality of first electrode pads 31 that originally need to be arranged one-to-one vertically above each first sub-pixel 21 in each pixel island 2 are rearranged. For example, the embodiment of the present disclosure takes each pixel island 2 as an example, in which 65 first sub-pixels are arranged in two rows, the first row includes 33 first sub-pixels 21, and the second row includes 32 first sub-pixels. By arranging the 65 first electrode pads 31 corresponding to each pixel island 2 into five rows and thirteen columns, and electrically connecting each first electrode pad 31 to the corresponding first sub-pixel 21 through the first lead 4, the problem in the related art of insufficient first electrode pads 31 corresponding one-to-one vertically above each first sub-pixel 21 can be solved.

[0076] It should be noted that FIG5 is a schematic diagram showing the driving backplane 1 and the pixel island 2 after alignment but before bonding.

[0077] Optionally, as shown in FIG6 and FIG7 , the multiple first electrode pads 31 corresponding to each pixel island 2 may be distributed at equal intervals, and the distance between two adjacent first electrode pads 31 may be the same as or different from the distance between adjacent first sub-pixels 21 .

[0078] It should be noted that, in the embodiment of the present disclosure, one pixel island is subdivided into 65 first sub-pixels, and the 65 first sub-pixels are arranged into two rows, with 33 first sub-pixels arranged in the first row and 32 first sub-pixels arranged in the second row. The first sub-pixels of the two rows are staggered in the row direction, and the first electrode pads are arranged in 5 rows and 13 columns as an example; if one pixel island is subdivided into 66 first sub-pixels, the first electrode pads can be arranged in 6 rows and 11 columns, or in 3 rows and 22 columns; if one pixel island is subdivided into 61 first sub-pixels, the first electrode pads can be arranged in 6 rows and 11 columns, or in 3 rows and 22 columns. If a pixel island is subdivided into 62 first sub-pixels, the corresponding 61 first electrode pads cannot be divided into M rows × N columns (M needs to be greater than 2), then the first electrode pads can also be arranged into 5 rows and 13 columns, and the last column only includes 1 first electrode pad; if a pixel island is subdivided into 62 first sub-pixels, the first electrode pads can also be arranged into 5 rows and 13 columns, then the last column only includes 2 first electrode pads; the arrangement of the first electrode pads corresponding to each pixel island can be determined according to the number of first sub-pixels subdivided in a pixel island.

[0079] In a specific implementation, since the positive electrode pads of the driving backplane need to be bound and connected to the first electrode pads electrically connected to the pixel islands in a one-to-one correspondence, the positions of the positive electrode pads corresponding to each pixel island need to correspond one-to-one with the first electrode pads corresponding to the pixel island. Since the driving circuit occupies a large area, the positive electrode pads cannot be arranged vertically above the driving circuits. Therefore, in the above-mentioned display panel provided by the embodiment of the present disclosure, as shown in Figures 8 and 9, the multiple positive electrode pads 13 are divided into multiple positive electrode pad groups 10. The positive electrode pad group 10 in Figure 9 corresponds one-to-one to the first electrode pad group 3 in Figure 6.

[0080] As shown in FIG9 , a plurality of driving circuits 12 are divided into a plurality of driving circuit groups 20, and the driving circuit groups 20 correspond one-to-one to the positive electrode pad groups 10, and the orthographic projection area of ​​each positive electrode pad group 10 on the substrate 11 is smaller than the orthographic projection area of ​​the driving circuit group 20 on the substrate 11. Specifically, as shown in FIG9 , since the positions of the positive electrode pad groups 10 need to correspond one-to-one to the positions of the first electrode pad groups 3 shown in FIG6 , and since the driving circuits 12 occupy a large area, each positive electrode pad group 10 only occupies a local area above the corresponding driving circuit group 20. For example, each rectangle represents a driving circuit 12, and a plurality of driving circuits 12 are evenly distributed on the substrate. For example, the 65 positive electrode pads 13 in the upper left corner of FIG9 need to be bound one-to-one with the 65 first electrode pads 31 corresponding to the pixel island 2 in the upper left corner of FIG6 , that is, the 65 positive electrode pads in the upper left corner of FIG9 The disk 13 only occupies a local area above the corresponding driving circuit group 20, that is, the 65 first electrode pads 31 cannot be set vertically above each driving circuit 12, then the 65 first electrode pads 31 need to be electrically connected to the corresponding driving circuit 12 through the second lead 5, which solves the problem of how to electrically connect the positive electrode pad 13 and the driving circuit 12 due to the need to match the position of the positive electrode pad 13 corresponding to each pixel island 2 with the position of the first electrode pad 13, thereby realizing an effective binding connection between the pixel island 2 and the driving backplane 1, and realizing independent control of the light emission of each first sub-pixel 21.

[0081] Therefore, in the embodiment of the present disclosure, each driving circuit 12 is electrically connected to the positive electrode pad 13 in a one-to-one correspondence through the second lead 5 , thereby realizing one-to-one driving of multiple viewpoints during light field display.

[0082] Optionally, the driving circuit may be a driving circuit with a compensation function, and may be a PAM drive, a PWM drive, or a PAM+PWM drive, such as a 3T1C pixel circuit or a 7T1C pixel circuit. The driving circuit may correspond one-to-one with each first sub-pixel, or may be a time-division multiplexing circuit in which one driving circuit corresponds to multiple first sub-pixels. In the disclosed embodiment, the driving circuit corresponds one-to-one with each first sub-pixel.

[0083] Optionally, the material of the substrate can be formed of at least one of polymer materials such as polyimide (PI), polyethylene (PE), polypropylene (PP), polyethylene terephthalate (PET), polycarbonate (PC), and fiber reinforced plastic (FRP).

[0084] In a specific implementation, in the above-mentioned display panel provided by the embodiment of the present disclosure, as shown in Figures 8 to 10, since each positive electrode pad group 10 includes 5 rows and 13 columns of positive electrode pads 13, the corresponding driving circuits 12 electrically connected to the positive electrode pad group 10 are also arranged in 5 rows and 13 columns. For example, the first row of positive electrode pads 13 in the 5 rows and 13 columns of positive electrode pads 13 are electrically connected to the first row of driving circuits 12 through the corresponding second lead 5, the second row of positive electrode pads 13 are electrically connected to the second row of driving circuits 12 through the corresponding second lead 5, the third row of positive electrode pads 13 are electrically connected to the third row of driving circuits 12 through the corresponding second lead 5, and the fourth row of positive electrode pads 13 are electrically connected to the fourth row of driving circuits 12 through the corresponding second lead 5. The fifth row of positive electrode pads 13 are electrically connected to the fifth row of driving circuit 12, and the fifth row of positive electrode pads 13 are electrically connected to the fifth row of driving circuit 12 through the corresponding second lead 5; in order to avoid each second lead 5 occupying the frame area, each second lead 5 is arranged to be routed from the gap between two adjacent rows of first sub-pixels 21 and / or the gap between two adjacent columns of first sub-pixels. Therefore, in the above-mentioned display panel provided by the embodiment of the present disclosure, as shown in Figures 9 and 10, the orthographic projection of the second lead 5 on the substrate 11 can be located within the orthographic projection range of the gap between two adjacent rows of first sub-pixels 21 on the substrate 11, and / or the orthographic projection of the second lead 5 on the substrate 11 is located within the orthographic projection range of the gap between two adjacent columns of first sub-pixels 21 on the substrate 11. For example, the orthographic projections of the second leads 5 corresponding to the positive electrode pads 13 in the first and second rows on the substrate 11 are located within the orthographic projection range of the gap between the first sub-pixels 21 in two adjacent rows on the substrate 11; the orthographic projections of the second leads 5 corresponding to the positive electrode pads 13 in the third to fifth rows on the substrate 11 are partially located within the orthographic projection range of the gap between the first sub-pixels 21 in two adjacent rows on the substrate 11, and the other partially located within the orthographic projection range of the gap between the first sub-pixels 21 in two adjacent columns on the substrate 11. Of course, the orthographic projections of the second leads 5 on the substrate 11 can also be located within the orthographic projection range of the gap between the first sub-pixels 21 in two adjacent columns on the substrate 11. The routing of each second lead 5 can be set according to actual needs, as long as each positive electrode pad 13 can be electrically connected to the corresponding drive circuit 12 via the second lead 5.

[0085] In a specific implementation, in the above-mentioned display panel provided by the embodiment of the present disclosure, as shown in Figures 5, 9 and 10, some of the second leads 5 electrically connected to the positive electrode pads 13 (for example, the first row, the second row and the fifth row) can be directly routed using the same metal layer, but the second lead 5 electrically connected to the positive electrode pad 13 of the third row will have an overlapping area with the second lead 5 corresponding to the positive electrode pad 13 of the fourth row, and the second lead 5 electrically connected to the positive electrode pad 13 of the fourth row will have an overlapping area with the second lead 5 corresponding to the positive electrode pad 13 of the fifth row, that is, at least part of the second lead 5 has an overlapping area with other second leads 5. If the second lead 5 electrically connected to the positive electrode pads 13 of the third and fourth rows adopts the same metal layer routing, it will be short-circuited with the second lead 5 electrically connected to the corresponding fourth and fifth rows. Therefore, the positive electrode pads 13 of the third and fourth rows are electrically connected. The second lead 5 needs to be bridged in the overlapping area with the second lead 5 electrically connected to other rows. Therefore, for two second leads 5 with overlapping areas (for example, the second lead 5 electrically connected to the first positive electrode pad 13 from the left in the fourth row and the second lead 5 electrically connected to the second positive electrode pad 13 from the left in the fifth row have an overlapping area), one of the two second leads 5 needs to be bridged by a bridging portion 6 in the overlapping area. For example, the second lead 5 electrically connected to the second positive electrode pad 13 from the left in the fifth row uses the same metal layer routing, and the second lead 5 electrically connected to the first positive electrode pad 13 from the left in the fourth row needs to use two layers of metal layer routing, that is, the same metal layer routing as the second lead 5 electrically connected to the second positive electrode pad 13 from the left in the fifth row is used in the non-overlapping area (on both sides of the overlapping area), and another layer of metal layer routing is used in the overlapping area.

[0086] In a specific implementation, in the above-mentioned display panel provided by the embodiment of the present disclosure, as shown in FIG5 and FIG11, FIG11 is for the purpose of clearly illustrating the structure of the driving backplane and only illustrates a partial structure in FIG5, the driving backplane 1 further includes a first insulating layer 14, a first metal layer 15, a second insulating layer 16 and a second metal layer 17 stacked in sequence between the driving circuit 12 and the positive electrode pad 13, and the first insulating layer 14 is close to the driving circuit 12; wherein,

[0087] A portion of the second lead 5 (for example, the second lead 5 on the right side in FIG11 ) is located on the first metal layer 15 ;

[0088] Another part of the second lead 5 (for example, the second lead 5 on the left side in Figure 11) includes a first sub-lead 51, a bridging portion 53 and a second sub-lead 52. The first sub-lead 51 and the second sub-lead 52 are both located in the first metal layer 15, and the bridging portion 53 is located in the second metal layer 17; wherein, one end of the first sub-lead 51 is electrically connected to the drive circuit 12 through a via passing through the first insulating layer 14, the other end of the first sub-lead 51 is electrically connected to one end of the bridging portion 53 through a via passing through the second insulating layer 16, one end of the second sub-lead 52 is electrically connected to the other end of the bridging portion 53 through a via passing through the second insulating layer 16, and the other end of the second sub-lead 52 is electrically connected to the positive electrode pad 13; for example, the second lead 5 electrically connected to the second positive electrode pad 13 from the left in the fifth row in Figure 10 is located in the first metal layer 15, and the second lead 5 electrically connected to the first positive electrode pad 13 from the left in the fourth row includes a first sub-lead 51, a bridging portion 53 and a second sub-lead 52.

[0089] As shown in Figures 13 to 15, in order to more clearly illustrate the driving circuit 12, the first metal layer 15 and the second metal layer 17 in the schematic diagram 10, Figure 13 is a plan schematic diagram of the driving circuit 12 in Figure 10, and the multiple small square boxes in Figure 13 represent the connection positions of the subsequent second lead 5 and the driving circuit 12. Figure 14 is a plan schematic diagram of the second lead 5, the first sub-lead 51 and the second sub-lead 52 included in the first metal layer 15 in Figure 10 set on the basis of Figure 13. Figure 15 is a plan schematic diagram of the second metal layer 17 (bridging portion 53) in Figure 10 set on the basis of Figure 14. Figure 10 is a plan schematic diagram of the positive electrode pad 13 set on the basis of Figure 15.

[0090] In a specific implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, as shown in Figures 5 and 11, the driving backplane 1 also includes: a first flat layer 18 located between the second metal layer 17 and the positive electrode pad 13, and a third insulating layer 19 located between the first flat layer 18 and the positive electrode pad 13; the other end of the second sub-lead 52 is electrically connected to the positive electrode pad 13 through a via hole that passes through the second insulating layer 16, the first flat layer 18 and the third insulating layer 19 in sequence.

[0091] Specifically, as shown in FIG5 and FIG11 , the second lead directly located on the first metal layer 15 is electrically connected to the positive electrode pad 13 through via holes penetrating the second insulating layer 16 , the first planar layer 18 and the third insulating layer 19 in sequence.

[0092] In a specific implementation, in the display panel provided by the embodiment of the present disclosure, as shown in FIG5 and FIG12 , FIG12 only illustrates a partial structure in FIG5 for the purpose of clearly illustrating the structure of the pixel island. Each first sub-pixel 21 includes a stacked first electrode 211 (i.e., a P-electrode), a first semiconductor layer 212 (i.e., a P-type semiconductor layer), a quantum well layer 213, a second semiconductor layer 214 (i.e., an N-type semiconductor layer), and a second electrode 215 (i.e., an N-electrode). The first electrode 211 is close to the driving backplane 1.

[0093] The display panel further includes a fourth insulating layer 6 located between the first electrode 211 and the first electrode pad 31 , one end of the first lead 4 is electrically connected to the first electrode pad 31 , and the other end of the first lead 4 is electrically connected to the first electrode 211 through a via hole penetrating the fourth insulating layer 6 .

[0094] It should be noted that in FIG6 and FIG7 , each first sub-pixel 21 is illustrated by a subdivided first electrode 211 , an array of first electrode pads 31 is distributed on the subdivided first electrode 211 , and a fourth insulating layer 6 is provided between the first electrode pads 31 and the first electrode 211 .

[0095] It should be noted that FIG7 takes the shape of the subdivided first electrode 211 as a parallelogram as an example. Of course, the shape of the subdivided first electrode 211 may also be a rectangle, as shown in FIG16 , but is certainly not limited thereto.

[0096] In a specific implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, as shown in Figures 5 and 12, the pixel island also includes a sapphire substrate 216 arranged on the side of the second electrode 215 away from the first electrode pad 31 and a buffer layer (not shown) located between the sapphire substrate 216 and the second electrode 215.

[0097] Optionally, the material of the buffer layer may be gallium nitride (GaN), the material of the first semiconductor layer 212 may be p-GaN, and the material of the second semiconductor layer 214 may be n-GaN.

[0098] In a specific implementation, in the display panel provided in the embodiments of the present disclosure, as shown in Figures 5 and 12 , the first electrode pad 31 and the first lead 4 can be provided on the same layer. In this way, the pattern of the first lead 4 and the first electrode pad 31 can be formed in a single patterning process simply by changing the original pattern when forming the first electrode pad 31. This eliminates the need for a separate process for preparing the first lead 4, simplifying the manufacturing process, saving production costs, and improving production efficiency.

[0099] In a specific implementation, in the display panel provided by the embodiments of the present disclosure, as shown in FIG5 and FIG12 , the quantum well layer 213 of each first sub-pixel 21 within the same pixel island can be an integral structure, the second semiconductor layer 214 of each first sub-pixel 21 within the same pixel island can be an integral structure, and the second electrode 215 of each first sub-pixel 21 within the same pixel island can be an integral structure. That is, each first sub-pixel 21 within the same pixel island shares the quantum well layer 213, the second semiconductor layer 214, and the second electrode 215, and different first sub-pixels 21 are defined by dividing the first semiconductor layer 212 and the first electrode 211.

[0100] In a specific implementation, the display panel provided in the embodiment of the present disclosure, as shown in Figures 5, 6, and 12, further includes a second electrode pad 31' provided in the same layer as the first electrode pad 31. The second electrodes 215 within the same pixel island are electrically connected to the same second electrode pad 31', while the second electrodes 215 within different pixel islands are electrically connected to different second electrode pads 31'. That is, the first sub-pixels 21 within the same pixel island share the same second electrode pad 31'.

[0101] In a specific implementation, in the display panel provided by the embodiment of the present disclosure, as shown in FIG6 , the second electrode pad 31 ′ may be located in a region between two adjacent columns of the first electrode pad groups 3 .

[0102] In a specific implementation, in the display panel provided in the embodiment of the present disclosure, as shown in Figures 5, 8-11, the driving backplane 1 further includes a negative electrode pad 13' provided on the same layer as the positive electrode pad 13. The negative electrode pad 13' is bound and connected to the second electrode pad 31'. That is, the position of the negative electrode pad 13' corresponds one-to-one with the position of the second electrode pad 31'.

[0103] Alternatively, the material of the positive electrode pad 13 and the negative electrode pad 13' can be a bonding metal such as electroplated Cu. As shown in FIG11 , the thickness of the electroplated Cu can be greater than or equal to the sum of the thicknesses of the second insulating layer 16 , the first planar layer 18 , and the third insulating layer 19 , to ensure a bonded connection with the first electrode pad 31 and the second electrode pad 31' shown in FIG12 .

[0104] In a specific implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, as shown in Figures 5 and 11, the driving backplane 1 also includes: a fifth insulating layer 110 located on the side of the positive electrode pad 13 away from the substrate 11, and a second flat layer 111 located on the side of the fifth insulating layer 110 away from the substrate 11; the fifth insulating layer 110 and the second flat layer 111 have a first exposed area exposing the positive electrode pad 13 and a second exposed area exposing the negative electrode pad 13', the first electrode pad 31 shown in Figure 12 is bound and connected to the positive electrode pad 13 through the first exposed area, and the second electrode pad 31' shown in Figure 12 is bound and connected to the negative electrode pad 13' through the second exposed area.

[0105] In a specific implementation, in the display panel provided in the embodiment of the present disclosure, as shown in Figures 5 and 11, the driving circuit 12 includes a first gate electrode 121, a first gate insulating layer 122, an active layer 123, a second gate insulating layer 124, a second gate electrode 125, an interlayer insulating layer 126, and source and drain electrodes (source electrode 127 and drain electrode 128), which are stacked in sequence between the substrate 11 and the first insulating layer 14. One end of the first sub-lead 51 is electrically connected to the drain electrode 128 of the driving circuit 12 through a via hole penetrating the first insulating layer 14. The drain electrode 128 is electrically connected to the active layer 123. The source electrode 127 of the driving circuit 12 is electrically connected to the first gate electrode 121 and the second gate electrode 125, respectively. The driving circuit 12 provided in the embodiment of the present disclosure adopts a dual-gate structure, which can reduce leakage current.

[0106] In a specific implementation, in the display panel provided by the embodiment of the present disclosure, as shown in FIG5 and FIG11 , the driving backplane 1 further includes: a first conductive connection portion 112 and a second conductive connection portion 113 located on the first metal layer 14 , a low voltage power line VSS and a high voltage power line VDD provided on the same layer as the source and drain electrodes (the source electrode 127 and the drain electrode 128 ), a third conductive connection portion 114 and a fourth conductive connection portion 115 provided on the same layer as the second gate electrode 125 , and a shielding electrode 116 provided on the same layer as the first gate electrode 121 ;

[0107] The negative electrode pad 13' is electrically connected to the first conductive connection portion 112 through a via penetrating the third insulating layer 19, the first flat layer 18 and the second insulating layer 16. The first conductive connection portion 112 is electrically connected to the low voltage power line VSS through a via penetrating the first insulating layer 14. The low voltage power line VSS is electrically connected to the third conductive connection portion 114 through a via penetrating the interlayer insulating layer 126. The second conductive connection portion 113 is electrically connected to the high voltage power line VDD through a via penetrating the first insulating layer 14. The high voltage power line VDD is electrically connected to the fourth conductive connection portion 115 through a via penetrating the interlayer insulating layer 126. The high voltage power line VDD is electrically connected to the shielding electrode 116 through a via penetrating the interlayer insulating layer 126, the second gate insulating layer 124 and the first gate insulating layer 122.

[0108] In a specific implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, as shown in Figures 2 and 9, a plurality of pixel islands 2 are arranged at intervals along the row direction X and the column direction Y, the negative electrode pads 13' electrically connected to each pixel island 2 located in the same column are electrically connected to the same low-voltage power line VSS, the driving circuits 12 electrically connected to each pixel island 2 located in the same column are electrically connected to the same high-voltage power line VDD, and a high-voltage power line VDD and a low-voltage power line VSS are provided in the gap between two adjacent columns of pixel islands 2.

[0109] In a specific implementation, in the display panel provided in the embodiment of the present disclosure, as shown in FIG2 , a plurality of first sub-pixels 21 within each pixel island 2 are arranged at intervals along the row direction X and the column direction Y. The first sub-pixels 21 in each row within each pixel island 2 are sequentially staggered along the row direction X, and the distance D1 between adjacent first sub-pixels 21 in the same row is less than the width W of the first sub-pixel 21 along the row direction X. In this way, more first sub-pixels 21 can be arranged within each pixel island 2, and when the display panel is applied to 3D light field display, the number of viewpoints can be increased.

[0110] In a specific implementation, in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 2 , the distance D2 between the center lines of any two adjacent first sub-pixels 21 along the column direction Y is equal.

[0111] In specific implementation, the display panel provided by the embodiment of the present disclosure can be applied to a large-size, ultra-multi-viewpoint 3D light field display screen, which requires splicing multiple small-size screens to form a large-size display screen. The gaps between the spliced ​​screens will make the 3D viewpoint display effect discontinuous. In order to avoid the presence of gaps in the splicing, in the above-mentioned display panel provided by the embodiment of the present disclosure, as shown in Figure 17, Figure 17 is a planar schematic diagram of the display panel, the display panel 1000 also includes a splicing area BB arranged around the display area AA, each square blank area in Figure 17 includes a driving backplane structure corresponding to the 9 pixel islands 2 shown in Figure 9, and the display panel also includes a GOA driving circuit 100 (gate scan line driving circuit), an EOA driving circuit 200 (light-emitting scan line driving circuit) and a MUX circuit 300 (multiplexer). The GOA driving circuit 100 and the EOA driving circuit 200 are respectively arranged between two different adjacent columns of pixel units, and the MUX circuit 300 is arranged between two adjacent rows of pixel units. The present disclosure disposes the GOA driving circuit 100 and the EOA driving circuit 200 respectively between two adjacent columns of pixel units. This eliminates the need to fabricate the GOA driving circuit 100, the EOA driving circuit 200, and the MUX circuit 300 in the peripheral area of ​​the driving backplane 1, and eliminates the need to reserve a frame for fabricating the driving circuit on the driving backplane. This solves the problems of the display panel having a frame in the prior art solution, resulting in screen segmentation and image discontinuity after splicing large-size display screens. The present disclosure can reserve splicing areas BB at the upper, lower, left, and right edges of small-size display screens for glass trimming, edge grinding, and other losses, thereby achieving seamless splicing of the various display screens.

[0112] Specifically, as shown in FIG17 , it is assumed that the position between two adjacent columns of pixel units where the driving circuit 100 is located is the first position, and the position between two adjacent columns of pixel units where the EOA driving circuit 200 is located is the second position. FIG17 of the embodiment of the present disclosure takes the first position and the second position as an example where one column of pixel units is spaced apart. Of course, the first position and the second position may also be spaced apart by two columns of pixel units, three columns of pixel units, etc.

[0113] Optionally, the flexible printed circuit (FPC) and the driving chip (IC) in the driving backplane can be bent to the back side of the driving backplane using side wiring and backside bonding processes.

[0114] In a specific implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, the pixel island can be a Mini LED pixel island.

[0115] Based on the same inventive concept, embodiments of the present disclosure further provide a display device comprising at least one of the aforementioned display panels provided by embodiments of the present disclosure. Because the principles underlying the problems solved by this display device are similar to those of the aforementioned display panel, the implementation of this display device can refer to the implementation of the aforementioned display panel, and any repetitions will not be repeated.

[0116] In a specific implementation, the display device provided in the embodiment of the present disclosure further includes a plurality of lenses 400 located on the light-emitting side of the display panel 1000, as shown in FIG18 and FIG19 ; the lenses 400 may be micro lenses;

[0117] As shown in FIG18 , a plurality of lenses 400 correspond one-to-one to a plurality of pixel islands 2 , or, as shown in FIG19 , each lens 400 corresponds one-to-one to each first sub-pixel 21 in each pixel island 2 ;

[0118] Light emitted from each first sub-pixel 21 in each pixel island 2 is incident on the corresponding lens 400 .

[0119] In a specific implementation, in the display device provided in the embodiment of the present disclosure, as shown in FIG20 , the display panel 1000 further includes a splicing area BB disposed around the display area AA. The display device includes at least two spliced ​​display panels (taking the splicing of four display panels 1000 shown in FIG17 as an example), and the splicing area BB of the at least two spliced ​​display panels is provided with a plurality of second sub-pixels (not shown) arranged in the same manner as the first sub-pixels 21. In this way, the arrangement of the second sub-pixels in the splicing area BB can be set to be the same as the arrangement of the first sub-pixels 21 in the display panel, and the splicing area BB can also achieve normal display, so that the spliced ​​display screen displays continuously.

[0120] In the light field display device shown in Figures 18 and 19 of the embodiment of the present disclosure, each pixel island includes multiple first sub-pixels. Each pixel island can provide a sufficient number of subdivided viewpoints. The lens converges the light field information to form a continuous 3D light field display effect.

[0121] Specifically, the display device provided by the embodiment of the present disclosure can be a large-size, ultra-multi-viewpoint 3D light field display screen, such as used in cinemas / shopping mall advertising screens / multimedia conference rooms / outdoor advertising screens, providing a multi-viewpoint light field display effect with a large viewing angle and a large main lobe that can be viewed by multiple people.

[0122] The embodiments of the present disclosure provide a display panel and a display device, by setting the number of rows of first electrode pads in the first electrode pad group corresponding to each pixel island to be greater than the number of rows of first sub-pixels in each pixel island, and setting the number of columns of first electrode pads in the first electrode pad group corresponding to each pixel island to be less than the number of columns of first sub-pixels in each pixel island, thereby rearranging a plurality of first electrode pads that originally needed to be arranged one-to-one vertically above each first sub-pixel in each pixel island. For example, the embodiments of the present disclosure take each pixel island as an example, in which each pixel island includes 65 first sub-pixels and is arranged in rows, the first row includes 33 first sub-pixels, and the second row includes 32 first sub-pixels. By arranging the 65 first electrode pads corresponding to each pixel island into rows and columns, and electrically connecting each first electrode pad to the corresponding first sub-pixel through a first lead, the problem in the related art that it is insufficient to produce first electrode pads corresponding one-to-one to each first sub-pixel vertically above each first sub-pixel can be solved.

[0123] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0124] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, wherein: A display area is provided, wherein the display area includes: A driving backplane, comprising a substrate, a plurality of driving circuits arrayed on the substrate, and a plurality of positive electrode pads located on a side of the driving circuits facing away from the substrate; A plurality of pixel islands are located on the driving backplane, each of the pixel islands including a plurality of first sub-pixels of the same color; A plurality of first electrode pad groups are located between the plurality of pixel islands and the driving backplane, the first electrode pad groups correspond to the pixel islands one-to-one, and the orthographic projections of the first electrode pad groups on the substrate are located within the orthographic projection range of the corresponding pixel islands on the substrate; each first electrode pad group includes a plurality of first electrode pads, and the first electrode pads are bound and connected to the positive electrode pad; wherein, The number of rows of the first electrode pads in each of the first electrode pad groups is greater than the number of rows of the first sub-pixels in each of the pixel islands, and the number of columns of the first electrode pads in each of the first electrode pad groups is less than the number of columns of the first sub-pixels in each of the pixel islands; The first electrode pad is electrically connected to the first sub-pixel through a first lead, and the positive electrode pad is electrically connected to the driving circuit through a second lead.

2. The display panel according to claim 1 , wherein the plurality of positive electrode pads are divided into a plurality of positive electrode pad groups, and the positive electrode pad groups correspond to the first electrode pad groups one by one; The multiple driving circuits are divided into multiple driving circuit groups, each of the driving circuit groups corresponds to the positive electrode pad groups one by one, and the orthographic projection area of ​​each of the positive electrode pad groups on the substrate is smaller than the orthographic projection area of ​​the driving circuit group on the substrate.

3. The display panel according to claim 2, wherein: The orthographic projection of the second lead on the substrate is located within the orthographic projection range of the gap between two adjacent rows of the first sub-pixels on the substrate, and / or the orthographic projection of the second lead on the substrate is located within the orthographic projection range of the gap between two adjacent columns of the first sub-pixels on the substrate.

4. The display panel according to claim 3, wherein: At least some of the second leads have an overlapping area with other second leads. For the two second leads having the overlapping area, one of the second leads is connected to the overlapping area by a bridge portion.

5. The display panel according to any one of claims 1 to 4, wherein: The driving backplane further includes a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer stacked in sequence between the driving circuit and the positive electrode pad, wherein the first insulating layer is close to the driving circuit; A portion of the second lead is located on the first metal layer; The other part of the second lead includes a first sub-lead, the bridging portion and a second sub-lead, the first sub-lead and the second sub-lead are both located in the first metal layer, and the bridging portion is located in the second metal layer; wherein, one end of the first sub-lead is electrically connected to the drive circuit through a via hole passing through the first insulating layer, the other end of the first sub-lead is electrically connected to one end of the bridging portion through a via hole passing through the second insulating layer, one end of the second sub-lead is electrically connected to the other end of the bridging portion through a via hole passing through the second insulating layer, and the other end of the second sub-lead is electrically connected to the positive electrode pad.

6. The display panel according to claim 5, wherein: The driving backplane also includes: a first flat layer located between the second metal layer and the positive electrode pad, and a third insulating layer located between the first flat layer and the positive electrode pad; the other end of the second sub-lead is electrically connected to the positive electrode pad through a via hole that sequentially passes through the second insulating layer, the first flat layer and the third insulating layer.

7. The display panel according to claim 6, wherein: Each of the first sub-pixels includes a first electrode, a first semiconductor layer, a quantum well layer, a second semiconductor layer, and a second electrode that are stacked, and the first electrode is close to the driving backplane; The display panel further includes a fourth insulating layer located between the first electrode and the first electrode pad, one end of the first lead is electrically connected to the first electrode pad, and the other end of the first lead is electrically connected to the first electrode through a via hole penetrating the fourth insulating layer.

8. The display panel according to claim 7, wherein: The first electrode pad is provided on the same layer as the first lead.

9. The display panel according to claim 7, wherein: The quantum well layer of each of the first sub-pixels in the same pixel island is an integrated structure, the second semiconductor layer of each of the first sub-pixels in the same pixel island is an integrated structure, and the second electrode of each of the first sub-pixels in the same pixel island is an integrated structure.

10. The display panel according to any one of claims 7 to 9, wherein: It also includes a second electrode pad arranged in the same layer as the first electrode pad, the second electrodes in the same pixel island are electrically connected to the same second electrode pad, and the second electrodes in different pixel islands are electrically connected to different second electrode pads.

11. The display panel according to claim 10, wherein: The second electrode pad is located in a region between two adjacent columns of the first electrode pad groups.

12. The display panel according to claim 10 or 11, wherein: The driving backplane further includes a negative electrode pad provided on the same layer as the positive electrode pad, and the negative electrode pad is bound and connected to the second electrode pad.

13. The display panel according to claim 12, wherein: The driving backplane also includes: a fifth insulating layer located on the side of the positive electrode pad facing away from the substrate, and a second flat layer located on the side of the fifth insulating layer facing away from the substrate; the fifth insulating layer and the second flat layer have a first exposed area exposing the positive electrode pad and a second exposed area exposing the negative electrode pad, the first electrode pad is bound and connected to the positive electrode pad through the first exposed area, and the second electrode pad is bound and connected to the negative electrode pad through the second exposed area.

14. The display panel according to claim 13, wherein: The driving circuit includes a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, a second gate, an interlayer insulating layer and a source-drain electrode stacked in sequence between the substrate and the first insulating layer; one end of the first sub-lead is electrically connected to the drain electrode of the driving circuit through a via hole penetrating the first insulating layer, the drain electrode is electrically connected to the active layer, and the source electrode of the driving circuit is electrically connected to the first gate and the second gate respectively.

15. The display panel according to claim 14, wherein: The driving backplane further includes: a first conductive connection portion and a second conductive connection portion located on the first metal layer, a low voltage power line and a high voltage power line provided on the same layer as the source and drain electrodes, a third conductive connection portion and a fourth conductive connection portion provided on the same layer as the second gate electrode, and a shielding electrode provided on the same layer as the first gate electrode; The negative electrode pad is electrically connected to the first conductive connection portion through a via penetrating the third insulating layer, the first flat layer and the second insulating layer, the first conductive connection portion is electrically connected to the low voltage power line through a via penetrating the first insulating layer, the low voltage power line is electrically connected to the third conductive connection portion through a via penetrating the interlayer insulating layer, the second conductive connection portion is electrically connected to the high voltage power line through a via penetrating the first insulating layer, the high voltage power line is electrically connected to the fourth conductive connection portion through a via penetrating the interlayer insulating layer, and the high voltage power line is electrically connected to the shielding electrode through a via penetrating the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

16. The display panel according to claim 15, wherein: The multiple pixel islands are arranged at intervals along the row direction and the column direction, the negative electrode pads electrically connected to the pixel islands in the same column are electrically connected to the same low-voltage power line, the driving circuits electrically connected to the pixel islands in the same column are electrically connected to the same high-voltage power line, and a high-voltage power line and a low-voltage power line are arranged in the gap between the pixel islands in two adjacent columns.

17. The display panel according to any one of claims 1 to 16, wherein: It includes multiple rows and columns of pixel units with different luminous colors, wherein the pixel units in the same row have the same luminous color, and the pixel units in the same column with different luminous colors are alternately arranged; Each of the pixel units includes at least two pixel islands spaced apart from each other, at least two pixel islands within each pixel unit are staggered along a row direction, and the outermost adjacent first sub-pixels of adjacent pixel islands within each pixel unit are staggered along a row direction.

18. The display panel according to claim 17, wherein: The multiple first sub-pixels in each pixel island are arranged at intervals along the row direction and the column direction, and the first sub-pixels in each row in each pixel island are staggered in sequence along the row direction, and the distance between adjacent first sub-pixels in the same row is less than the width of the first sub-pixel along the row direction.

19. The display panel according to claim 18, wherein: The distance between the center lines of any two adjacent first sub-pixels along the column direction is equal.

20. The display panel according to any one of claims 17 to 19, wherein: It also includes a GOA driving circuit, an EOA driving circuit and a MUX circuit. The GOA driving circuit and the EOA driving circuit are respectively arranged between two different adjacent columns of the pixel units, and the MUX circuit is arranged between two adjacent rows of the pixel units.

21. The display panel according to any one of claims 1 to 20, wherein: The pixel island is a Mini LED pixel island.

22. A display device, wherein: The device comprises at least one display panel according to any one of claims 1 to 21.

23. The display device according to claim 22, wherein: Also included are a plurality of lenses located on the light-emitting side of the display panel; The plurality of lenses correspond one-to-one to the plurality of pixel islands, or each of the lenses corresponds one-to-one to each of the first sub-pixels in each of the pixel islands; The light emitted by each first sub-pixel in each pixel island is incident on the corresponding lens.

24. The display device according to claim 22 or 23, wherein: The display panel further includes a splicing area arranged around the display area. The display device includes at least two spliced ​​display panels. The splicing area of ​​at least two display panels is provided with a plurality of second sub-pixels arranged in the same manner as the first sub-pixels.