Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a light-emitting unit (OLED). The display panel further comprises a base substrate (91), a light-shielding layer, a pixel defining layer (PDL), and a plurality of functional layers. The base substrate (91) comprises a light-transmitting area. The light-shielding layer is located on one side of the base substrate (91), and the light-shielding layer has a light-shielding effect. The pixel defining layer (PDL) is located on the side of the light-shielding layer facing away from the base substrate (91), a pixel opening (PH) is formed on the pixel defining layer (PDL), and the pixel opening (PH) is used for forming the light-emitting unit (OLED). The plurality of functional layers are located between the base substrate (91) and the pixel defining layer (PDL), and the orthographic projections of light-shielding structures of all the functional layers located between the base substrate (91) and the pixel defining layer (PDL) on the base substrate (91) are located outside the light-transmitting area. A first opening (H1) is formed on the light-shielding layer, and the orthographic projection of the first opening (H1) on the base substrate (91) is located in the light-transmitting area.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a display panel with a high pixel density, the light transmittance of the display panel is relatively low, so the display panel cannot meet the light transmittance requirements of technologies such as fingerprint recognition and under-screen cameras.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, comprising a light-emitting unit, and further comprising: a base substrate, a light-shielding layer, a pixel-defining layer, and a multi-layer functional layer. The base substrate comprises a light-transmitting area; the light-shielding layer is located on one side of the base substrate, and the light-shielding layer has a light-shielding function; the pixel-defining layer is located on a side of the light-shielding layer facing away from the base substrate, and a pixel opening is formed on the pixel-defining layer, wherein the light-emitting unit is formed within the pixel opening; the multi-layer functional layer is located between the base substrate and the pixel-defining layer, and the light-shielding structures of all functional layers located between the base substrate and the pixel-defining layer have their orthographic projections on the base substrate located outside the light-transmitting area; the light-shielding layer has a first opening formed on the light-shielding layer, and the orthographic projection of the first opening on the base substrate is located in the light-transmitting area.

[0006] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit for driving the light-emitting unit, and the pixel driving circuit includes a driving transistor; the multi-layer functional layer includes: a first active layer, the first active layer includes a third active portion, and the third active portion is used to form a channel region of the driving transistor; the light-shielding layer is located between the first active layer and the base substrate, the light-shielding layer includes a first light-shielding portion, and the orthographic projection of the first light-shielding portion on the base substrate covers the orthographic projection of the third active portion on the base substrate.

[0007] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a fourth transistor, wherein the first electrode of the first transistor is connected to a first initial signal line, the second electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the fourth transistor is connected to a data line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor; the display panel further includes: a first reset signal line and a second gate line, the orthographic projection of the first reset signal line on the substrate extends along a first direction, and a partial structure of the first reset signal line is used to form a top gate of the first transistor; the orthographic projection of the second gate line on the substrate extends along the first direction, and a partial structure of the second gate line is used to form the gate of the fourth transistor; wherein the orthographic projection of the first opening on the substrate is located between the orthographic projections of the first reset signal line and the second gate line on the substrate in the same pixel driving circuit.

[0008] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of repeating units, and the plurality of repeating units are arrayed in a first direction and a second direction, and the first direction and the second direction intersect; the repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are arranged in mirror symmetry.

[0009] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor being connected to a data line, and a second electrode of the fourth transistor being connected to the first electrode of the driving transistor; an orthographic projection of the data line on the substrate extends along the second direction, and an orthographic projection of the first opening on the substrate is located between the orthographic projections of two adjacent data lines on the substrate in the same repeating unit.

[0010] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a sixth transistor and a seventh transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; the first active layer further includes: a sixth active portion, a seventh active portion, and an eighth active portion, the sixth active portion is used to form a channel region of the sixth transistor; the seventh active portion is used to form a channel region of the seventh transistor; the eighth active portion is connected between the sixth active portion and the seventh active portion; the light-shielding layer further includes: a second light-shielding portion, the second light-shielding portion is connected to the first light-shielding portion; wherein the orthographic projection of the eighth active portion on the substrate and the orthographic projection of the second light-shielding portion on the substrate at least partially overlap.

[0011] In an exemplary embodiment of the present disclosure, the orthographic projection of the eighth active portion on the substrate extends along a first direction, and the size of the orthographic projection of the eighth active portion on the substrate in the first direction is larger than the size of the orthographic projection of the eighth active portion on the substrate in the second direction; the orthographic projection of the second light-shielding portion on the substrate extends along the first direction, and the size of the orthographic projection of the second light-shielding portion on the substrate in the first direction is larger than the size of the orthographic projection of the second light-shielding portion on the substrate in the second direction; the first direction and the second direction intersect.

[0012] In an exemplary embodiment of the present disclosure, the light-shielding layer further includes: a third light-shielding portion, the orthographic projection of the third light-shielding portion on the base substrate extends along the second direction, and the third light-shielding portion is connected between the first light-shielding portion and the second light-shielding portion; the second light-shielding portion includes a first sub-light-shielding portion and a second sub-light-shielding portion, and in the first direction, the orthographic projections of the first sub-light-shielding portion and the second sub-light-shielding portion on the base substrate are located on both sides of the orthographic projection of the third light-shielding portion on the base substrate; the orthographic projection of the first sub-light-shielding portion on the base substrate and the orthographic projection of the eighth active portion on the base substrate at least partially overlap, and the orthographic projection of the second sub-light-shielding portion on the base substrate and the orthographic projection of the eighth active portion on the base substrate at least partially overlap. overlap; the first active layer also includes: a ninth active portion, the orthographic projection of the ninth active portion on the base substrate extends along the second direction, and the ninth active portion is connected between the eighth active portion and the seventh active portion; the eighth active portion includes a first sub-active portion and a second sub-active portion, and in the first direction, the orthographic projections of the first sub-active portion and the second sub-active portion on the base substrate are located on both sides of the orthographic projection of the ninth active portion on the base substrate; the orthographic projection of the first sub-active portion on the base substrate and the orthographic projection of the second light-shielding portion on the base substrate at least partially overlap, and the orthographic projection of the second sub-active portion on the base substrate and the orthographic projection of the second light-shielding portion on the base substrate at least partially overlap.

[0013] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of repeating units, and the plurality of repeating units are arrayed in a first direction and a second direction, and the first direction and the second direction intersect; the repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are arranged in a mirror-symmetrical manner; the first light-shielding layer also includes: a fourth light-shielding portion, the fourth light-shielding portion and the repeating unit are arranged correspondingly, the fourth light-shielding portion is connected to the two second light-shielding portions in the repeating unit corresponding thereto, and the fourth light-shielding portion is connected to an end of the second light-shielding portion away from the first light-shielding portion, and the first opening is formed on the fourth light-shielding portion.

[0014] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a second transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor; the multi-layer functional layer also includes: a first conductive layer and a fourth conductive layer, the first conductive layer is located between the first active layer and the pixel defining layer, the first conductive layer includes a first conductive portion, the orthographic projection of the first conductive portion on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form the gate of the driving transistor; the fourth conductive layer is located between the first conductive layer and the pixel defining layer, the fourth conductive layer includes a first bridge portion and a second bridge portion; wherein the first bridge portion is connected to the first electrode of the second transistor, and the first bridge portion is connected to the first conductive portion through a via, the second bridge portion is connected to the eighth active portion through a via, and the size of the orthographic projection of the second bridge portion on the base substrate in the first direction is larger than the size of the orthographic projection of the second bridge portion on the base substrate in the second direction.

[0015] In an exemplary embodiment of the present disclosure, an area of ​​an orthographic projection of the first opening on the base substrate is smaller than an area of ​​an orthographic projection of the first light shielding portion on the base substrate.

[0016] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a second transistor, wherein the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor; the multi-layer functional layer further includes: a first conductive layer and a fourth conductive layer, the first conductive layer is located between the first active layer and the pixel defining layer, the first conductive layer includes a first conductive portion, the orthographic projection of the first conductive portion on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form the gate of the driving transistor; the fourth conductive layer is located between the first conductive layer and the pixel defining layer, the fourth conductive layer includes a first bridging portion and the first initial signal line, the orthographic projection of the first initial signal line on the base substrate extends along a first direction; the first bridging portion is connected to the first electrode of the second transistor, and the first bridging portion is connected to the first conductive portion through a via.

[0017] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to a first power line; the multi-layer functional layer also includes: a first conductive layer, a second conductive layer, a fourth conductive layer, and a fifth conductive layer, the first conductive layer is located between the first active layer and the pixel defining layer, the first conductive layer includes a first conductive portion, the orthographic projection of the first conductive portion on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form the gate of the driving transistor and the first electrode of the capacitor; the second conductive layer is located between the first conductive layer and the pixel defining layer, the second conductive layer includes a second conductive portion and a first connecting portion, the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate at least partially overlap, and the second conductive portion is used to form a second electrode of the capacitor The first connecting portion is connected between two second conductive portions in the same repeating unit; the fourth conductive layer is located between the second conductive layer and the pixel defining layer, the fourth conductive layer includes a first power connection line, the positive projection of the first power connection line on the base substrate extends along the first direction and the first power connection line is connected to the first connecting portion through a via; the fifth conductive layer is located on the side of the fourth conductive layer away from the base substrate, the fifth conductive layer includes the first power line, in two adjacent repeating units in the first direction, two adjacent first power lines are connected, and the connected two first power lines are connected to the first power connection line through a via.

[0018] In an exemplary embodiment of the present disclosure, the pixel defining layer is black, and a second opening is further formed on the pixel defining layer, the orthographic projection of the second opening on the substrate is located in the light-transmitting area; the orthographic projection of the second opening on the substrate coincides with the orthographic projection of the first opening on the substrate; or, the orthographic projection area of ​​the second opening on the substrate is larger than the orthographic projection area of ​​the first opening on the substrate, and the orthographic projection of the second opening on the substrate covers the orthographic projection of the first opening on the substrate; or, the orthographic projection area of ​​the first opening on the substrate is larger than the orthographic projection area of ​​the second opening on the substrate, and the orthographic projection of the first opening on the substrate covers the orthographic projection of the second opening on the substrate.

[0019] In an exemplary embodiment of the present disclosure, the display panel includes a display area, the display area includes a light signal collection area, and at least the light shielding layer in the light signal collection area is provided with the first opening.

[0020] In an exemplary embodiment of the present disclosure, the display area also includes a normal display area located outside the optical signal collection area; the orthographic projection of the light-shielding layer located in the optical signal collection area on the base substrate and the orthographic projection of the light-shielding layer located in the normal display area on the base substrate have different pattern shapes.

[0021] In an exemplary embodiment of the present disclosure, the display area also includes a normal display area outside the optical signal collection area, and the light-shielding layer in the normal display area is also provided with the first opening; the orthographic projection of the light-shielding layer located in the optical signal collection area on the base substrate and the orthographic projection of the light-shielding layer located in the normal display area on the base substrate have the same pattern shape.

[0022] In an exemplary embodiment of the present disclosure, the light shielding layer located in the optical signal collection area is provided on the entire surface except for the first opening.

[0023] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a plurality of switching transistors; the first active layer further includes: a plurality of active portions, the active portions being used to form channel regions of the switching transistors; wherein a plurality of first openings are further formed on the light-shielding layer located in the optical signal acquisition area, the first openings and the active portions being arranged correspondingly, and the orthographic projection of the first opening on the substrate covers the orthographic projection of the corresponding active portion on the substrate.

[0024] In an exemplary embodiment of the present disclosure, the light-shielding layer located in the normal display area further includes: a plurality of second connecting portions and a plurality of third connecting portions, wherein the orthographic projections of the second connecting portions on the base substrate extend along a first direction and are connected between the first light-shielding portions adjacent to each other in the first direction; the orthographic projections of the third connecting portions on the base substrate extend along a second direction and are connected between the first light-shielding portions adjacent to each other in the second direction, and the first direction and the second direction intersect.

[0025] In an exemplary embodiment of the present disclosure, the display panel further includes a display area, which includes a fan-out area and an optical signal collection area; the display panel further includes: a plurality of data lines, a plurality of first data fan-out lines, and a plurality of second data fan-out lines, wherein the plurality of data lines are located in the display area, and the orthographic projections of the data lines on the substrate are spaced apart along a first direction and extend along a second direction, and the first direction and the second direction intersect; a plurality of first data fan-out lines are located in the fan-out area, and the orthographic projections of the first data fan-out lines on the substrate are spaced apart along the second direction and extend along the first direction, the first data fan-out lines are arranged correspondingly to the data lines, and the first data fan-out lines are connected to the corresponding data lines; a plurality of second data fan-out lines are located in the fan-out area, and the orthographic projections of the second data fan-out lines on the substrate are spaced apart along the first direction and extend along the second direction, the second data fan-out lines are arranged correspondingly to the first data fan-out lines, and the second data fan-out lines are connected to the corresponding first data fan-out lines; and the first data fan-out lines are located in the light shielding layer.

[0026] In an exemplary embodiment of the present disclosure, the multilayer functional layer further includes: a fifth conductive layer, the fifth conductive layer is located between the base substrate and the pixel defining layer, the fifth conductive layer includes the data line; the light shielding layer is located between the fifth conductive layer and the pixel defining layer.

[0027] In an exemplary embodiment of the present disclosure, the display area also includes other display areas located outside the fan-out area and the optical signal acquisition area; the display panel also includes: multiple first signal lines, and the multiple first signal lines are located in a conductive layer outside the light-shielding layer; the light-shielding layer located in the other display areas includes multiple second signal lines, and the orthographic projection of the first signal line on the base substrate and the orthographic projection of the second signal line on the base substrate intersect, and the second signal line is connected to the first signal line intersecting with it through a via.

[0028] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit, which includes a driving transistor, a first transistor, a fifth transistor, and a seventh transistor; the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the fifth transistor is connected to the first power line, the second electrode of the fifth transistor is connected to the first electrode of the driving transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; the multiple first signal lines include one or more of the first initial signal line, the second initial signal line, and the first power line.

[0029] In an exemplary embodiment of the present disclosure, the display area also includes other display areas located outside the fan-out area and the optical signal acquisition area; the display panel also includes: a common electrode layer, the common electrode layer is located on the side of the pixel defining layer away from the base substrate, and the common electrode layer is used to form the second electrode of the light-emitting unit; the light-shielding layer located in the other display areas includes a plurality of second power lines, and the second power lines are connected to the common electrode layer.

[0030] In an exemplary embodiment of the present disclosure, the orthographic projections of some of the second power lines on the base substrate extend along the first direction, and the orthographic projections of some of the second power lines on the base substrate extend along the second direction, and the second power lines with different extension directions intersect.

[0031] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit, which is used to drive the light-emitting unit to emit light. The pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor. The first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor; the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the fifth transistor is connected to the first power line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the first power line; the first transistor and the second transistor are N-type transistors, and the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.

[0032] In an exemplary embodiment of the present disclosure, the multilayer functional layer includes: a first active layer, a first conductive layer, a second active layer, and a third conductive layer. The first active layer is located between the base substrate and the pixel defining layer, and the first active layer includes: a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion; wherein the third active portion is used to form the channel region of the driving transistor, the fourth active portion is used to form the channel region of the fourth transistor, the fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor; the first conductive layer is located between the first active layer and the pixel defining layer, and the first conductive layer includes: a second reset signal line, a second gate line, an enable signal line, and a first conductive portion, wherein the orthographic projections of the second reset signal line, the second gate line, and the enable signal line on the base substrate extend along a first direction; wherein the first conductive portion is used to form the gate of the driving transistor and the first electrode of the capacitor, and the second Part of the structure of the gate line is used to form the gate of the fourth transistor, part of the structure of the second reset signal line is used to form the gate of the seventh transistor, and part of the structure of the enable signal line is used to form the gates of the fifth transistor and the sixth transistor, respectively; the second active layer is located between the first conductive layer and the pixel defining layer, the second active layer includes a first active portion and a second active portion, the first active portion is used to form the channel region of the first transistor, and the second active portion is used to form the channel region of the second transistor; the third conductive layer is located between the second active layer and the pixel defining layer, the third conductive layer includes: the first gate line and the first reset signal line, the orthographic projections of the first gate line and the first reset signal line on the substrate extend along the first direction; part of the structure of the first gate line is used to form the top gate of the second transistor, and part of the structure of the first reset signal line is used to form the top gate of the first transistor.

[0033] In an exemplary embodiment of the present disclosure, in the same pixel driving circuit, the first reset signal line, the second gate line, the first gate line, the first conductive portion, the enable signal line, and the second reset signal line are sequentially distributed in the second direction as their orthographic projections on the substrate, and the first direction and the second direction intersect; the second gate line in the pixel driving circuit of this row is multiplexed as the second reset signal line in the pixel driving circuit of the previous row.

[0034] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit, which is used to drive the light-emitting unit to emit light; the multi-layer functional layer also includes: an electrode layer, the electrode layer includes a plurality of electrode portions, the electrode portion is used to form a first electrode of the light-emitting unit, and the plurality of electrode portions include a first electrode portion, a second electrode portion, and a third electrode portion; among the plurality of electrode portions connected to the pixel driving circuit in the same row, the second electrode portion, the first electrode portion, the third electrode portion, and the first electrode portion are alternately distributed in sequence in the row direction; in two adjacent columns of pixel driving circuits, a plurality of second electrode portions and a plurality of third electrode portions are connected to the pixel driving circuit in the same column, and the second electrode portions and the third electrode portions connected to the pixel driving circuit in the same column are alternately distributed in sequence in the column direction, a plurality of first electrode portions are connected to the pixel driving circuit in another column, and the first electrode portions connected to the pixel driving circuit in the same column are spaced apart in the column direction.

[0035] In an exemplary embodiment of the present disclosure, the first opening is used to image the optical signal aperture on one side of the display panel onto the other side of the display panel.

[0036] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes: a base substrate, a light-shielding layer, a light-shielding layer, the light-shielding layer is located on one side of the base substrate, and the light-shielding layer has a light-shielding function; a plurality of functional layers are located on one side of the base substrate; wherein a first opening is formed on the light-shielding layer, the orthographic projection of the first opening on the base substrate and the orthographic projection of the light-shielding structure in the functional layer on the base substrate do not overlap, and the orthographic projection of the light-shielding layer on the base substrate and the orthographic projection of the light-shielding structure in at least one layer of the functional layer on the base substrate overlap.

[0037] In an exemplary embodiment of the present disclosure, the display panel also includes a light-emitting unit and a pixel driving circuit for driving the light-emitting unit, the pixel driving circuit includes a driving transistor; the multi-layer functional layer includes: a first active layer, the first active layer includes a third active portion, the third active portion is used to form a channel region of the driving transistor; the light-shielding layer is located between the first active layer and the base substrate, the light-shielding layer includes a first light-shielding portion, the orthographic projection of the first light-shielding portion on the base substrate covers the orthographic projection of the third active portion on the base substrate. The pixel driving circuit also includes a first transistor and a fourth transistor, wherein the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the fourth transistor is connected to the data line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor; the display panel also includes: a first reset signal line and a second gate line, the orthographic projection of the first reset signal line on the substrate extends along the first direction, and a partial structure of the first reset signal line is used to form the top gate of the first transistor; the orthographic projection of the second gate line on the substrate extends along the first direction, and a partial structure of the second gate line is used to form the gate of the fourth transistor; wherein the orthographic projection of the first opening on the substrate is located between the orthographic projections of the first reset signal line and the second gate line on the substrate in the same pixel driving circuit.

[0038] In an exemplary embodiment of the present disclosure, the display panel further includes a display area, which includes a fan-out area and an optical signal collection area; the display panel further includes: a plurality of data lines, a plurality of first data fan-out lines, and a plurality of second data fan-out lines, wherein the plurality of data lines are located in the display area, and the orthographic projections of the data lines on the substrate are spaced apart along a first direction and extend along a second direction, and the first direction and the second direction intersect; a plurality of first data fan-out lines are located in the fan-out area, and the orthographic projections of the first data fan-out lines on the substrate are spaced apart along the second direction and extend along the first direction, the first data fan-out lines are arranged correspondingly to the data lines, and the first data fan-out lines are connected to the corresponding data lines; a plurality of second data fan-out lines are located in the fan-out area, and the orthographic projections of the second data fan-out lines on the substrate are spaced apart along the first direction and extend along the second direction, the second data fan-out lines are arranged correspondingly to the first data fan-out lines, and the second data fan-out lines are connected to the corresponding first data fan-out lines; and the first data fan-out lines are located in the light shielding layer.

[0039] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0042] FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art;

[0043] FIG2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1 ;

[0044] FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0045] FIG4 is a structural diagram of the light shielding layer in FIG3 ;

[0046] FIG5 is a structural diagram of the first active layer in FIG3;

[0047] FIG6 is a structural diagram of the first conductive layer in FIG3 ;

[0048] FIG7 is a structural diagram of the second conductive layer in FIG3 ;

[0049] FIG8 is a structural diagram of the second active layer in FIG3;

[0050] FIG9 is a structural diagram of the third conductive layer in FIG3 ;

[0051] FIG10 is a structural diagram of the fourth conductive layer in FIG3;

[0052] FIG11 is a structural diagram of the fifth conductive layer in FIG3 ;

[0053] FIG12 is a structural diagram of the electrode layer and the pixel definition layer in FIG3;

[0054] FIG13 is a structural diagram of the pixel definition layer in FIG3 ;

[0055] FIG14 is a structural diagram of the light shielding layer and the first active layer in FIG3;

[0056] FIG15 is a structural layout diagram of the light shielding layer, the first active layer, and the first conductive layer in FIG3;

[0057] FIG16 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3;

[0058] FIG17 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ;

[0059] FIG18 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ;

[0060] FIG19 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ;

[0061] FIG20 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 ;

[0062] FIG21 is a partial cross-sectional view of the display panel shown in FIG3 taken along dotted line AA;

[0063] FIG22 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0064] FIG23 is a layout structure of the light shielding layer in the optical signal acquisition area;

[0065] FIG24 is a layout structure of the light shielding layer in the normal display area;

[0066] FIG25 is another layout structure of the light shielding layer in the optical signal collection area;

[0067] FIG26 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0068] FIG27 shows the layout structure of the light shielding layer in other display areas of the display panel shown in FIG26 . DETAILED DESCRIPTION

[0069] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0070] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0071] As shown in Figure 1, a circuit structure diagram of a pixel driving circuit in related art is shown. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the first electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the second electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the node N, the second electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to the node N, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting unit (OLED) to drive the light-emitting unit (OLED) to emit light. The light-emitting unit (OLED) can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal (VSS). The first transistor T1 and the second transistor T2 can be N-type transistors, for example, N-type metal oxide transistors (NMOTs). N-type transistors have low leakage current, thereby reducing leakage current at node N through the first transistor T1 and the second transistor T2 during the light-emitting phase. Meanwhile, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, P-type low-temperature polysilicon transistors (LTPS). P-type LTPS transistors have high carrier mobility, thereby facilitating the realization of a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals, depending on actual conditions.

[0072] As shown in Figure 2, it is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 1. Among them, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, and EM represents the timing of the enable signal terminal EM. The driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. During the compensation phase t2, the first gate drive signal terminal G1 outputs a high-level signal, the second gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. During the second reset phase t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. During the light-emitting phase t4, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.

[0073] The output current formula of the driving transistor is as follows:

[0074] I=(μWCox / 2L)(Vgs-Vth) 2

[0075] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor.

[0076] According to the above formula for the output current of the driving transistor, the gate voltage Vdata+Vth and the source voltage Vdd of the driving transistor in the pixel driving circuit of the present invention are substituted into the above formula to obtain: the output current of the driving transistor in the pixel driving circuit of the present invention is I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0077] This exemplary embodiment provides a display panel, which may include a base substrate, a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, an electrode layer, and a pixel defining layer stacked in sequence, wherein an insulating layer may be provided between adjacent conductive layers.

[0078] As shown in Figures 3-20, Figure 3 is a structural layout of an exemplary embodiment of the display panel disclosed in the present invention, Figure 4 is a structural layout of the light-shielding layer in Figure 3, Figure 5 is a structural layout of the first active layer in Figure 3, Figure 6 is a structural layout of the first conductive layer in Figure 3, Figure 7 is a structural layout of the second conductive layer in Figure 3, Figure 8 is a structural layout of the second active layer in Figure 3, Figure 9 is a structural layout of the third conductive layer in Figure 3, Figure 10 is a structural layout of the fourth conductive layer in Figure 3, Figure 11 is a structural layout of the fifth conductive layer in Figure 3, Figure 12 is a structural layout of the electrode layer and the pixel defining layer in Figure 3, Figure 13 is a structural layout of the pixel defining layer in Figure 3, Figure 14 is a structural layout of the light-shielding layer and the first active layer in Figure 3, and Figure 15 is a structural layout of the light-shielding layer and the first FIG16 is a structural layout of the light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3 ; FIG17 is a structural layout of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ; FIG18 is a structural layout of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ; FIG19 is a structural layout of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ; FIG20 is a structural layout of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 . The display panel may include multiple pixel driving circuits shown in FIG1 . As shown in FIG20 , the plurality of pixel driving circuits may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently arranged in a first direction X. The first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in mirror symmetry. The first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may form a repeating unit, and the display panel may include a plurality of repeating units arranged in an array in the first direction X and the second direction Y. The first direction X and the second direction Y may intersect. For example, the first direction may be a row direction, and the second direction may be a column direction.

[0079] As shown in Figures 3, 4 and 14, the shading layer may include multiple first shading portions 71, which are distributed in an array in the first direction X and the second direction Y, and the adjacent first shading portions 71 in the first direction X are connected, and the adjacent first shading portions 71 in the second direction Y are connected.

[0080] As shown in Figures 3, 5, and 15, the first active layer may include a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, a seventh active portion 67, an eighth active portion 68, a ninth active portion 69, a tenth active portion 610, an eleventh active portion 611, a twelfth active portion 612, and a thirteenth active portion 613. Among them, the third active portion 63 can be used to form the channel region of the driving transistor T3; the fourth active portion 64 can be used to form the channel region of the fourth transistor T4; the fifth active portion 65 can be used to form the channel region of the fifth transistor T5; the sixth active portion 66 can be used to form the channel region of the sixth transistor T6; the seventh active portion 67 can be used to form the channel region of the seventh transistor T7; the eighth active portion 68 is connected between the sixth active portion 66 and the seventh active portion 67, and the orthographic projection of the eighth active portion 68 on the substrate extends along the first direction X, and the size of the orthographic projection of the eighth active portion 68 on the substrate in the first direction X is larger than the size of the orthographic projection of the eighth active portion 68 on the substrate The size of the orthogonal projection on the base substrate in the second direction Y is shown in FIG. The ninth active portion 69 is connected between the eighth active portion 68 and the seventh active portion 67, and the orthogonal projection of the ninth active portion 69 on the base substrate extends along the second direction Y. The tenth active portion 610 is connected to the end of the fourth active portion 64 away from the third active portion 63. The eleventh active portion 611 is connected to the end of the fifth active portion 65 away from the third active portion 63. In the same repeating unit, two eleventh active portions 611 can be connected. The twelfth active portion 612 is connected to the end of the seventh active portion 67 away from the sixth active portion 66. The thirteenth active portion 613 is connected between the third active portion 63 and the sixth active portion 66. The first active layer can be formed of polysilicon material. Accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polysilicon thin film transistors.

[0081] As shown in Figures 14 and 15 , the orthographic projection of the first light shielding portion 71 on the substrate covers the orthographic projection of the third active portion 63 on the substrate. The first light shielding portion 71 can shield the third active portion 63 to reduce the impact of light on the characteristics of the driving transistor T3. As shown in Figure 4 , the light shielding layer can also include a second light shielding portion 72 and a third light shielding portion 73. The orthographic projection of the third light shielding portion 73 on the substrate extends along the second direction Y, and the third light shielding portion 73 is connected between the first light shielding portion 71 and the second light shielding portion 72. The orthographic projection of the second light shielding portion 72 on the substrate at least partially overlaps with the orthographic projection of the eighth active portion 68 on the substrate. The second light shielding portion 72 and the eighth active portion 68 can form a parasitic capacitance. That is, this arrangement can increase the parasitic capacitance of the second electrode of the sixth transistor T6 in Figure 1, thereby improving the redness problem of the display panel at low grayscales. In which, the second light-shielding portion 72 may include a first sub-light-shielding portion 721 and a second sub-light-shielding portion 722. In the first direction X, the orthographic projections of the first sub-light-shielding portion 721 and the second sub-light-shielding portion 722 on the base substrate are located on both sides of the orthographic projection of the third light-shielding portion 73 on the base substrate; the orthographic projection of the first sub-light-shielding portion 721 on the base substrate and the orthographic projection of the eighth active portion 68 on the base substrate at least partially overlap, and the orthographic projection of the second sub-light-shielding portion 722 on the base substrate and the orthographic projection of the eighth active portion 68 on the base substrate at least partially overlap. As shown in Figure 5, the eighth active portion 68 may include a first sub-active portion 681 and a second sub-active portion 682. In the first direction X, the orthographic projections of the first sub-active portion 681 and the second sub-active portion 682 on the substrate are located on both sides of the orthographic projection of the ninth active portion 69 on the substrate; the orthographic projection of the first sub-active portion 681 on the substrate and the orthographic projection of the second light-shielding portion 72 on the substrate at least partially overlap, and the orthographic projection of the second sub-active portion 682 on the substrate and the orthographic projection of the second light-shielding portion 72 on the substrate at least partially overlap.

[0082] As shown in Figures 3, 6, and 15, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate overlaps the orthographic projection of the fourth active portion 64 on the substrate, and a portion of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the sixth active portion 66 on the substrate, and a portion of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the second reset signal line Re2 on the substrate can overlap the orthographic projection of the seventh active portion 67 on the substrate. Part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 63 on the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. As shown in Figure 15, the second gate line G2 in the pixel driving circuit of this row can be reused as the second reset signal line Re2 in the pixel driving circuit of the previous row. This arrangement can improve the integration of the pixel driving circuit and reduce the layout area of ​​the pixel driving circuit. The light shielding layer can be connected to a stable power supply terminal. For example, the light shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in Figure 1. The first light shielding portion 71 can stabilize the voltage of the first conductive portion 11, thereby reducing the voltage fluctuation of the gate of the driving transistor T3 during the light-emitting phase. In addition, the display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area covered by the first conductive layer in the first active layer can form the channel region of the transistor, and the area not covered by the first conductive layer forms a conductor structure.

[0083] As shown in Figures 3, 7, and 16, the second conductive layer may include: a third reset signal line 2Re1, a third gate line 2G1, a plurality of second conductive portions 22, and a first connecting portion 21. The third reset signal line 2Re1 may be used to provide the first reset signal terminal in Figure 1, and the third gate line 2G1 may be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the third reset signal line 2Re1 on the base substrate and the orthographic projection of the third gate line 2G1 on the base substrate may both extend along the first direction X. The orthographic projection of the second conductive portion 22 on the base substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate. The second conductive portion 22 may be used to form the second electrode of the capacitor C, and the first connecting portion 21 is connected between two second conductive portions 22 in the same repeating unit. It should be understood that in other exemplary embodiments, in two adjacent repeating units in the first direction X, two adjacent second conductive portions may also be connected.

[0084] As shown in Figures 3, 8, and 17, the second active layer may include multiple sub-active portions 8, including a first active portion 81, a second active portion 82, a fifteenth active portion 815, a sixteenth active portion 816, and a seventeenth active portion 817. The first active portion 81 may be used to form the channel region of the first transistor T1; the second active portion 82 may be used to form the channel region of the second transistor T2; the fifteenth active portion 815 is connected to the end of the first active portion 81 away from the second active portion 82; the sixteenth active portion 816 is connected to the end of the second active portion 82 away from the first active portion 81; and the seventeenth active portion 817 is connected between the first active portion 81 and the second active portion 82. In two adjacent repeating units in the first direction X, adjacent sub-active portions 8 share the same fifteenth active portion 815. The second active layer may be formed of indium gallium zinc oxide. Accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 on the substrate can overlap the orthographic projection of the second active portion 82 on the substrate, and a portion of the structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor. The orthographic projection of the third reset signal line 2Re1 on the substrate can overlap the orthographic projection of the first active portion 81 on the substrate, and a portion of the structure of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1. In other exemplary embodiments, the orthographic projection of the light shielding layer on the substrate can also overlap the orthographic projection of the sub-active portion 8 on the substrate to reduce the impact of light on the characteristics of the first and second transistors.

[0085] As shown in Figures 3, 9, and 18, the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1. The orthographic projection of the first reset signal line 3Re1 on the base substrate and the orthographic projection of the first gate line 3G1 on the base substrate may both extend along the first direction X. The first reset signal line 3Re1 may be used to provide the first reset signal terminal shown in Figure 1. The orthographic projection of the first reset signal line 3Re1 on the base substrate may cover the orthographic projection of the first active portion 81 on the base substrate. Part of the structure of the first reset signal line 3Re1 may be used to form the top gate of the first transistor T1. At the same time, the first reset signal line 3Re1 may be connected to the third reset signal line 2Re1 through a via located in the edge routing area of ​​the display panel. The first gate line 3G1 can be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the first gate line 3G1 on the substrate can cover the orthographic projection of the second active portion 82 on the substrate. Part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the edge routing area of ​​the display panel. As shown in Figures 3, 9, and 18, in the same pixel drive circuit, the orthographic projections of the first reset signal line 3Re1, the second gate line G2, the first gate line 3G1, the first conductive portion 11, the enable signal line EM, and the second reset signal line Re2 on the substrate are sequentially distributed in the second direction Y. The display panel can use the third conductive layer as a mask to perform conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area not covered by the third conductive layer forms a conductor structure.

[0086] As shown in Figures 3, 10, and 19, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a first initial signal line Vinit1, a second initial signal line Vinit2, and a first power connection line 4VDD. The first bridge portion 41 may be connected to the seventeenth active portion 817 and the first conductive portion 11 through vias (black squares in the figure) to connect the first electrode of the second transistor T2 and the gate of the driving transistor T3. An opening 221 may be formed on the second conductive portion 22, and the orthographic projection of the via connected between the first conductive portion 11 and the first bridge portion 41 on the substrate is located on the orthographic projection of the opening 221 on the substrate, so as to insulate the via connected between the first conductive portion 11 and the first bridge portion 41 from the second conductive portion 22. The second bridge portion 42 may be connected to the eighth active portion through a via to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. Among them, the size of the orthographic projection of the second bridge portion 42 on the substrate in the first direction X is greater than the size of the orthographic projection of the second bridge portion 42 on the substrate in the second direction Y. The second bridge portion 42 and signal lines such as the first initial signal line Vinit1 can form lateral parasitic capacitance to further increase the parasitic capacitance of the second electrode of the sixth transistor. The third bridge portion 43 can be connected to the sixteenth active portion 816 and the thirteenth active portion 613 through vias, respectively, to connect the second electrode of the second transistor T2 and the second electrode of the driving transistor T3. The fourth bridge portion 44 can be connected to the tenth active portion 410 through a via to connect the first electrode of the fourth transistor T4. The orthographic projection of the first initial signal line Vinit1 on the substrate extends along the first direction. The first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1. The first initial signal line Vinit1 can be connected to the fifteenth active portion 815 through a via to connect the first electrode of the first transistor T1. The orthographic projection of the second initial signal line Vinit2 on the base substrate can extend along the first direction X. The second initial signal line Vinit2 can be equivalent to the second initial signal terminal in Figure 1. The second initial signal line Vinit2 can be connected to the twelfth active portion 612 via a via to connect to the first electrode of the seventh transistor T7. The orthographic projection of the first power connection line 4VDD on the base substrate can extend along the first direction X. The first power connection line 4VDD can be connected to the first connection portion 21 and the eleventh active portion 611 via vias to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C.

[0087] As shown in Figures 3, 11, and 20, the fifth conductive layer may include a first power line VDD, a data line Da, and a fifth bridge portion 55. The fifth bridge portion 55 may be connected to the second bridge portion 42 via a via, thereby connecting to the second electrode of the sixth transistor. The orthographic projection of the first power line VDD on the substrate may extend along the second direction Y. The first power line VDD is used to provide the first power signal terminal shown in Figure 1. The first power line VDD may include a first extension portion VDD1, a second extension portion VDD2, and a third extension portion VDD3. The second extension portion VDD2 is connected between the first extension portion VDD1 and the third extension portion VDD3. The orthographic projection of the second extension portion VDD2 on the substrate in the first direction X may be larger than the orthographic projection of the first extension portion VDD1 on the substrate in the first direction X. The orthographic projection of the second extension portion VDD2 on the substrate in the first direction X may also be larger than the orthographic projection of the third extension portion VDD3 on the substrate in the first direction X. In two adjacent repeating units in the first direction X, the second extensions VDD2 of two adjacent first power lines VDD are connected, and the connected second extensions VDD2 are connected to the first power connection line 4VDD through one or more vias. The first power lines VDD and the first power connection line 4VDD can form a grid structure, and the power lines of this grid structure can reduce the voltage drop of the power signal thereon. The orthographic projection of the second extension VDD2 on the substrate can cover the orthographic projections of the first active portion 81 and the second active portion 82 on the substrate. The second extension VDD2 can reduce the impact of light on the characteristics of the first transistor and the second transistor. The orthographic projection of the second extension VDD2 on the substrate can also cover the orthographic projection of the first bridge portion 41 on the substrate. The second extension VDD2 can stabilize and shield the first bridge portion 41 to reduce voltage fluctuations on the gate of the driving transistor T3 during the light-emitting phase. As shown in Figure 20, the connected second extension portion VDD2 is connected to the first power connection line 4VDD via a via, and the first power connection line 4VDD can be connected to the first connection portion 21 via a via. This arrangement can reduce the number of vias, thereby saving the space occupied by the vias. The data line Da can be used to provide the data signal terminal shown in Figure 1. The orthographic projection of the data line Da on the substrate can extend along the second direction Y. The data line Da can be connected to the fourth bridge portion 44 via a via, thereby connecting the data signal terminal and the first electrode of the fourth transistor.

[0088] As shown in Figures 3, 12, and 13, the electrode layer includes multiple electrode portions: a first electrode portion G, a second electrode portion B, and a third electrode portion R. Each electrode portion can be connected to the fifth bridge portion 55 via a via, thereby connecting to the second electrode of the sixth transistor. A plurality of pixel openings PH are formed on the pixel defining layer. The pixel openings PH are arranged corresponding to the electrode portions, and the orthographic projections of the pixel openings PH on the substrate coincide with the orthographic projections of the electrode portions on the substrate. The first electrode portion G can be used to form the electrode portion of the green light-emitting unit in the display panel, the second electrode portion B can be used to form the electrode portion of the blue light-emitting unit in the display panel, and the third electrode portion R can be used to form the electrode portion of the red light-emitting unit. Among the multiple electrode portions connected to the same row of pixel driving circuits, the second electrode portion B, the first electrode portion G, the third electrode portion R, and the first electrode portion G are alternately distributed in the row direction X. In two adjacent columns of pixel driving circuits, the multiple second electrode portions B and the multiple third electrode portions R are connected to the same column of pixel driving circuits, and the second electrode portions B and the third electrode portions R connected to the same column of pixel driving circuits are alternately distributed in the column direction Y. The multiple first electrode portions G are connected to the other column of pixel driving circuits, and the first electrode portions G connected to the same column of pixel driving circuits are alternately distributed in the column direction. The minimum distance S1 between the orthogonal projections of two first electrode portions G connected to adjacent pixel driving circuit rows and the same pixel driving circuit column on the substrate in the column direction is greater than the dimension S2 of the orthogonal projection of the third electrode portion R on the substrate in the column direction, and / or the minimum distance S1 between the orthogonal projections of two first electrode portions G connected to adjacent pixel driving circuit rows and the same pixel driving circuit column on the substrate in the column direction is greater than the dimension S3 of the orthogonal projection of the second electrode portion B on the substrate in the column direction.

[0089] As shown in Figure 4, a first opening H1 may also be provided on the light-shielding layer, the substrate may include a light-transmitting area, and the light-shielding structure of all functional layers (including the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, the electrode layer, and the insulating layer between the above layers) between the substrate and the pixel defining layer has an orthographic projection on the substrate substrate outside the light-transmitting area, and the orthographic projection of the first opening H1 on the substrate substrate is located in the light-transmitting area. Based on the principle of pinhole imaging, the optical signal on one side of the display panel can be imaged on the other side of the display panel through the first opening H1, so that the display device using the display panel can realize technologies such as fingerprint recognition and under-screen camera. In addition, the light-shielding layer around the first opening H1 can reduce the influence of stray light formed by the light-shielding structure between the substrate and the pixel defining layer on the pinhole imaging effect. Among them, the light-shielding structure may refer to a structure with a transmittance of less than 50% in the stacking direction of the display panel.

[0090] As shown in FIG4 , the light-shielding layer may further include a fourth light-shielding portion 74, which is disposed corresponding to the repeating unit. The fourth light-shielding portion 74 connects the two second light-shielding portions 72 in the corresponding repeating unit, and is connected to an end of the second light-shielding portion 72 away from the first light-shielding portion 71. The first opening H1 is formed on the fourth light-shielding portion 74. The edge of the fourth light-shielding portion 74 on the side closest to the second light-shielding portion 72 may also form a lateral capacitance with the eighth active portion 68, thereby further increasing the parasitic capacitance of the second electrode of the sixth transistor T6.

[0091] As shown in Figures 3, 4, and 20, the orthographic projection of the first opening H1 on the substrate can be located between the orthographic projections of the first reset signal line 3Re1 and the second gate line G2 in the same pixel driving circuit on the substrate. The orthographic projection of the first opening H1 on the substrate is located between the orthographic projections of two adjacent data lines Da in the same repeating unit on the substrate.

[0092] In this exemplary embodiment, the area of ​​the orthographic projection of the first opening H1 on the substrate may be smaller than the area of ​​the orthographic projection of the first light shielding portion 71 on the substrate. The area of ​​the orthographic projection of the first light shielding portion 71 on the substrate may be 2-5 times the area of ​​the orthographic projection of the first opening H1 on the substrate. For example, the area of ​​the orthographic projection of the first light shielding portion 71 on the substrate may be 2 times, 3 times, 4 times, 5 times, etc., the area of ​​the orthographic projection of the first opening H1 on the substrate.

[0093] It should be understood that in other exemplary embodiments, the pixel driving circuit can also be other structures, and accordingly, the layout structure of the display panel can also be other structures. As long as a first opening is formed on the light-shielding layer, pinhole imaging can be achieved through the first opening located on the light-shielding layer, so that the display device using the display panel can realize fingerprint recognition, under-screen camera and other technologies.

[0094] As shown in Figures 3 and 13, the pixel defining layer PDL can be black, and a second opening H2 can also be formed on the pixel defining layer, and the orthographic projection of the second opening H2 on the base substrate can also be located in the light-transmitting area. The second opening H2 and / or the first opening H1 can form a pinhole required for pinhole imaging. The orthographic projection of the second opening H2 on the base substrate and the orthographic projection of the first opening H1 on the base substrate can overlap; or the orthographic projection area of ​​the second opening H2 on the base substrate is larger than the orthographic projection area of ​​the first opening H1 on the base substrate, and the orthographic projection of the second opening H2 on the base substrate covers the orthographic projection of the first opening H1 on the base substrate; or the orthographic projection area of ​​the first opening H1 on the base substrate is larger than the orthographic projection area of ​​the second opening H2 on the base substrate, and the orthographic projection of the first opening H1 on the base substrate covers the orthographic projection of the second opening H2 on the base substrate.

[0095] In other exemplary embodiments, the display panel may further include a color filter layer located on the side of the pixel defining layer facing away from the base substrate, and the black matrix on the color filter layer may be formed with a third imaging hole, and one or more of the first opening, the second opening, and the third imaging hole may form the small hole required for pinhole imaging.

[0096] It should be noted that, as shown in Figures 3, 19, and 20, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. The black squares indicate the locations of the vias, and different vias represented by black squares in different locations can penetrate different insulating layers.

[0097] As shown in Figure 21, a partial cross-sectional view of the display panel shown in Figure 3 taken along dotted line AA is shown. The display panel may further include a first buffer layer 92, a first insulating layer 93, a second insulating layer 94, a second buffer layer 95, a third insulating layer 96, a dielectric layer 97, a first planar layer 98, and a second planar layer 99. Specifically, the base substrate 91, the light shielding layer, the first buffer layer 92, the first active layer, the first insulating layer 93, the first conductive layer, the second insulating layer 94, the second conductive layer, the second buffer layer 95, the second active layer, the third insulating layer 96, the third conductive layer, the dielectric layer 97, the fourth conductive layer, the first planar layer 98, the fifth conductive layer, the second planar layer 99, the electrode layer, and the pixel definition layer (PDL) are stacked in sequence. The first buffer layer 92 and the second buffer layer 95 may comprise one or more layers of silicon oxide or silicon nitride. The first insulating layer 93, the second insulating layer 94, and the third insulating layer 96 may comprise one or more layers of silicon oxide or silicon nitride. The dielectric layer 97 may comprise a silicon nitride layer. The materials of the first planarization layer 98 and the second planarization layer 99 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding (SOG), and the like. The base substrate 91 may comprise a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer may be an inorganic material. The materials of the first, second, and third conductive layers may be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate. The materials of the fourth and fifth conductive layers may be metal materials, such as molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate, or a titanium / aluminum / titanium laminate. The electrode layer may include an indium tin oxide layer and a silver layer. The square resistance of any one of the first conductive layer, the second conductive layer, and the third conductive layer may be greater than the square resistance of any one of the fourth conductive layer and the fifth conductive layer.

[0098] It should be noted that the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to define different structure names and do not have a specific order or quantity meaning. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending straight or curved along the direction. A transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this exemplary embodiment, the channel region refers to the region where current mainly flows. In this exemplary embodiment, the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. When using transistors with opposite polarity or when the direction of current changes during circuit operation, the functions of "source" and "drain" are sometimes reversed. Therefore, in this exemplary embodiment, "source" and "drain" can be reversed. Furthermore, the gate electrode can also be referred to as a control electrode.

[0099] As shown in Figure 22, it is a schematic diagram of the structure of another exemplary embodiment of the display panel of the present disclosure. The display panel may include a display area AA, and the display area AA may include an optical signal collection area AA1 and a normal display area AA2 outside the optical signal collection area AA1. The optical signal collection area AA1 may be in a circular, rectangular, triangular, polygonal, or other shape. The optical signal located on one side of the display panel can be imaged on the other side of the display panel through the first opening H1 located in the optical signal collection area AA1. The optical signal collection area AA1 can be used as a fingerprint recognition area, an under-screen camera area, etc.

[0100] In this exemplary embodiment, the layout structures in both the optical signal acquisition area AA1 and the normal display area AA2 can be as shown in Figure 3. The light shielding layers in the optical signal acquisition area AA1 and the normal display area AA2 have the same pattern shape, so that different areas of the display panel have the same parasitic capacitance distribution. This arrangement can improve the display uniformity of the display panel.

[0101] In other exemplary embodiments, the orthographic projections of the light shielding layer in the optical signal collection area AA1 and the normal display area AA2 on the substrate may have different pattern shapes. For example, as shown in Figures 23 and 24, Figure 23 shows the layout structure of the light shielding layer in the optical signal collection area, and Figure 24 shows the layout structure of the light shielding layer in the normal display area.

[0102] As shown in Figure 23, the light shielding layer in the optical signal collection area is provided entirely except for the first opening H1. This arrangement ensures that the first opening in the optical signal collection area has a better imaging effect. As shown in Figure 24, the light shielding layer in the normal display area may include: a first light shielding portion 71, a second connecting portion 752, and a third connecting portion 753. The orthographic projection of the second connecting portion 752 on the substrate extends along a first direction X and connects between adjacent first light shielding portions 71 in the first direction X; the orthographic projection of the third connecting portion 753 on the substrate extends along a second direction Y and connects between adjacent first light shielding portions 71 in the second direction Y. In the normal display area, the ratio of the orthographic projection area of ​​the light shielding layer's hollow structure on the substrate to the orthographic projection area of ​​its solid structure on the substrate is K1. In the optical signal collection area, the ratio of the orthographic projection area of ​​the light shielding layer's hollow structure on the substrate to the orthographic projection area of ​​its solid structure on the substrate is K2. K1 may be greater than K2. This setting can effectively improve the problem of electrostatic damage to the device caused by the large area of ​​​​the light shielding layer covering the normal display area.

[0103] As shown in Figure 25, another layout structure of the light shielding layer in the optical signal acquisition area is shown. A plurality of first openings B1 are further formed on the light shielding layer in the optical signal acquisition area. The first openings B1 correspond to the active portions in the display panel for forming the transistor channel region. The orthographic projection of the first openings B1 on the substrate overlaps the orthographic projection of the corresponding active portion on the substrate. The active portion for forming the transistor channel region may include a first active portion 81, a second active portion 82, a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, and a seventh active portion 67. Forming the first openings B1 on the light shielding layer can reduce the parasitic capacitance between the light shielding layer and the transistor channel region, thereby reducing the influence of the parasitic capacitance on the transistor characteristics.

[0104] In other exemplary embodiments, the light shielding layer may also be located at any other position between the base substrate and the pixel defining layer. For example, the light shielding layer may be located at the conductive layer where the fan-out line added in the FIP (Fanout In Panel) technology is located. As shown in FIG26 , it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure, wherein the display panel includes a display area AA, and the display area AA includes a fan-out area AA3, an optical signal acquisition area AA1, and other display areas AA4 located outside the fan-out area AA3 and the optical signal acquisition area AA1. The display panel may include a plurality of data lines Da, a plurality of first data fan-out lines Fa1, and a plurality of second data fan-out lines Fa2. The plurality of data lines Da are located in the display area AA, with their orthographic projections on the substrate spaced apart along a first direction X and extending along a second direction Y. The plurality of first data fan-out lines Fa1 are located in the fan-out area AA3, with their orthographic projections on the substrate spaced apart along a second direction Y and extending along the first direction X. The first data fan-out lines Fa1 are arranged correspondingly to the data lines Da and connected to their corresponding data lines Da. The plurality of second data fan-out lines Fa2 are located in the fan-out area AA3, with their orthographic projections on the substrate spaced apart along the first direction X and extending along the second direction Y. The second data fan-out lines Fa2 are arranged correspondingly to the first data fan-out lines Fa1 and connected to their corresponding first data fan-out lines Fa1. The first data fan-out lines Fa1 may be located in the light shielding layer. The data line Da and the second data fan-out line Fa2 may be located in the fifth conductive layer, and the first data fan-out line Fa1 may be located in the sixth conductive layer added between the fifth conductive layer and the pixel defining layer.

[0105] In the display panel shown in FIG26 , the layout structure of the light shielding layer in the optical signal acquisition area AA1 can be the same as the structure shown in FIG23 or FIG25 . FIG27 shows the layout structure of the light shielding layer in the other display area AA4 of the display panel shown in FIG26 . The light shielding layer located in the other display area AA4 can include multiple second power supply lines VSS. The orthographic projections of some of the second power supply lines VSS on the base substrate can extend along the first direction X, and the orthographic projections of some of the second power supply lines VSS on the base substrate can extend along the second direction Y. The second power supply lines extending in different directions can intersect to form a grid structure. The second power supply lines VSS forming the grid structure can be connected to the common electrode layer through vias, thereby reducing the voltage drop of the signal on the common electrode layer. The common electrode layer is located on the side of the pixel defining layer facing away from the base substrate, and the common electrode layer is used to form the second electrode of the light-emitting unit. In other exemplary embodiments, the second power supply lines in the light shielding layer in the other display area AA4 can also extend in the same direction. In addition, in other exemplary embodiments, the light-shielding layer located in other display areas AA4 may further include other signal lines. For example, the light-shielding layer located in other display areas AA4 may further include a second signal line. The second signal line may intersect with the orthographic projection of the first signal line located on a different conductive layer on the base substrate, and the second signal line may be connected to the intersecting first signal line through a via. The second signal line may form a grid structure with the first signal line to reduce the voltage drop of the signal on the first signal line. The first signal line may include one or more of a first initial signal line, a second initial signal line, and a first power line. It should be noted that the light-shielding layer located in other display areas AA4 may include both a second signal line and a second power line.

[0106] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0107] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0108] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

[0109] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a light emitting unit, and the display panel further includes: a base substrate, the base substrate comprising a light-transmitting area; A light shielding layer is located on one side of the base substrate, and the light shielding layer has a light shielding function; a pixel defining layer, located on a side of the light shielding layer away from the base substrate, wherein a pixel opening is formed on the pixel defining layer, and the light emitting unit is formed in the pixel opening; A multi-layer functional layer is located between the base substrate and the pixel defining layer, and the orthographic projections of the light-shielding structures of all the functional layers between the base substrate and the pixel defining layer on the base substrate are located outside the light-transmitting area; A first opening is formed on the light shielding layer, and an orthographic projection of the first opening on the base substrate is located in the light-transmitting area.

2. The display panel according to claim 1, wherein: The display panel further includes a pixel driving circuit for driving the light emitting unit, wherein the pixel driving circuit includes a driving transistor; The multi-layer functional layers include: a first active layer, the first active layer including a third active portion, the third active portion being used to form a channel region of the driving transistor; The light shielding layer is located between the first active layer and the base substrate. The light shielding layer includes a first light shielding portion. The orthographic projection of the first light shielding portion on the base substrate covers the orthographic projection of the third active portion on the base substrate.

3. The display panel according to claim 2, wherein: The pixel driving circuit further includes a first transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a first reset signal line, wherein an orthographic projection of the first reset signal line on the substrate extends along a first direction, and a portion of the first reset signal line is used to form a top gate of the first transistor; a second gate line, an orthographic projection of the second gate line on the substrate extending along the first direction, and a portion of the second gate line being used to form a gate of the fourth transistor; The orthographic projection of the first opening on the base substrate is located between the orthographic projections of the first reset signal line and the second gate line on the base substrate in the same pixel driving circuit.

4. The display panel according to claim 2, wherein: The display panel includes a plurality of repeating units, wherein the plurality of repeating units are arrayed in a first direction and a second direction, and the first direction and the second direction intersect; The repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are arranged in mirror symmetry.

5. The display panel according to claim 4, wherein: The pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The orthographic projection of the data line on the base substrate extends along the second direction, and the orthographic projection of the first opening on the base substrate is located between the orthographic projections of two adjacent data lines on the base substrate in the same repeating unit. The display panel according to claim 2 , wherein: The pixel driving circuit further includes a sixth transistor and a seventh transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; The first active layer further comprises: a sixth active portion, configured to form a channel region of the sixth transistor; a seventh active portion, configured to form a channel region of the seventh transistor; an eighth active portion connected between the sixth active portion and the seventh active portion; The light-shielding layer further comprises: a second light shielding portion, the second light shielding portion being connected to the first light shielding portion; The orthographic projection of the eighth active portion on the base substrate and the orthographic projection of the second light shielding portion on the base substrate at least partially overlap.

7. The display panel according to claim 6, wherein: The orthographic projection of the eighth active portion on the base substrate extends along a first direction, and a size of the orthographic projection of the eighth active portion on the base substrate in the first direction is greater than a size of the orthographic projection of the eighth active portion on the base substrate in a second direction; The orthographic projection of the second light shielding portion on the base substrate extends along the first direction, and the size of the orthographic projection of the second light shielding portion on the base substrate in the first direction is larger than the size of the orthographic projection of the second light shielding portion on the base substrate in the second direction; The first direction and the second direction intersect.

8. The display panel according to claim 6, wherein: The display panel includes a plurality of repeating units, wherein the plurality of repeating units are arrayed in a first direction and a second direction, and the first direction and the second direction intersect; The repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are arranged in mirror symmetry; The first light-shielding layer further includes: A fourth light-shielding portion, wherein the fourth light-shielding portion and the repeating unit are arranged correspondingly, the fourth light-shielding portion is connected to two second light-shielding portions in the repeating unit corresponding thereto, and the fourth light-shielding portion is connected to one end of the second light-shielding portion away from the first light-shielding portion, and the first opening is formed on the fourth light-shielding portion.

9. The display panel according to claim 6, wherein: The pixel driving circuit further includes a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; The multi-layer functional layer also includes: a first conductive layer, located between the first active layer and the pixel defining layer, the first conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, the first conductive portion being used to form a gate of the driving transistor; a fourth conductive layer, located between the first conductive layer and the pixel defining layer, the fourth conductive layer comprising a first bridge portion and a second bridge portion; The first bridge portion is connected to the first electrode of the second transistor, and the first bridge portion is connected to the first conductive portion through a via, the second bridge portion is connected to the eighth active portion through a via, and the size of the orthographic projection of the second bridge portion on the base substrate in the first direction is larger than the size of the orthographic projection of the second bridge portion on the base substrate in the second direction.

10. The display panel according to claim 2, wherein: An area of ​​an orthographic projection of the first opening on the base substrate is smaller than an area of ​​an orthographic projection of the first light shielding portion on the base substrate.

11. The display panel according to claim 2, wherein: The pixel driving circuit further includes a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate electrode of the driving transistor, a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The multi-layer functional layer also includes: a first conductive layer, located between the first active layer and the pixel defining layer, the first conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, the first conductive portion being used to form a gate of the driving transistor; a fourth conductive layer, located between the first conductive layer and the pixel defining layer, the fourth conductive layer comprising a first bridge portion and the first initial signal line, wherein an orthographic projection of the first initial signal line on the base substrate extends along a first direction; The first bridge portion is connected to the first electrode of the second transistor, and the first bridge portion is connected to the first conductive portion through a via.

12. The display panel according to claim 4, wherein: The pixel driving circuit further comprises a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the first power line; The multi-layer functional layer also includes: a first conductive layer, located between the first active layer and the pixel defining layer, the first conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, the first conductive portion being used to form a gate of the driving transistor and a first electrode of the capacitor; a second conductive layer, located between the first conductive layer and the pixel defining layer, the second conductive layer comprising a second conductive portion and a first connecting portion, the orthographic projection of the second conductive portion on the base substrate at least partially overlapping the orthographic projection of the first conductive portion on the base substrate, the second conductive portion being used to form a second electrode of the capacitor, and the first connecting portion being connected between two second conductive portions in the same repeating unit; a fourth conductive layer, located between the second conductive layer and the pixel defining layer, the fourth conductive layer comprising a first power connection line, an orthographic projection of the first power connection line on the base substrate extending along a first direction and the first power connection line connected to the first connection portion through a via; A fifth conductive layer is located on the side of the fourth conductive layer away from the base substrate, and the fifth conductive layer includes the first power line. In two adjacent repeating units in the first direction, two adjacent first power lines are connected, and the two connected first power lines are connected to the first power connection line through a via.

13. The display panel according to claim 1, wherein: The pixel defining layer is black, and a second opening is formed on the pixel defining layer, wherein the orthographic projection of the second opening on the base substrate is located in the light-transmitting area; The orthographic projection of the second opening on the base substrate coincides with the orthographic projection of the first opening on the base substrate; Alternatively, the orthographic projection area of ​​the second opening on the base substrate is larger than the orthographic projection area of ​​the first opening on the base substrate, and the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first opening on the base substrate; Alternatively, the orthographic projection area of ​​the first opening on the base substrate is larger than the orthographic projection area of ​​the second opening on the base substrate, and the orthographic projection of the first opening on the base substrate covers the orthographic projection of the second opening on the base substrate.

14. The display panel according to claim 2, wherein: The display panel includes a display area, the display area includes a light signal collection area, and the light shielding layer in at least the light signal collection area is provided with the first opening.

15. The display panel according to claim 14, wherein: The display area also includes a normal display area located outside the optical signal collection area; The orthographic projection of the light shielding layer located in the optical signal collection area on the base substrate and the orthographic projection of the light shielding layer located in the normal display area on the base substrate have different pattern shapes.

16. The display panel according to claim 14, wherein: The display area further includes a normal display area outside the optical signal collection area, and the light shielding layer in the normal display area is also provided with the first opening; The orthographic projection of the light shielding layer located in the optical signal collection area on the base substrate and the orthographic projection of the light shielding layer located in the normal display area on the base substrate have the same pattern shape.

17. The display panel according to claim 15, wherein: The light shielding layer located in the optical signal collection area is provided on the entire surface except for the first opening.

18. The display panel according to claim 17, wherein: The pixel driving circuit further includes a plurality of switching transistors; The first active layer further comprises: a plurality of active portions, wherein the active portions are used to form a channel region of the switch transistor; Among them, a plurality of first openings are also formed on the light shielding layer located in the optical signal collection area, and the first openings are arranged corresponding to the active parts, and the orthographic projections of the first openings on the base substrate cover the orthographic projections of the corresponding active parts on the base substrate.

19. The display panel according to claim 15, wherein: The light shielding layer located in the normal display area further includes: a plurality of second connecting portions, the orthographic projections of which on the base substrate extend along a first direction and are connected between adjacent first light shielding portions in the first direction; A plurality of third connecting portions have orthographic projections on the base substrate extending along a second direction and connected between adjacent first light shielding portions in the second direction, and the first direction and the second direction intersect.

20. The display panel according to claim 1, wherein The display panel further includes a display area, and the display area includes a fan-out area and an optical signal collection area; The display panel further includes: a plurality of data lines located in the display area, wherein orthographic projections of the data lines on the base substrate are spaced apart along a first direction and extend along a second direction, wherein the first direction and the second direction intersect; a plurality of first data fan-out lines located in the fan-out area, wherein the orthographic projections of the first data fan-out lines on the substrate are spaced apart along the second direction and extend along the first direction, the first data fan-out lines are arranged corresponding to the data lines, and the first data fan-out lines are connected to the corresponding data lines; a plurality of second data fan-out lines located in the fan-out area, wherein the orthographic projections of the second data fan-out lines on the substrate are spaced apart along the first direction and extend along the second direction, the second data fan-out lines being arranged corresponding to the first data fan-out lines, and the second data fan-out lines being connected to the corresponding first data fan-out lines; The first data fan-out line is located in the light shielding layer.

21. The display panel according to claim 20, wherein: The multi-layer functional layer also includes: a fifth conductive layer, located between the base substrate and the pixel defining layer, wherein the fifth conductive layer includes the data line; The light shielding layer is located between the fifth conductive layer and the pixel defining layer.

22. The display panel according to claim 20, wherein: The display area also includes other display areas outside the fan-out area and the optical signal acquisition area; The display panel further includes: a plurality of first signal lines located in the conductive layer outside the light shielding layer; The light shielding layer located in the other display area includes multiple second signal lines, the orthographic projection of the first signal line on the base substrate intersects with the orthographic projection of the second signal line on the base substrate, and the second signal line is connected to the first signal line intersecting with it through a via.

23. The display panel according to claim 1, wherein: The first opening is used to image the optical signal aperture on one side of the display panel onto the other side of the display panel.

24. A display panel, wherein: The display panel includes: substrate; A light shielding layer is located on one side of the base substrate, and the light shielding layer has a light shielding function; A multi-layer functional layer is located on one side of the substrate; In which, a first opening is formed on the light-shielding layer, the orthographic projection of the first opening on the base substrate and the orthographic projection of the light-shielding structure in the functional layer on the base substrate do not overlap, and the orthographic projection of the light-shielding layer on the base substrate and the orthographic projection of the light-shielding structure in at least one layer of the functional layer on the base substrate overlap.

25. The display panel according to claim 24, wherein: The display panel further includes a light emitting unit and a pixel driving circuit for driving the light emitting unit, wherein the pixel driving circuit includes a driving transistor; The multi-layer functional layers include: a first active layer, the first active layer including a third active portion, the third active portion being used to form a channel region of the driving transistor; The light shielding layer is located between the first active layer and the base substrate, and the light shielding layer includes a first light shielding portion, wherein the orthographic projection of the first light shielding portion on the base substrate covers the orthographic projection of the third active portion on the base substrate; The pixel driving circuit further includes a first transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a first reset signal line, wherein an orthographic projection of the first reset signal line on the substrate extends along a first direction, and a portion of the first reset signal line is used to form a top gate of the first transistor; a second gate line, an orthographic projection of the second gate line on the substrate extending along the first direction, and a portion of the second gate line being used to form a gate of the fourth transistor; The orthographic projection of the first opening on the base substrate is located between the orthographic projections of the first reset signal line and the second gate line on the base substrate in the same pixel driving circuit.

26. The display panel according to claim 24, wherein: The display panel further includes a display area, and the display area includes a fan-out area and an optical signal collection area; The display panel further includes: a plurality of data lines located in the display area, wherein orthographic projections of the data lines on the base substrate are spaced apart along a first direction and extend along a second direction, wherein the first direction and the second direction intersect; a plurality of first data fan-out lines located in the fan-out area, wherein the orthographic projections of the first data fan-out lines on the substrate are spaced apart along the second direction and extend along the first direction, the first data fan-out lines are arranged corresponding to the data lines, and the first data fan-out lines are connected to the corresponding data lines; a plurality of second data fan-out lines located in the fan-out area, wherein the orthographic projections of the second data fan-out lines on the substrate are spaced apart along the first direction and extend along the second direction, the second data fan-out lines being arranged corresponding to the first data fan-out lines, and the second data fan-out lines being connected to the corresponding first data fan-out lines; The first data fan-out line is located in the light shielding layer.

27. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 26.