Drive method and display devic

Abstract

A drive method, relating to the technical field of display. The drive method is used for driving a pixel array, and comprises an operation (S210) to an operation (S220): in the operation (S210), according to a valid time difference between valid signals of a data signal (Vdata) and of a gate drive signal (Gate), setting the timing sequence of the gate drive signal (Gate); and in the operation (S220), driving a pixel array by means of the gate drive signal (Gate). Further provided is a display device (600).

Description

Driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving method and a display device. Background Art

[0002] A display device (such as an OLED display) may include a display panel, a gate driver, a data driver, and a timing controller. The display panel includes a pixel array consisting of multiple pixels. The gate driver generates a gate drive signal that is supplied to the pixel rows, and the data driver provides data voltages to the pixels.

[0003] However, changes in the data signal may cause fluctuations in the power supply voltage, thereby causing crosstalk when the display panel displays images, thereby affecting the display effect of the display panel.

[0004] Summary of the Invention

[0005] The present disclosure provides a driving method and a display device.

[0006] According to a first aspect, the present disclosure provides a driving method, which sets a timing of a gate driving signal according to an effective time difference between a data signal and an effective signal of the gate driving signal; and drives a pixel array through the gate driving signal.

[0007] For example, the effective time difference includes a first time difference between the application moment of the data signal and the start moment of the effective level of the gate drive signal; according to the effective time difference, setting the timing of the gate drive signal includes: setting the timing of the gate drive signal so that while keeping the effective level duration of the data signal and the gate drive signal unchanged, the first time difference between the application moment of the data signal and the start moment of the effective level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference.

[0008] For example, the ratio of the effective time difference to the scanning period of the gate driving signal ranges from 35% to 45%.

[0009] For example, the ratio of the effective time difference to the scanning period of the gate driving signal is 39%.

[0010] For example, the ratio of the first time difference to the scanning period of the gate driving signal ranges from 22% to 37%.

[0011] For example, the scanning period of the gate driving signal is 8.7 μs, and the range of the first time difference is 1.9 μs to 3.2 μs.

[0012] For example, the first time difference is greater than a transition time of the power supply voltage.

[0013] For example, the driving method also includes setting the duration of the latch input period according to the effective time difference, so that the time difference between the end time of the latch input period and the effective level start time of the gate drive signal of the next scanning cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

[0014] For example, the method according to the embodiment of the present disclosure further includes: in a first driving mode, the first time difference is A1; in a second driving mode, the first time difference is A2, and A1 is greater than A2.

[0015] According to a second aspect, the present disclosure provides a display device comprising: a pixel array; a timing controller; a source driver configured to generate a data signal under the control of the timing controller; and a gate driver configured to generate a gate drive signal under the control of the timing controller, wherein the timing controller is configured to set the timing of the gate drive signal according to the effective time difference between the effective signal of the data signal and the gate drive signal, so as to drive the pixel array by the gate drive signal.

[0016] For example, the effective time difference includes a first time difference between the application moment of the data signal and the start moment of the effective level of the gate drive signal; the timing controller is also configured to: set the timing of the gate drive signal so that while keeping the effective level duration of the data signal and the gate drive signal unchanged, the first time difference between the application moment of the data signal and the start moment of the effective level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference.

[0017] For example, the ratio of the effective time difference to the scanning period of the gate driving signal ranges from 35% to 45%.

[0018] For example, the ratio of the effective time difference to the scanning period of the gate driving signal is 39%.

[0019] For example, the ratio of the first time difference to the scanning period of the gate driving signal ranges from 22% to 37%.

[0020] For example, the scanning period of the gate driving signal is 8.7 μs, and the range of the first time difference is 1.9 μs to 3.2 μs.

[0021] For example, the first time difference is greater than a transition time of the power supply voltage.

[0022] For example, the timing controller is also configured to set the duration of the latch input period according to the effective time difference, so that the time difference between the end time of the latch input period and the start time of the effective level of the gate drive signal of the next scanning cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

[0023] For example, the display device according to the embodiment of the present disclosure further includes an external power supply, which is provided between the voltage source of the source driver and the pixel array.

[0024] For example, the display device according to the embodiment of the present disclosure further includes a resistor disposed between the voltage source of the source driver and the pixel array.

[0025] For example, the timing controller is further configured to set: in the first driving mode, the first time difference is A1; in the second driving mode, the first time difference is A2, and A1 is greater than A2. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1A is a timing diagram of signals for driving a display panel according to an example;

[0027] FIG1B is a schematic diagram of an abnormal display screen of a display device driven by the signal timing diagram of FIG1A ;

[0028] FIG2 is a flowchart of a driving method according to an embodiment of the present disclosure;

[0029] FIG3 is a signal timing diagram according to an embodiment of the present disclosure;

[0030] FIG4 is a signal timing diagram according to another embodiment of the present disclosure;

[0031] FIG5A is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure;

[0032] FIG5B is a signal timing diagram of the pixel circuit in FIG5A ;

[0033] FIG6 is a block diagram of a display device according to one embodiment of the present disclosure; and

[0034] FIG. 7 is a block diagram of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0036] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure shall have the same general meaning as those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0037] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to a direct connection between two components or a connection between two components via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0038] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vdata can represent both a data signal and the level of the data signal. Similarly, the symbol Gate can represent both a gate drive signal and the level of the gate drive signal. The symbol VINT can represent both a predetermined initial voltage terminal and the voltage of the initial signal. The symbol ELVDD can represent both a power supply and the power supply voltage provided by the power supply. The following embodiments are the same and will not be repeated here.

[0039] Figure 1A is a signal timing diagram for driving a display panel according to an example. Figure 1B is a schematic diagram of an abnormal display image of a display device driven by the signal timing diagram of Figure 1A.

[0040] As shown in Figure 1A, when the data signal Vdata is applied, changes in the reference voltage AVDD of the data signal Vdata can cause a jump in the power supply voltage VDD. Period a can be a period in which the start time of the gate drive signal Gate's effective level is delayed compared to the application time of the data signal Vdata, and period b can be a period in which the end time of the gate drive signal Gate's effective level is earlier than the end time of the application of the data signal Vdata. If the noise generated by the jump in the power supply voltage VDD is not eliminated at the start time of the gate drive signal Gate's effective level, that is, during period a, crosstalk may occur on the display screen of the display panel, affecting the display quality of the display panel.

[0041] As shown in FIG1B , the display panel includes pixel units 110, 120, and 130. During the display process, a gate drive signal Gate scans the pixel units row by row. The applied data signal Vdata causes pixel unit 110 to display a black image, while pixel units 120 and 130 display a white image. Due to noise generated by the jumps in the power supply voltage VDD, pixel units 120 and 130 are affected by crosstalk from pixel unit 110, causing pixel units 120 and 130 to actually display a gray image, thereby affecting the display quality of the display panel.

[0042] The present disclosure provides a driving method for driving a pixel array, comprising setting a timing of a gate driving signal according to an effective time difference between an effective signal of a data signal and a gate driving signal; and driving the pixel array by the gate driving signal.

[0043] FIG2 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0044] As shown in FIG. 2 , the driving method may include operations S210 to S220 .

[0045] In operation S210, a timing of a gate driving signal is set according to a valid time difference between a data signal and a valid signal of the gate driving signal.

[0046] For example, the duration of the data signal is longer than the effective level of the gate drive signal, which can avoid the driving transistor not writing the data signal when it is turned on. In a scanning cycle, the application time of the data signal is before the start time of the effective level of the gate drive signal, and the end application time of the data signal is after the end time of the effective level of the gate drive signal. The ratio of the effective time difference to the scanning period of the gate drive signal is in the range of 35-45%. As shown in Figure 1A, the effective time difference between the effective signal of the data signal and the gate drive signal includes period a and period b. The scanning period of the gate drive signal is 1H. For example, the scanning period of the gate drive signal is the time required to scan a row of the pixel array.

[0047] For example, the effective time difference can be fixed for any pixel array. By setting the timing of the gate drive signal based on the effective time difference, noise generated by the transition of the power supply voltage VDD can be completely eliminated before the gate drive signal reaches an effective level, thereby alleviating crosstalk on the display panel.

[0048] In operation 220 , the pixel array is driven by a gate driving signal.

[0049] For example, a display panel includes a pixel array. By setting the timing of a gate driving signal according to the disclosed embodiment, the gate driving signal drives the pixel array, thereby alleviating the crosstalk phenomenon occurring on the display panel.

[0050] Through the embodiments of the present disclosure, the noise generated by the jump of the power supply voltage VDD can be completely eliminated before the start time of the effective level of the gate driving signal, thereby alleviating the crosstalk phenomenon on the display panel.

[0051] The present disclosure provides an embodiment for setting the timing of a gate driving signal. The effective time difference includes a first time difference between the application time of the data signal and the effective level start time of the gate driving signal.

[0052] Operation S210 includes setting the timing of the gate drive signal based on an effective time difference between the effective signals of the data signal and the gate drive signal. The step includes setting the timing of the gate drive signal such that, while maintaining the effective level durations of the data signal and the gate drive signal unchanged, a first time difference is greater than 0.5 times the effective time difference and less than the effective time difference. A ratio of the first time difference to a scanning period of the gate drive signal ranges from 22% to 37%.

[0053] Figure 3 is a signal timing diagram according to an embodiment of the present disclosure. As shown in Figure 3, the low level of the gate drive signal is the effective level. In the example of Figure 3, Gate(N) represents the gate signal of the Nth row of pixels, and Gate(N+1) represents the gate signal of the N+1th row of pixels, where N is an integer greater than or equal to 1. The first time difference is period a, and the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference. The effective time difference also includes a second time difference between the end moment of the effective level of the gate drive signal and the end moment of application of the data signal. The second time difference is period b. The second time difference b is less than 0.5 times the effective time difference and greater than 0.

[0054] For example, for a common timing of the gate drive signal, the first time difference and the second time difference may both be equal to 0.5 times the effective time difference. For example, for the default timing of the gate drive signal, when the duration of the gate drive signal's effective level and the effective time difference of the data signal are 3.4 μs, the first time difference and the second time difference are both 1.7 μs. In this case, it can be considered that the default values ​​of the first time difference and the second time difference may be 0.5 times the effective time difference, for example, 1.7 μs. While keeping the effective level duration of the gate drive signal unchanged, the first time difference can be increased by delaying the start moment of the effective level of the gate drive signal, so that the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference.

[0055] The first time can be greater than the duration of the power supply voltage jump. When the first time difference is large enough, the noise generated by the power supply voltage VDD jump can be completely eliminated before the gate drive signal starts to reach an effective level, thereby alleviating the crosstalk phenomenon on the display panel.

[0056] Optionally, the first time difference is 1.2 to 2.4 times the transition time of the power supply voltage VDD. This can better ensure that noise generated by the transition of the power supply voltage VDD is completely eliminated before the gate drive signal reaches a valid level. For example, the first time difference is 2.4 to 3.2 μs, which is greater than the duration of the power supply voltage transition of 2.0 μs.

[0057] Since the effective level duration of the data signal and the gate drive signal remains unchanged, the effective time difference (period a and period b) can be considered to be unchanged. When the first time difference (period a) increases relative to the default value (the first time difference is 0.5 times the effective time difference), the second time difference (period b) will decrease accordingly. In addition, the first time difference also needs to be less than the effective time difference. If the first time difference is increased without limit, the second time difference will not exist, that is, the end application moment of the data signal is before the end moment of the effective level of the gate drive signal, thereby causing no data signal to be written when the drive transistor is turned on.

[0058] The present disclosure provides a driving method according to another embodiment. The driving method further includes, in addition to operations S210 to S220, setting a duration of a latch input period according to the effective time difference, such that a time difference between an end of the latch input period and a start of an effective level of a gate driving signal in a next scanning cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

[0059] The interval between two adjacent data signals is the latch input period. Changing the latch input period causes the data signal frequency to change, altering the timing of data signal application in the next scan cycle. For example, decreasing the latch input period causes the data signal application time to be advanced in the next scan cycle. Changing the latch input period also causes a change in the data signal reference voltage AVDD, thereby changing the transition timing of the power supply voltage signal VDD.

[0060] Figure 4 is a signal timing diagram according to another embodiment of the present disclosure. In the example of Figure 4, Gate(N) represents the gate signal of the Nth row of pixels, Gate(N+1) represents the gate signal of the N+1th row of pixels, and Gate(N+2) represents the gate signal of the N+2th row of pixels. As shown in Figure 4, the duration of the first latch input period of the normal timing of the data signal is Latch input 1. For example, the signal timing diagram shown in Figure 4 can be obtained by first setting the timing of the gate drive signal and then setting the duration of the latch input period while keeping the effective level duration of the gate drive signal unchanged. The timing of the gate drive signal is first set so that the first time difference (period a) is greater than 0.5 times the effective time difference and less than the effective time difference. The duration of the second latch input period is then set to Latch input 2. The duration of the second latch input period, Latch input 2, is shorter than the duration of the first latch input period, Latch input 1. This allows the first time difference (period a') between the start time of application of the data signal for the pixels in the N+1th row and the start time of the effective level of the gate drive signal Gate(N+1) in the next row to be greater than the first time difference (period a) between the start time of application of the data signal for the pixels in the Nth row and the start time of the effective level of the gate drive signal Gate(N) in the Nth row. The second time difference a' is also greater than 0.5 times the effective time difference and less than the effective time difference.

[0061] It should be noted that FIG4 is merely intended to illustrate how the first time difference may change due to a change in the duration of the latch input period. Optionally, in actual driving applications, after the duration of the latch input period is set, the duration of the latch input period remains unchanged. For example, in the disclosed embodiment, the duration of the latch input period in the timing of the data signal is set to Latch input 2.

[0062] For example, the driving method can also be to set the duration of the latch input period without changing the default timing of the gate drive signal, so that the time difference between the end time of the latch input period and the start time of the effective level of the gate drive signal of the next scanning cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

[0063] For example, in the above-mentioned normal timing of the data signal, the duration of the latch input period can be 1.5 μs. While maintaining the data signal application duration and the normal timing of the gate drive signal, the first time difference can be increased by reducing the duration of the latch input period, so that the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference. The duration of the latch input period can be set to 1.2 μs-0.3 μs.

[0064] Alternatively, the duration of the latch input period may be set to 0.4 μs.

[0065] Optionally, the overlap length of the data signal application duration and the gate drive signal on duration can be kept constant, so as to ensure that when the gate drive signal is output to each row, the effective data signal loaded therein is substantially consistent.

[0066] Figure 5A is a schematic diagram of the structure of a pixel circuit according to one embodiment of the present disclosure. Figure 5B is a signal timing diagram of the pixel circuit in Figure 5A.

[0067] 5A and 5B , in the example of FIG5A , the transistors T1 to T7 may be P-type transistors. In the initialization phase, the low level of the reset signal Reste1 is an active level.

[0068] Under the control of the reset signal Restel, the transistor T1 is turned on, and the initialization signal VINT initializes the gate of the driving transistor T3, thereby initializing the gate voltage of the driving transistor T3 to VINT and charging the storage capacitor CST.

[0069] During the data write phase, the low level of the gate drive signal Gate and the low level of the reset signal Reste2 are active. Under the control of the gate drive signal Gate, transistors T2 and T4 are turned on. Driven by the voltage signal stored in the storage capacitor CST, the drive transistor T3 is turned on. The data signal Vdata is written to the node N1 via transistors T4, T3, and T2 along the path from the data signal terminal to the node N1. Under the control of the reset signal Reste2, transistor T7 is turned on, and the initialization signal VINT is written to the anode of the light-emitting element EL along the initialization path from the predetermined initial voltage terminal to the light-emitting element EL, thereby initializing the anode voltage of the light-emitting element EL to VINT.

[0070] It is understood that the voltage difference (VINT-ELVSS) between the initial signal terminal VINT and the second power supply terminal ELVSS should be less than the threshold voltage Voled of the light-emitting element EL. ELVSS is the voltage at the second terminal of the light-emitting element OLED, and Voled is the light-emitting threshold voltage of the light-emitting element EL. This ensures that the light-emitting element EL does not emit light during the data writing phase.

[0071] During the light-emitting phase, the low level of the light-emitting control signal EM is active. Under the control of the light-emitting control signal EM, transistors T5 and T6 are turned on. Driven by the voltage signal stored in the storage capacitor CST, the driving transistor T3 is turned on. When transistors T5 and T6 are turned on, a drive current is applied to the light-emitting element EL along the light-emitting path from the power supply to the light-emitting element EL via transistor T5, the driving transistor T3, and the transistor T6, causing the light-emitting element EL to emit light.

[0072] Of course, the present invention can also be applied to other pixel circuits. For example, transistors T1 to T2 are N-type transistors, and transistors T3 to T7 can be P-type transistors.

[0073] For example, a crosstalk test was performed on a display panel including the pixel circuit shown in FIG5A. In one example, the display scanning frame rate was 60 Hz, and the display panel had a resolution of 1915 lines. Thus, the gate drive signal Gate had a scanning period of 1H = 8.7 μs, an effective time difference a + b = 3.4 μs, and the default values ​​of the first time difference a and the second time difference b were 1.7 μs. In this case, the ratio of the effective time difference to the gate drive signal scanning period was 39%.

[0074] Optionally, the scanning period H of the gate drive signal Gate can be determined by the scanning frame frequency and the number of resolution lines of the display panel. For example, the scanning frame frequency is 60Hz, and the resolution lines of the display panel are 1915 lines. It should be noted that the resolution lines of the display panel may include real lines and virtual lines. For example, the real lines are 1888 lines and the virtual lines are 27 lines. The gate drive signal scans the virtual lines first and then scans the real lines. The scanning period 1H of the gate drive signal Gate is 1 / F = 1 / (60*1915) = 8.7μs, where: F = driving frequency * number of resolution lines.

[0075] Of course, other driving frequencies or resolutions are applicable in some embodiments. Optionally, the display panel can also have other resolutions, such as 10-30 Hz, or 90 Hz-120 Hz, or other resolutions, such as 2360 lines.

[0076] Optionally, the values ​​of the first time difference a and the second time difference b are changed by setting the timing of the gate drive signal and / or setting the duration of the latch input period. For example, the first time difference a is approximately 22 to 37% of 1 / F, where: F = driving frequency * number of resolution lines. The embodiment of the present disclosure changes the ratio of the first time difference a to the second time difference b by setting the timing of the gate drive signal and / or setting the duration of the latch input period. In order to test the crosstalk phenomenon under different ratios a / b, a crosstalk test was performed on the display panel including the pixel circuit shown in Figure 5A using the driving method shown in the embodiment of the present disclosure, and the test results are shown in Table 1. During the test, the ratio a / b of the first time difference to the second time difference ranged from 0.0625 to 16. The lower the crosstalk level, the more serious the crosstalk phenomenon.

[0077] Table 1

[0078] a3.23.02.52.01.71.40.90.40.2b0.20.40.91.41.72.02.53.03.2 Crosstalk level 43240-1-2-3-4

[0079] As shown in Table 1, starting from the default value of a = b = 1.7 μs, crosstalk gradually decreases as the ratio a / b increases. The crosstalk level reaches its highest level when a / b = 16 and a = 3.2 μs. As the ratio a / b decreases, the crosstalk level decreases and becomes increasingly severe. The crosstalk level reaches its highest level when a / b = 0.0625 and a = 0.2 μs.

[0080] When the scanning period H of the gate driving signal is 8.7 μs, in order to ensure the alleviation of crosstalk, the ratio a / b of the first time difference to the second time difference can be in the range of 1.27 to 16, and the range of the first time difference can be set to 1.9 μs to 3.2 μs.

[0081] For example, 4 test points are arbitrarily selected from the display area of ​​the display panel including the pixel circuit shown in FIG5A, and crosstalk test values ​​are performed on the test points. The crosstalk test values ​​in the horizontal and vertical directions of each test point are tested by setting the timing of the gate drive signal and setting the duration of the latch input period. For the same display panel, under the same test conditions, in a comparison scheme, the crosstalk test values ​​of the 4 test points are shown in Table 2, and the crosstalk test values ​​of the 4 test points using the technical solution according to the embodiment of the present disclosure are shown in Table 3. The duration of the latch input period in the above comparison scheme is 1.5μs, and the ratio a / b of the first time difference to the second time difference is in the range of 1. For example, the first time difference and the second time difference can both be set to a default value of 1.7μs. According to the technical solution of the embodiment of the present disclosure, the duration of the latch input period is 0.4 μs, the ratio a / b of the first time difference to the second time difference ranges from 1.27 to 16, and the ratio of the first time difference to the duration of the latch input period ranges from 475 to 8. For example, the first time difference is 3.2, the second time difference is 0.2, and the ratio of the first time difference to the duration of the latch input period is 8.

[0082] Table 2

[0083]

[0084] Table 3

[0085]

[0086] As shown in Table 2, using the above comparison scheme, the crosstalk test value of test point 2 in the horizontal direction H is 2.35%, indicating that test point 2 has serious crosstalk in the horizontal direction. As shown in Table 3, according to the technical solution of the embodiment of the present disclosure, the crosstalk test values ​​of the four test points in the horizontal and vertical directions are all less than 2.00%, indicating that all test points according to the technical solution of the embodiment of the present disclosure have almost no crosstalk. Among them, the crosstalk test value of test point 2 in the horizontal direction H is 0.95%, indicating that test point 2 has almost no crosstalk in the horizontal direction. This verifies that the crosstalk phenomenon is improved by setting the timing of the gate drive signal and setting the duration of the latch input period. After increasing the ratio a / b of the first time difference to the second time difference, the crosstalk phenomenon of the display panel is alleviated.

[0087] The present disclosure also performs crosstalk testing and improvement on the display panel under various working modes. For example, the working modes include high-frequency drive and low-frequency drive. For example: in the first drive mode, the first time difference is A1, for example, A1 = 2.6μs-3μs; in the second drive mode, the first time difference is A2, A1 = 2.0μs-2.4μs, wherein the first time difference is A1 greater than A2. Optionally, the first drive mode is high-frequency drive (for example: 60HZ-240HZ), and the second drive mode is low-frequency drive (for example: 10HZ-50HZ); of course, the second drive mode can also be high-frequency drive (for example: 60HZ-240HZ), and the first drive mode is low-frequency drive (for example: 10HZ-50HZ). In one embodiment, in order to alleviate the crosstalk phenomenon of the display panel, the first time difference under the high-frequency drive mode (120HZ) is less than the first time difference under the low-frequency drive mode (30HZ).

[0088] Through the embodiments of the present disclosure, the timing of the gate drive signal and / or the duration of the latch input period are set so that the first time difference and the second time difference have a ratio greater than 1. When the first time difference is greater than 0.5 times the effective time difference, the power supply voltage ELVDD jumps away from the effective level of the gate drive signal, and the noise generated by the jump of the power supply voltage ELVDD can be eliminated before the start time of the effective level of the gate drive signal. When the gate drive signal Gate reaches the effective level, the jump power supply voltage ELVDD has basically returned to the normal power supply voltage ELVDD, preventing noise interference from being written into the storage capacitor CST and improving crosstalk.

[0089] In the embodiment of the present disclosure, the timing of the light-emitting control signal EM can also be set according to the timing of the gate drive signal. Since the starting moment of the effective level of the gate drive signal is delayed relative to the starting moment of the effective level in the normal timing, the reset signal Reste1 can be set so that while the duration of the effective level of the reset signal Reste1 remains unchanged, the starting moment of the effective level of the reset signal Reste1 is delayed by the same amplitude as the starting moment of the effective level of the gate drive signal. Thus, by setting the timing of the light-emitting control signal, the duration of the effective level of the light-emitting control signal in the previous scanning cycle can be extended relative to the default duration of the effective level of the light-emitting control signal. By extending the duration of the effective level of the light-emitting control signal, the average current density can be reduced, thereby extending the life of the light-emitting element EL.

[0090] FIG6 is a block diagram of a display device according to an embodiment of the present disclosure. As shown in FIG6 , the display device 600 may include: a pixel array 610 , a timing controller 620 , a source driver 630 , and a gate driver 640 .

[0091] The pixel array 610 includes a plurality of pixels located at intersections of a plurality of scan lines S, a plurality of data lines DL, and a plurality of light emission control lines EM.

[0092] The source driver 630 is configured to generate a data signal under the control of the timing controller 620. The gate driver 640 is configured to generate a gate driving signal under the control of the timing controller 620.

[0093] The timing controller 620 is configured to set the timing of the gate driving signal according to the effective time difference between the data signal and the effective signal of the gate driving signal, so as to drive the pixel array through the gate driving signal.

[0094] The timing controller 620, the source driver 630 and the gate driver 640 are configured to execute the driving method of the embodiment described above to drive the pixel array 610. The timing controller 620 is configured to execute the operation S210 described above, which will not be described in detail here.

[0095] For example, the effective time difference includes a first time difference between the application time of the data signal and the effective level start time of the gate drive signal. The timing controller 620 is further configured to set the timing of the gate drive signal so that, while maintaining the effective level duration of the data signal and the gate drive signal unchanged, the first time difference between the application time of the data signal and the effective level start time of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference.

[0096] For example, the ratio of the effective time difference to the scanning period of the gate driving signal ranges from 35% to 45%.

[0097] For example, the ratio of the effective time difference to the scanning period of the gate driving signal is 39%.

[0098] For example, the ratio of the first time difference to the scanning period of the gate driving signal ranges from 22% to 37%.

[0099] For example, the scanning period of the gate driving signal is 8.7 μs, and the range of the first time difference is 1.9 μs to 3.2 μs.

[0100] For example, the first time difference is greater than a transition time of the power supply voltage, and the transition time of the power supply voltage is related to a reference voltage of the data signal.

[0101] For example, the timing controller 620 is further configured to set the duration of the latch input period according to the effective time difference so that the time difference between the end time of the latch input period and the effective level start time of the gate driving signal of the next scanning cycle is less than the effective time difference.

[0102] FIG. 7 is a block diagram of a display device according to another embodiment of the present disclosure.

[0103] The display device 700 may include a pixel array 710 , a timing controller 720 , a source driver 730 , a gate driver 740 , a power chip Power IC 750 , and a gamma correction chip GAM IC 760 .

[0104] The pixel array 710, timing controller 720, source driver 730 and gate driver 740 respectively have similar functions to the display device shown in FIG6 including pixel array 610, timing controller 620, source driver 630 and gate driver 640. For the sake of simplicity, this disclosure will not repeat them.

[0105] Power IC 750 is configured to input a reference voltage AVDD for data signals to a gamma correction chip GAM IC 760. GAM IC 760 performs gamma correction on the reference voltage AVDD for data signals and inputs the corrected reference voltage AVDD for data signals to pixel array 610. Power IC 750 is also configured to input an initialization signal VINT to pixel array 610.

[0106] In the embodiment of the present disclosure, the display panel can be tested for water ripple phenomenon and crosstalk by setting external devices, such as an external power supply, a voltage-stabilizing capacitor, or a filter resistor, at point N, point P, and point Q as shown in FIG. 7 .

[0107] For example, in order to test the water ripple phenomenon and crosstalk phenomenon of the display panel under different hardware conditions, a water ripple test and a crosstalk test are performed on the display panel including the pixel circuit shown in Figure 5A. The hardware conditions of the test include setting relevant external devices at points N, P and Q on the path of the reference voltage of the input data signal as shown in Figure 7, modifying the working mode of Power IC750, and replacing Power IC750 with Power IC 2. During the test, the duration of the latch input period of the data line input includes 0.4μs and 1.5μs. The test results are shown in Table 4. N indicates that the phenomenon shown in the table does not exist, and Y indicates that the phenomenon shown in the table exists. Since the water ripple phenomenon is improved when the external device is set at point Q, the test results of setting the relevant external devices at point Q are not shown in Table 4.

[0108] Table 4

[0109]

[0110] As shown in Table 4, when the duration of the latch input period is set to 1.5 μs, crosstalk occurs on the display panels of the display devices shown in Table 4. When the duration of the latch input period is set to 0.4 μs, crosstalk is considered to be absent. When the duration of the latch input period is set to 0.4 μs, no ripples occur when an external power supply is provided at point N or point P. The presence of a filter resistor at point N also indicates no ripples. The presence of ripples also occurs when Power IC 750 operates in normal mode rather than energy-saving mode. The presence of ripples also occurs when Power IC 750 is replaced with another power supply chip.

[0111] According to the embodiments of the present disclosure, an external power supply or filter resistor is provided between the power chip Power IC 750 and the gamma correction chip GAM IC 760 to optimize the reference voltage of the data signal and improve the water ripple problem. An external power supply or filter resistor can also be provided between the power chip Power IC 750 and the pixel array 710 to optimize the reference voltage of the data signal and alleviate the water ripple problem.

[0112] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0113] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, even if such combinations or combinations are not explicitly described in this disclosure. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0114] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A driving method for driving a pixel array, comprising: Setting the timing of the gate drive signal according to the effective time difference between the data signal and the effective signal of the gate drive signal; as well as The pixel array is driven by the gate driving signal.

2. The method according to claim 1, wherein The effective time difference includes a first time difference between the application time of the data signal and the effective level start time of the gate driving signal; The step of setting the timing of the gate driving signal according to the effective time difference includes: The timing of the gate driving signal is set so that the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference while maintaining the effective level duration of the data signal and the gate driving signal unchanged.

3. The method according to claim 2, wherein: The ratio of the effective time difference to the scanning period of the gate driving signal is in a range of 35-45%.

4. The method according to claim 3, wherein: The ratio of the effective time difference to the scanning period of the gate driving signal is 39%.

5. The method according to claim 2, wherein: The ratio of the first time difference to the scanning period of the gate driving signal ranges from 22% to 37%.

6. The method according to any one of claims 3 to 5, wherein The scanning period of the gate driving signal is 8.7 μs, and the first time difference ranges from 1.9 μs to 3.2 μs.

7. The method according to claim 2, wherein: The first time difference is greater than a transition time of the power supply voltage.

8. The method according to claim 2, further comprising: According to the effective time difference, the duration of the latch input period is set so that the time difference between the end moment of the latch input period and the effective level start moment of the gate drive signal of the next scanning cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

9. The method according to claim 2, further comprising: In the first driving mode, the first time difference is A1; In the second driving mode, the first time difference is A2, and A1 is greater than A2.

10. A display device comprising: pixel array; Timing controller; a source driver configured to generate a data signal under the control of the timing controller; as well as a gate driver configured to generate a gate drive signal under the control of the timing controller, Wherein, the timing controller is configured as follows: The timing of the gate driving signal is set according to the effective time difference between the data signal and the effective signal of the gate driving signal, so as to drive the pixel array by the gate driving signal.

11. The display device according to claim 10, wherein The effective time difference includes a first time difference between the application time of the data signal and the effective level start time of the gate driving signal; The timing controller is further configured as: The timing of the gate drive signal is set so that, while keeping the effective level duration of the data signal and the gate drive signal unchanged, the first time difference between the application moment of the data signal and the effective level start moment of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference.

12. The display device according to claim 11, wherein The ratio of the effective time difference to the scanning period of the gate driving signal is in a range of 35-45%.

13. The display device according to claim 11, wherein The ratio of the effective time difference to the scanning period of the gate driving signal is 39%.

14. The display device according to claim 11, wherein The ratio of the first time difference to the scanning period of the gate driving signal ranges from 22% to 37%.

15. The display device according to any one of claims 12 to 14, wherein: The scanning period of the gate driving signal is 8.7 μs, and the first time difference ranges from 1.9 μs to 3.2 μs.

16. The display device according to claim 11, wherein The first time difference is greater than a transition time of the power supply voltage.

17. The display device according to claim 10, wherein The timing controller is further configured to set the duration of the latch input period according to the effective time difference, so that the time difference between the end moment of the latch input period and the effective level start moment of the gate drive signal of the next scanning cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

18. The display device according to claim 10, further comprising: The external power supply is arranged between the voltage source of the source driver and the pixel array.

19. The display device according to claim 10, further comprising: The resistor is arranged between the voltage source of the source driver and the pixel array.

20. The display device according to claim 11, wherein The timing controller is further configured to set: in a first driving mode, the first time difference is A1; in a second driving mode, the first time difference is A2, and A1 is greater than A2.