Ultra-high-framerate and continuous-readout pixel for image sensor

Abstract

This invention is related to pixel design for ultra-high-framerate and continuous-readout image sensors, such as Single Photon Avalanche Diode (SPAD) and Complementary Metal-Oxide Semiconductor (CIS)

Description

This invention relates to a pixel design for ultra-high-framerate and continuous-readout image sensors, especially Single Photon Avalanche Diode (SPAD) and Complementary Metal-Oxide-Semiconductor Image Sensor (CIS). An ultra-high-framerate image sensor is an imaging device capturing frames at the rate of millions per second, allowing it to record transient events or fastmoving subjects with fine details. Conventional high-speed image sensors rely on capturing only a finite number of frames, which are first stored in memory circuits and later read out in a process termed a ‘burst’. However, there is a time gap between the two bursts while the acquisition of new frames is stopped until the readout is finalized and memory circuits are ready for another burst of frames. Image information in the time gap is permanently lost and cannot be recovered. In this patent, a pixel design is provided that allows for a continuous in-pixel frame generation and readout, ensuring all image information is collected without time gaps between bursts. Here, the design of a SPAD sensor is taken as an example to illustrate the continuous ultra-high-framerate imaging method. SPAD-based pixels are natively digital and respond to a single photon entering the diode with a microscopic current termed an ‘avalanche’, triggered by the first photogenerated electron. The device gain is ‘infinite’ and therefore there is no associated readout noise. This can allow for a Photon Shot Noise (PSN) limited imaging, where the only noise source is the PSN resulting from the quantum nature of light and inherent to all imaging technologies. SPAD pixels can count incoming photons providing a digital number as the pixel output, alleviating the need to apply the time consuming analogue-to-digital conversion. It would be desirable to provide a high-speed image sensor offering continuous capture of the unlimited number of frames and having a reduced readout noise, preferably allowing for the photon shot noise limited operation. In a first aspect of the invention there is provided a memory circuit for a high-framerate continuous-readout pixel comprising: two memory banks operated in an interleaved way, while one is receiving light intensity information and the other is being read out; a demultiplexer directing the light intensity data to either odd memory bank or even memory bank according to a memory bank address signal; a memory address decoder choosing said memory bank for the read out; and a readout and pixel output driving circuits block driving the output terminals of the memory circuit based on a row select signal; wherein the light intensity data is input to the demultiplexer, the outputs of said demultiplexer are connected to the inputs of said memory banks, and the outputs of said memory banks are connected to said readout and pixel output driving circuits block. In a second aspect of the invention there is provided a method of operating the memory circuit for a high-framerate continuous-readout pixel comprising: setting a demultiplexer to direct the light intensity data to the odd memory bank; writing the light intensity data to the odd memory bank for a number of N frames; simultaneously reading out a previously stored series of N frames from the even memory bank to the outside of the memory circuit; setting a demultiplexer to direct the light intensity data to the even memory bank once the writing of the N frames to the odd memory bank is complete; writing the light intensity data to the even memory bank for a number of N frames; simultaneously reading out a previously stored series of N frames from the odd memory bank to the outside of the memory circuit; and repeating said steps as long as needed for the desired number of frames to be recorded. In a third aspect of the invention there is provided a high-framerate continuous-readout pixel comprising: a sensing device converting the input light intensity into an electrical signal; a frontend circuits biasing and reading out the sensing device; and a memory circuit comprising: two memory banks working in an interleaved way, while one is receiving light intensity information and the other is being read out; a demultiplexer directing the light intensity data to either odd memory bank or even memory bank according to the memory bank address signal; a memory address decoder choosing said memory bank for the read out; and a readout and pixel output driving circuits block driving the output terminals of the memory circuit based on the row select signal; wherein the light intensity data is input to the demultiplexer, the outputs of said demultiplexer are connected to the inputs of said memory banks, and the outputs of said memory banks are connected to said readout and pixel output driving circuits block; wherein the output of said sensing device is input to the frontend circuits, and the output of said frontend circuit is connected to the inputs of said memory circuits. In a fourth aspect of the invention there is provided a high-framerate continuous-readout image sensor comprising: a pixel array comprising a plurality of pixels arranged in a two-dimensional shape comprising rows and columns, each pixel comprising: a sensing device converting the input light intensity into an electrical signal; a frontend circuits biasing and reading out the sensing device; and a memory circuit comprising; two memory banks working in an interleaved way, while one is receiving light intensity information and the other is being read out; a demultiplexer directing the light intensity data to either odd memory bank or even memory bank according to the memory bank address signal; a memory address decoder choosing said memory bank for the read out; and a readout and pixel output driving circuits block driving the output terminals of the memory circuit based on the row select signal; wherein the light intensity data is input to the demultiplexer, the outputs of said demultiplexer are connected to the inputs of said memory banks, and the outputs of said memory banks are connected to said readout and pixel output driving circuits block; wherein the output of said sensing device is input to the frontend circuits, and the output of said frontend circuit is connected to the inputs of said memory circuits. Other aspects of invention are described in the appended independent and dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings in which: Figure 1 shows a block diagram of a high-framerate continuous capture SPAD pixel using a dual channel memory array. Figure 2 shows a timing diagram of a high-framerate continuous capture SPAD pixel using a dual channel memory array. Figure 3 shows a block diagram of a high-framerate continuous capture SPAD pixel using two banks of shift registers. Figure 4 shows a timing diagram of a high-framerate continuous capture SPAD pixel using two banks of shift registers. Figure 5 shows a schematic diagram of a shift register memory bank and its control and readout circuits. Figure 6 shows a timing diagram a of a shift register memory bank and its control and readout circuits. Figure 7 the comparison of exposure times in state-of-the-art pixels and the ultra-high framerate and continuous-readout pixel. Figure 8 shows a schematic diagram of two memory banks using memory elements implemented as a shift register. Figure 9 shows a block diagram of an image sensor based on high-framerate continuous capture SPAD pixel. Figure 10 shows a readout timing diagram of an image sensor based on high-framerate continuous capture SPAD pixel. DETAILED DESCRIPTION OF THE EMBODIMENTS Ultra-high-framerate and continuous-readout pixel Figure 1 shows a schematic diagram of an ultra-high-framerate and continuous-readout pixel 110. The pixel utilizes two memory banks 160 to achieve a continuous capture and readout of the unlimited number of frames. Two memory banks are activated in the alternate fashion, while one of them is active for the write operation, the other bank is available for the readout of the previously captured data. Thanks to this, there is no time gap between the two frame series and no image information is lost during the pixel readout. Each memory bank 160 may contain a plurality of memory elements 170. A series of N frames may be stored in the memory bank 160, allowing for the N times increased time available to readout the data from the pixel, provided the pixel output 1150 consists of a bus composed of a plurality of parallel wires. The ultra-high-framerate and continuous-readout pixel 110 shown on the Figure 1 utilizes a SPAD device, which is interfaced to the pixel circuit by a SPAD quenching and frontend block 120. Output of the SPAD quenching and frontend block 120 is connected to a photon counter 130, which provides a digital count corresponding to the number of the input SPAD pulses. The photon counter output is connected to a demultiplexer 140. Based on a memory bank address 190, one of the memory channels 180 is selected and used to store the photon counts for each frame in the series. The memory channels 180 are connected to the two memory banks 160, storing the photon count in a suitable memory element 170. An exposure time control signal 1100 is used to reset the photon counter 130 between the capture of the subsequent frames and to shift the photon count written in the memory bank 160 to the next memory element 170. The exposure time control signal 1100 is provided to an exposure time control demultiplexer 150 directing said signal to the currently selected memory bank 160. Consequently, the photon counts are shifted between the subsequent memory elements 170 only in the active memory bank 160. The detailed implementation of the shifting operation may depend on the used memory type and circuits in the memory bank 160. Memory bank address 190 is provided to the previous address calculation block 1110. Based on the calculated previous memory bank address, memory address decoder 1120 selects the memory bank 160 for the pixel readout. While the photon counts corresponding to the new frames are being written to one of the memory banks 160, the other bank is used to readout the previously stored N frames out of the pixel circuit. The corresponding photon counts are made available on the column buses connecting memory banks 160 to the readout and pixel output driving circuits block 1130. Based on a row select signal 1140, the readout and pixel output driving circuits block 1130 outputs the photon counts to the pixel output 1150. Figure 2 shows a timing diagram of the ultra-high-framerate and continuous-readout pixel 110. A frontend output trace 210 shows a sample train of digital pulses representing detected incoming photons. Every rising edge of the frontend output trace 210 marks the arrival of a photon. A photon counter output trace 220 shows a corresponding digital count provided by the photon counter 130. When a memory bank address trace 230 is equal to the logic low, the photon count is demultiplexed to the memory channel 1, as shown on memory channel 1 trace 240. Conversely, when the memory bank address trace 230 is equal to the logic high, memory channel 2 is selected and the photon count appears on the memory channel 2 trace 250. Pulses shown on the exposure time control trace 260 are used to set the desired exposure time and to control the shifting of the frame data between memory elements 170. The rising edge of the pulse initializes sampling the photon count into the first memory element 170 and shifting of the previous frame data to the respective next memory element 170. The falling edge of the same pulse is used to reset the photon counter 130 before the capture of the next frame. This time delay between sampling and resetting the counter, equal to the length of the pulse, ensures that all frame data can be successfully stored in the memory bank 160. As a result, an exposure time is equal to the time interval between the two rising edges of the pulses on the exposure time control trace 260. The photon count captured in the given frame is shifted between all memory elements 170 in the activated memory bank 160, as can be seen on memory element 1 in bank 1 trace 270, memory element 2 in bank 1 trace 280, and memory element N in bank 1 trace 290. While memory bank 1 is used for the capture of the new frames, the memory bank 2 is selected for the readout, as the previous memory bank address trace 2130 is equal to the logic high. The photon counts captured for each frame in the previous series is available at the outputs of all memory elements 170 in the memory bank 2, as shown on memory element 1 in bank 2 trace 2100, memory element 2 in bank 2 trace 2110, and memory element N in bank 2 trace 2120. When the row select trace 2140 is equal to the logic high, the readout and pixel output driving circuits block 1130 settles the photon counts from all memory elements 170 in the memory bank 2 at the pixel output 1150. Next, after N frames are captured in the memory bank 1, the memory bank address trace 230 toggles to the logic high activating the memory bank 2 for the capture of the next N frames. Consequently, the previous memory bank address trace 2130 toggles to the logic low, selecting memory bank 1 for the readout. The implementation of the two memory bank pixel readout scheme may be varied and is not limited to the SPAD-based pixels. Other possible embodiments include 4T pixels with two analogue memory banks, 3T pixels with two analogue memory banks, 3T or 4T pixels comprising an in-pixel Analogue-to-Digital Converter (ADC) and digital memory banks, and other pixel circuits. SPAD-based pixel implementations of the two memory bank pixel readout scheme may also vary. The pixel blocks shown on Figure 1 can be implemented using different circuits providing the same functionality, for example the photon counter 130 can be implemented both as digital or analogue counter, providing the use of a suitable demultiplexer and memory bank circuits. The timing diagram shown on the Figure 2 is purely illustrative and may be varied, according to the implementation of the two memory bank pixel readout scheme and corresponding pixel circuits. Figure 3 shows a schematic diagram of a high-framerate continuous capture SPAD pixel using two photon counters 310. The two photon counters 130 are activated in the alternating fashion, allowing for the simultaneous capture of the photon count by one of them, while the other is available for the readout of the previously captured count out of the pixel. This pixel circuit allows for the continuous readout and gapless frame capture while having the advantage of a power and area-efficient design, provided the sensor row time is long enough to settle the photon count at the pixel output 1240. The high-framerate continuous capture SPAD pixel using two photon counters 310 shown on the Figure 2 utilizes a SPAD device, which is interfaced to the pixel circuit by a SPAD quenching and frontend block 120. Output of the SPAD quenching and frontend block 120 is connected to a demultiplexer 140. Based on a memory bank address 190, one of the memory channels 180 is selected, connecting the output of the SPAD quenching and frontend block 120 to the photon counter 130. Memory bank address 190 is provided to the previous address calculation block 1110. Using the previous memory bank address, the readout and pixel output driving circuits block 1130 selects the photon counter 130 for the pixel readout. PMOS pull-up transistors 320 are used at the inputs to both photon counters 130 in order to ensure the captured photon count is not changing during the pixel readout, while the respective photon counter input is not driven by the demultiplexer 140. Counter 1 reset signal 330 and counter 2 reset signal 340 are used to reset the photon counter before the start of the capture of the next frame. Based on the row select signal 1140, the readout and pixel output driving circuits block 1130 outputs the photon counts to the pixel output 1150. Figure 4 shows a timing diagram of the high-framerate continuous capture SPAD pixel using two photon counters 310. A frontend output trace 410 shows a sample train of digital pulses representing detected incoming photons. Every falling edge of the frontend output trace 410 marks the arrival of a photon. When a memory bank address trace 420 is equal to the logic low, the train of pulses is demultiplexed to the memory channel 1, as shown on memory channel 1 trace 430. Conversely, when the memory bank address trace 420 is equal to the logic high, memory channel 2 is selected and the train of pulses is available at the memory channel 2 trace 440. Photon counter 1 output trace 450 and photon counter 2 output trace 460 show the rising photon counts, according to the incoming pulses. When a previous memory bank address trace 470 is equal to the logic high, photon counter 2 is selected for the readout and the stored photon count is available for the readout and pixel output driving circuits block 1130. While the row select trace 4100 is equal to the logic high, the readout and pixel output driving circuits block 1130 settles the photon count at the pixel output 1150. The logic low appearing on the counter 1 reset trace 480 and counter 2 reset trace 490 resets the respective photon count to 0 before the before the capture of the next frame. The falling edges of the counter reset pulses are aligned with the toggling of the memory bank address trace 420 to ensure counting of all arriving photons till the end of the given frame. An exposure time is equal to the time interval between the rising edge of the counter 1 reset trace 480 or counter 2 reset trace 490 and the next toggle of the memory bank address trace 420. The implementation of the high-framerate continuous capture SPAD pixel using two photon counters 310 may be varied using any suitable circuits allowing to realize the desired pixel operation. The pixel blocks shown on Figure 3 may be implemented using different circuits providing the same functionality, for example the photon counter 130 can be implemented both as digital or analogue counter. The timing diagram shown on the Figure 4 is purely illustrative and may be varied, according to the implementation of the high-framerate continuous capture SPAD pixel using two photon counters 310. Figure 5 shows a schematic diagram of a high-framerate continuous capture SPAD pixel using two photon counters with no counter reset signal 510. This eliminates the need for the external reset provided for the both counters. This is advantageous compared to the design shown on Figure 3, as the usage of signal routing resources is decreased. The pixel block diagram is modified by adding pulse shortening blocks 510. Their inputs are the memory bank address 190 and the previous memory bank address calculated by the previous address calculation block 1110. The shortened pulses are used as the reset signals for the photon counters 130 used for both memory channels 180. The pulse shortening blocks 510 may be implemented as such as they allow for an externally-controllable length of the shortened pulse. Figure 6 shows a timing diagram of the high-framerate continuous capture SPAD pixel using two photon counters with no counter reset signal 510. A frontend output trace 610 shows a sample train of digital pulses representing detected incoming photons. Every falling edge of the frontend output trace 610 marks the arrival of a photon. When a memory bank address trace 620 is equal to the logic low, the train of pulses is demultiplexed to the memory channel 1, as shown on memory channel 1 trace 630. Conversely, when the memory bank address trace 620 is equal to the logic high, memory channel 2 is selected and the train of pulses is available at the memory channel 2 trace 640. Incoming photons are counted by the two alternating counters as shown on photon counter 1 output trace 650 and photon counter 2 output 660 trace. When a previous memory bank address trace 670 is equal to the logic high, photon counter 2 is selected for the readout and the stored photon count is available for the readout and pixel output driving circuits block 1130. While the row select trace 6100 is equal to the logic high, the readout and pixel output driving circuits block 1130 settles the photon count at the pixel output 1150. Counter 1 reset trace 680 and counter 2 reset trace 690 are derived from the previous memory bank address trace 670 and the memory bank address trace 620 respectively by the pulse shortening blocks 510. The logic high appearing on the counter 1 reset trace 680 and counter 2 reset trace 690 resets the respective photon count to 0 before the before the capture of the next frame. An exposure time is equal to the time interval between the falling edge of the said reset traces and the next toggle of the memory bank address trace 620. The implementation of the high-framerate continuous capture SPAD pixel using two photon counters with no counter reset signal 510 may be varied using any suitable circuits allowing to realize the desired pixel operation. The pixel blocks shown on Figure 5 may be implemented using different circuits providing the same functionality, for example the photon counter 130 can be implemented both as digital or analogue counter. The timing diagram shown on the Figure 6 is purely illustrative and may be varied, according to the implementation of the high-framerate continuous capture SPAD pixel using two photon counters 510. Continuous-exposure pixel Figure 7 shows the comparison of exposure times in state-of-the-art pixels and the ultra-high framerate and continuous-readout pixel 310 in relation to the total frame time. Conventional CIS 4T pixels offer rolling or global shutter operation mode. In this pixel architecture the photogenerated charges are transferred from a pinned photodiode to the sense node where charge-to-voltage conversion is performed. In both modes, the maximum achievable exposure time is always shorter than the total frame time and is equal to the time span between the falling edge of the reset pulse and the falling edge of the transfer pulse. The rolling shutter exposure 7110 is longer than global shutter exposure 7120 for the same conventional 4T pixel assuming the same total frame time allotted for the pixel operation. This is because the global shutter mode necessitates ending the exposure at the same time for all pixels in the pixel array and allowing a longer time for the combined readout of every row of pixels before the next exposure can start. The exposure time 7130 of the ultra-high framerate and continuous-readout pixel 310 can be equal to the total frame time, simultaneously allowing for the global shutter operation. Memory banks implemented as a shift register Figure 8 shows a schematic diagram of two memory banks implemented as a shift register. This implementation benefits from the data shifting operation natively available for the shift register circuit, readily for use in the ultra-high-framerate and continuous-readout pixel 110. A photon counter output 810 consisting of M bits is demultiplexed by the demultiplexer 140 into one of the memory channels 180, based on the memory channel address signal 190. Each of said channels 180 is connected to the inputs of the first memory element 170 of each memory bank 160. The memory element 170 is implemented as M parallel D flip flops 820, corresponding to the M bits in the photon counter output 810. Outputs Q of the D flip flops 820 are daisy-chain connected to the inputs D of said D flip flops 820 in the next memory element 170 in the memory bank 160. Exposure time control signal 1100 is provided to the clock input of all D flip flops 820 in every memory element 170, enabling the shifting of all data bits between the memory elements. The shifting operation may be triggered by the rising or falling edge of the exposure time control signal 1100, depending on the used implementation of the D flip flop 820. Memory channel address signal 190 is provided to the previous address calculation block 1110, implemented as an inverter 840. Calculated previous memory bank address is input to the memory address decoder 1120. A decoded memory channel address is provided to a buffer 830 and an inverter 840, driving respectively an NMOS transistor and a PMOS transistor, consisting of a transmission gate 850, acting as a select switch for every of the M bits stored in each memory element 170. When said transmission gate 850 is closed, the M bits are settled on the column wires connected to the readout and pixel output driving circuits block 1130. Said block may be implemented as N groups of M buffers 830, having transmission gates 850 connected to their outputs and acting as a select switch. The row select signal 1140 is connected to a buffer 830 and an inverter 840, driving respectively an NMOS transistor and a PMOS transistor in the transmission gates 850. The readout and pixel output driving circuits block 1130 is driving the pixel output 1150, consisting of M times N bits, for all N frames stored in the memory bank 160. Ultra-high-framerate and continuous-readout image sensor Figure 9 shows a block diagram of an ultra-high-framerate and continuous-readout image sensor 910. The pixel array 920 is composed of L by K pixels 930. A plurality of timing control signals 940 may be provided to the clock generator block 950, which generates an exposure time control signal 960 and a memory address signal 970. The said signals are distributed to every pixel in the pixel array 920. A row address signal 980 is provided to the row address block 990. The said block decodes the row address signal 980 into a suitable input for a pixel driver circuits block 9100, selecting a desired row for the readout. The pixels are driven by the pixel driver circuits block 9100 providing the row select signal 9110 to every pixel row. The outputs of the pixels are organized in columns 9120, which may be implemented as buses composed of a plurality of parallel wires. The columns 9120 are input to the column readout and processing block 9130. The said block is connected to the to the sensor output circuits block 9140 providing the sensor output signal 9150 containing the frame data. Figure 10 shows a timing diagram for the ultra-high-framerate and continuous-readout image sensor 910. Memory bank address trace 1010 selects the memory bank 160 in all pixels 930 for capturing the frame data. Pulses shown on the exposure time control trace 1020 are used to set the desired exposure time and control shifting of the frame data between memory elements 170 inside the pixels 930. A pulse is given on row 1 select trace 1030, row 2 select trace 1040, row 3 select trace 1050 and row L select trace 1060, in order to select a given row of pixels for the readout. While each of the said traces is equal to the logic high, the photon counts from all memory elements 170 in the currently selected memory bank 160 in all pixels 930 in the selected row are settled on the columns 9120. The photon counts appear on column 1 trace 1070, column 2 trace 1080, column 3 trace 1090, and column K trace 10100. The row select pulse is non-overlapping between adjacent pixel rows, ensuring correct pixel counts are settled on the columns 9120 and no excess power is used while two different readout and pixel output driving circuits blocks 1130 are driving the same column 9120 at the same time.

Claims

1. A memory circuit for a high-framerate continuous-readout pixel comprising:two memory banks operated in an interleaved way, while one is receiving light intensity information and the other is being read out;a demultiplexer directing the light intensity data to either odd memory bank or even memory bank according to a memory bank address signal;a memory address decoder choosing said memory bank for the read out; anda readout and pixel output driving circuits block driving the output terminals of the memory circuit based on a row select signal;wherein the light intensity data is input to the demultiplexer, the outputs of said demultiplexer are connected to the inputs of said memory banks, and the outputs of said memory banks are connected to said readout and pixel output driving circuits block.

2. A memory circuit for a high-framerate continuous-readout pixel as described in claim 1, wherein the memory bank is implemented as a shift register circuit.

3. A memory circuit for a high-framerate continuous-readout pixel as described in claim 1, wherein the memory element is implemented as a photon counting circuit.

4. A memory circuit for a high-framerate continuous-readout pixel as described in claim 1, wherein the memory element is implemented as a plurality of static random access memory cells, and suitable memory supporting circuits for read and write operations.

5. A memory circuit for a high-framerate continuous-readout pixel as described in claim 1, wherein the memory element is implemented as a plurality of dynamic random access memory cells, and suitable memory supporting circuits for read and write operations.

6. A memory circuit for a high-framerate continuous-readout pixel as described in claim 1, wherein the memory element is implemented as any suitable digital or analogue memory circuit.

7. A method of operating the memory circuit for a high-framerate continuous-readout pixel comprising:setting a demultiplexer to direct the light intensity data to the odd memory bank;writing the light intensity data to the odd memory bank for a number of N frames;simultaneously reading out a previously stored series of N frames from the even memory bank to the outside of the memory circuit;setting a demultiplexer to direct the light intensity data to the even memory bank once the writing of the N frames to the odd memory bank is complete;writing the light intensity data to the even memory bank for a number of N frames; simultaneously reading out a previously stored series of N frames from the odd memory bank to the outside of the memory circuit; andrepeating said steps as long as needed for the desired number of frames to be recorded.

8. A method of operating the memory circuit for a high-framerate continuous-readout pixel as described in claim 7, applied in order to achieve the gapless exposure to the light, and applicable to any gapless exposure image sensor, not limited to the high-framerate image sensors and cameras.

9. A high-framerate continuous-readout pixel comprising:a sensing device converting the input light intensity into an electrical signal;a frontend circuits biasing and reading out the sensing device; anda memory circuit comprising:two memory banks working in an interleaved way, while one is receiving light intensity information and the other is being read out;a demultiplexer directing the light intensity data to either odd memory bank or even memory bank according to the memory bank address signal;a memory address decoder choosing said memory bank for the read out; anda readout and pixel output driving circuits block driving the output terminals of the memory circuit based on the row select signal;wherein the light intensity data is input to the demultiplexer, the outputs of said demultiplexer are connected to the inputs of said memory banks, and the outputs of said memory banks are connected to said readout and pixel output driving circuits block;wherein the output of said sensing device is input to the frontend circuits, and the output of said frontend circuit is connected to the inputs of said memory circuits.

10. A high-framerate continuous-readout image sensor comprising:a pixel array comprising a plurality of pixels arranged in a two-dimensional shape comprising rows and columns, each pixel comprising:a sensing device converting the input light intensity into an electrical signal;a frontend circuits biasing and reading out the sensing device; anda memory circuit comprising;two memory banks working in an interleaved way, while one is receiving light intensity information and the other is being read out;a demultiplexer directing the light intensity data to either odd memory bank or even memory bank according to the memory bank address signal;a memory address decoder choosing said memory bank for the read out; and a readout and pixel output driving circuits block driving the output terminals of the memory circuit based on the row select signal;wherein the light intensity data is input to the demultiplexer, the outputs of said demultiplexer are connected to the inputs of said memory banks, and the outputs of said memory banks are connected to said readout and pixel output driving circuits block;wherein the output of said sensing device is input to the frontend circuits, and the output of said frontend circuit is connected to the inputs of said memory circuits.