Not yet published

Abstract

Provided are a display substrate, a display panel, and a display device. The display substrate comprises a plurality of sub-pixels and a plurality of signal lines located on a substrate, wherein the plurality of sub-pixels are arranged in an array in a first direction and a second direction, and at least one sub-pixel comprises a light-emitting device and a pixel drive circuit; and the plurality of signal lines comprise a first power supply signal line. The display substrate further comprises: a light-shielding layer, a first semiconductor layer, and a first conductive layer which are away from the substrate in sequence. The pixel drive circuit comprises a third transistor comprising a third active layer located in the first semiconductor layer and a third gate located in the first conductive layer, wherein the third active layer comprises a third channel region, and the orthographic projections of the third gate and the third channel region on the substrate at least partially overlap with each other. The first power supply signal line comprises a first sub-power supply signal line located in the light-shielding layer, and the orthographic projection of the first sub-power supply signal line on the substrate covers the orthographic projection of the third channel region on the substrate.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] With the development of display technology, display products are showing a trend of high integration and low cost. Currently, LTPO (Low Temperature Poly-Oxide) pixel driver circuits are commonly used in OLED display products. The low leakage of indium gallium zinc oxide (IGZO) TFTs can achieve low-frequency display of display products and reduce power consumption. However, compared with traditional LTPS (Low Temperature Poly-Silicon) pixel driver circuits, LTPO pixel driver circuits require the addition of multiple coating film layers. The increase in coating film layers requires the corresponding addition of multiple metal mask plates, resulting in an increase in the cost of display products. Moreover, as the size of display products decreases, the wiring space for pixel driver circuits of high-pixel display products becomes smaller. The increase in the number of film layers during the preparation of pixel driver circuits will also lead to a decrease in the yield of display products.

[0003] One of the important research topics for R&D personnel is how to optimize the layout space of the pixel driving circuit of display products to improve the yield of display products, and reduce unnecessary film layers to save metal mask costs.

[0004] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0005] Summary of the Invention

[0006] In one aspect, a display substrate is provided, wherein the display substrate comprises: a base substrate; a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels being arranged in an array on the base substrate along a first direction and a second direction, at least one sub-pixel comprising a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, the first direction and the second direction intersecting; a plurality of signal lines arranged on the base substrate, the plurality of signal lines comprising a first power signal line, the first power signal line being used to provide a first power signal to the pixel driving circuit, wherein the display substrate further comprises: a light-shielding layer located on the base substrate; a first semiconductor layer located on a side of the light-shielding layer away from the base substrate. ; and a first conductive layer located on a side of the first semiconductor layer away from the substrate; the pixel driving circuit includes a third transistor, the third transistor includes a third active layer and a third gate, the third active layer is located in the first semiconductor layer, the third gate is located in the first conductive layer, the third active layer includes a third channel region, the orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projection of the third channel region on the substrate; and the first power signal line includes a first sub-power signal line located in the light-shielding layer, the orthographic projection of the first sub-voltage signal line on the substrate covers the orthographic projection of the third channel region on the substrate.

[0007] According to some exemplary embodiments, the first power signal line further includes a second sub-power signal line located in the light shielding layer, a main portion of the first sub-power signal line extends along a first direction, and the second sub-power signal line extends along a second direction.

[0008] According to some exemplary embodiments, the display substrate includes m first sub-power signal lines and n second sub-power signal lines located in the light-shielding layer, and each of the m first sub-power signal lines crosses with n second sub-power signal lines, so that the portion of the first power signal line located in the light-shielding layer has a grid structure.

[0009] According to some exemplary embodiments, the display substrate further includes: a second conductive layer located on a side of the first conductive layer away from the base substrate; a planarization layer located on a side of the second conductive layer away from the base substrate; and a first electrode layer located on a side of the planarization layer away from the base substrate; the light-emitting element further includes a first electrode, which is located in the first electrode layer; the planarization layer includes a first surface facing the second conductive layer and a second surface facing the first electrode layer, the first surface contacts at least a portion of the second conductive layer, and the second surface contacts at least a portion of the first electrode layer.

[0010] For example, the third transistor further includes a third source and a third drain, and the third source and the third drain are located in the second conductive layer.

[0011] According to some exemplary embodiments, the pixel driving circuit further includes a storage capacitor, the storage capacitor including a first capacitor plate and a second capacitor plate; a portion of the first capacitor plate overlapping the third active layer serves as the third gate; and a portion of the first power signal line located in the light shielding layer is electrically connected to the second capacitor plate. For example, the portion of the first power signal line located in the light shielding layer is electrically connected to the second capacitor plate within the display area.

[0012] According to some exemplary embodiments, the display substrate further includes: a second conductive layer located on a side of the first conductive layer away from the base substrate; the third transistor further includes a third source and a third drain, and the third source and the third drain are located in the second conductive layer; the first power signal line further includes a third sub-power signal line located in the second conductive layer.

[0013] According to some exemplary embodiments, an orthographic projection of the third sub-power signal line on the base substrate at least partially overlaps with an orthographic projection of the second sub-power signal line on the base substrate.

[0014] According to some exemplary embodiments, the display substrate includes k third sub-power signal lines located in the second conductive layer; and the number n of the second sub-power signal lines is more than twice the number k of the third sub-power signal lines.

[0015] According to some exemplary embodiments, the third sub-power signal line is electrically connected to the second sub-power signal line through a first via.

[0016] According to some exemplary embodiments, the display substrate further includes: a second conductive layer located on a side of the first conductive layer away from the base substrate; the third transistor further includes a third source and a third drain, and the third source and the third drain are located in the second conductive layer; the first power signal line further includes a first conductive transition portion located in the second conductive layer, and the first conductive transition portion is electrically connected to the second sub-power signal line through a first via.

[0017] According to some exemplary embodiments, an orthographic projection of the first conductive transition portion on the base substrate at least partially overlaps with an orthographic projection of the second sub-power signal line on the base substrate.

[0018] According to some exemplary embodiments, the display substrate further includes: a second semiconductor layer located on a side of the first semiconductor layer away from the base substrate; the pixel driving circuit further includes a second transistor, the second transistor includes a second active layer, and the second active layer is located in the second semiconductor layer; the first semiconductor layer includes single crystal silicon, amorphous silicon or polycrystalline silicon semiconductor material, and the second semiconductor layer includes an oxide semiconductor material.

[0019] According to some exemplary embodiments, the second transistor includes a second gate, the second gate includes a first sub-gate and a second sub-gate, the layer where the first sub-gate is located is located on the side of the second semiconductor layer close to the base substrate, the layer where the second sub-gate is located is located on the side of the second semiconductor layer away from the base substrate, the orthographic projection of the first sub-gate on the base substrate at least partially overlaps with the orthographic projection of the second active layer on the base substrate, and the orthographic projection of the second sub-gate on the base substrate at least partially overlaps with the orthographic projection of the second active layer on the base substrate.

[0020] According to some exemplary embodiments, the display substrate further includes: a third conductive layer located between the first semiconductor layer and the second semiconductor layer; and a fourth conductive layer located on a side of the second semiconductor layer away from the base substrate; the first sub-gate is located in the third conductive layer, and the second sub-gate is located in the fourth conductive layer.

[0021] According to some exemplary embodiments, the display substrate further includes: a third conductive layer located on a side of the second semiconductor layer away from the base substrate; the first sub-gate is located in the first conductive layer, and the second sub-gate is located in the third conductive layer.

[0022] According to some exemplary embodiments, the display substrate further includes: a fourth conductive layer located on a side of the second semiconductor layer away from the base substrate; the first sub-gate is located in the first conductive layer, and the second sub-gate is located in the fourth conductive layer.

[0023] According to some exemplary embodiments, at least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the third conductive layer.

[0024] According to some exemplary embodiments, at least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the fourth conductive layer.

[0025] According to some exemplary embodiments, a portion of the third sub-power signal line is electrically connected to the second sub-power signal line through a first via, and another portion of the third sub-power signal line is electrically connected to at least a portion of the second capacitor plate through a second via.

[0026] According to some exemplary embodiments, a portion of the first conductive transition portion is electrically connected to the second sub-power signal line through a first via, and another portion of the first conductive transition portion is electrically connected to at least a portion of the second capacitor plate through a second via.

[0027] According to some exemplary embodiments, the first conductive layer is located on a side of the second semiconductor layer away from the substrate; the second transistor and the third transistor both have a top gate structure; the second transistor includes a second gate, and the second gate and the third gate are both located in the first conductive layer, and the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate.

[0028] According to some exemplary embodiments, the display substrate further includes: a second conductive layer located on a side of the first conductive layer away from the base substrate; at least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the second conductive layer.

[0029] According to some exemplary embodiments, the third sub-power signal line and at least a portion of the second capacitor plate, both located in the second conductive layer, are connected, and the third sub-power signal line is electrically connected to the second sub-power signal line through a first via.

[0030] According to some exemplary embodiments, the second capacitor plate includes a first sub-capacitor plate and a second sub-capacitor plate, the first sub-capacitor plate is located in the second conductive layer, and the second sub-capacitor plate is located in the light-shielding layer; the orthographic projection of each of the first sub-capacitor plate and the second sub-capacitor plate on the base substrate at least partially overlaps with the orthographic projection of the first capacitor plate on the base substrate.

[0031] According to some exemplary embodiments, the resistivity of a material of the light shielding layer is lower than the resistivity of a material of the second conductive layer.

[0032] According to some exemplary embodiments, the light shielding layer is made of copper or aluminum.

[0033] According to some exemplary embodiments, in the light-shielding layer, a first portion of the first power signal line providing a first power signal line to a pixel driving circuit of a sub-pixel in the j-th column and a second portion of the first power signal line providing a first power signal line to a pixel driving circuit of a sub-pixel in the j+1-th column are symmetrical with respect to a first imaginary straight line, wherein the first imaginary straight line is a straight line extending along the second direction.

[0034] According to some exemplary embodiments, the multiple signal lines further include a first initialization signal line, a second initialization signal line, a reset signal line, a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting control signal line and a data signal line, the first initialization signal line, the second initialization signal line, the reset signal line, the first scan signal line, the second scan signal line, the third scan signal line and the light-emitting control signal line extend along a first direction, and the data signal line extends along a second direction.

[0035] According to some exemplary embodiments, the pixel driving circuit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the first transistor includes a first gate, a first source, and a first drain, the first gate being electrically connected to the reset signal line, and one of the first source and the first drain being electrically connected to the first initialization signal line; the second gate being electrically connected to the third scan signal line; the fourth transistor includes a fourth gate, a fourth source, and a fourth drain, the fourth gate being electrically connected to the first scan signal line, and one of the fourth source and the fourth drain being electrically connected to the data signal line; the fifth transistor includes a fifth gate, a fifth source, and a fifth drain, the fifth gate being electrically connected to the light emitting control signal line, and one of the fifth source and the fifth drain being electrically connected to the first power supply signal line; the sixth transistor includes a sixth gate, a sixth source, and a sixth drain, the sixth gate being electrically connected to the first scan signal line, and the sixth source and the sixth drain being electrically connected to the first power supply signal line. The gate is electrically connected to the light-emitting control signal line; the seventh transistor includes a seventh gate, a seventh source and a seventh drain, the seventh gate is electrically connected to the second scanning signal line, and one of the seventh source and the seventh drain is electrically connected to the second initialization signal line; and the second source and the second drain, the third gate and the first capacitor plate are electrically connected to each other, the third source and the third drain, the other of the fourth source and the fourth drain, and the fifth source and the other of the fifth drain are electrically connected to each other, the first source and the other of the first drain, the second source and the second drain, the other of the third source and the third drain, and one of the sixth source and the sixth drain are electrically connected to each other, the sixth source and the other of the sixth drain, and the seventh source and the other of the seventh drain are electrically connected to each other.

[0036] According to some exemplary embodiments, the reset signal line, the first scan signal line, the second scan signal line, the light emitting control signal line, and the second initialization signal line are located in the first conductive layer; and the first initialization signal line is located in the third conductive layer.

[0037] According to some exemplary embodiments, the reset signal line, the first scan signal line, the second scan signal line, the light emitting control signal line, and the second initialization signal line are located in the first conductive layer; and the first initialization signal line is located in the fourth conductive layer.

[0038] According to some exemplary embodiments, the first initialization signal line, the reset signal line, the first scan signal line, the second scan signal line, the third scan signal line, the light emission control signal line, and the second initialization signal line are all located in the first conductive layer.

[0039] On the other hand, a display substrate is provided, wherein the display substrate includes: a base substrate; a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged in an array on the base substrate along a first direction and a second direction, at least one sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; a plurality of signal lines arranged on the base substrate, the plurality of signal lines including a first power signal line, the first power signal line being used to provide a first power signal to the pixel driving circuit, wherein the display substrate also includes: a light-shielding layer located on the base substrate; a first semiconductor layer located on a side of the light-shielding layer away from the base substrate; and a first conductive layer located on a side of the first semiconductor layer away from the base substrate; the first power signal line also includes a first sub-power signal line and a second sub-power signal line located in the light-shielding layer, the main part of the first sub-power signal line extends along the first direction, and the second sub-power signal line extends along the second direction, the first sub-power signal line and the second sub-power signal line are electrically connected to each other for transmitting the first power signal.

[0040] In yet another aspect, a display substrate is provided, wherein the display substrate comprises: a base substrate; and a plurality of sub-pixels located on the base substrate, wherein the plurality of sub-pixels are arranged in an array on the base substrate along a first direction and a second direction, at least one sub-pixel comprises a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; wherein the display substrate further comprises: a first semiconductor layer located on the substrate; a first conductive layer located on a side of the first semiconductor layer away from the substrate; a second semiconductor layer located on a side of the first conductive layer away from the substrate; and a third conductive layer located on a side of the second semiconductor layer away from the substrate; the pixel driving circuit includes a second transistor and a third transistor, the second transistor and the third transistor both having a top gate structure; the third transistor includes a third active layer and a third gate, the third active layer is located in the first semiconductor layer, the third gate is located in the first conductive layer, the third active layer includes a third channel region, and the orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projection of the third channel region on the substrate; and the second transistor includes a second active layer and a second gate, the second active layer is located in the second semiconductor layer, the second gate is located in the third conductive layer, the second active layer includes a second channel region, and the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projection of the second channel region on the substrate.

[0041] According to some exemplary embodiments, the display substrate further includes a light-shielding layer located on a side of the first semiconductor layer close to the base substrate; and the display substrate includes a first light-shielding portion and a second light-shielding portion located in the light-shielding layer, the orthographic projection of the first light-shielding portion on the base substrate at least partially overlaps with the orthographic projection of the third channel region on the base substrate, and the orthographic projection of the second light-shielding portion on the base substrate at least partially overlaps with the orthographic projection of the second channel region on the base substrate.

[0042] According to some exemplary embodiments, the first light-shielding portion includes a first light-shielding sub-portion extending along a first direction and a second light-shielding sub-portion extending along a second direction, and the first light-shielding sub-portion and the second light-shielding sub-portion are connected so that the first light-shielding portion forms an L-shaped structure; and / or the second light-shielding portion extends from a portion of the first light-shielding sub-portion along the second direction.

[0043] On the other hand, a display substrate is provided, wherein the display substrate includes: a base substrate; and a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged in an array on the base substrate along a first direction and a second direction, at least one sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; wherein the display substrate also includes: a first semiconductor layer located on the base substrate; a first conductive layer located on a side of the first semiconductor layer away from the base substrate; a second semiconductor layer located on a side of the first conductive layer away from the base substrate; a third conductive layer located on a side of the second semiconductor layer away from the base substrate; and a fourth conductive layer located on a side of the third conductive layer away from the base substrate; the pixel driving circuit includes a second transistor and a third transistor, the second transistor having a dual-gate structure, the first transistor having a dual-gate structure, and the second transistor having a dual-gate structure. The three transistors have a top gate structure; the third transistor includes a third active layer and a third gate, the third active layer is located in the first semiconductor layer, the third gate is located in the first conductive layer, the third active layer includes a third channel region, and the orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projection of the third channel region on the substrate; and the second transistor includes a second active layer and a second gate, the second gate includes a first sub-gate and a second sub-gate, the first sub-gate is located in the first conductive layer, the second sub-gate is located in the third conductive layer or the fourth conductive layer, the orthographic projection of the first sub-gate on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the orthographic projection of the second sub-gate on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate.

[0044] In yet another aspect, a display panel is provided, comprising the display substrate as described in any one of the above items.

[0045] In yet another aspect, a display device is provided, comprising the display substrate as described in any one of the above items or the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0047] FIG1 is a schematic plan view of a display substrate according to some embodiments of the present disclosure;

[0048] FIG2 is a schematic diagram of a sub-pixel structure according to some embodiments of the present disclosure;

[0049] FIG3 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0050] FIG4 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0051] 5 is a plan view schematically illustrating a pixel driving circuit for a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure;

[0052] FIG6 is a plan view of a light shielding layer in the pixel driving circuit of FIG5 ;

[0053] FIG7 is a schematic plan view of the first semiconductor layer in the pixel driving circuit of FIG5 ;

[0054] FIG8 is a plan view of a combined film layer of a light shielding layer and a first semiconductor layer in the pixel driving circuit of FIG5 ;

[0055] FIG9 is a plan view of a first conductive layer in the pixel driving circuit of FIG5 ;

[0056] 10 is a plan view of a combined film layer of a light shielding layer, a first semiconductor layer, and a first conductive layer in the pixel driving circuit of FIG5 ;

[0057] FIG11 is a plan view of a third conductive layer in the pixel driving circuit of FIG5 ;

[0058] 12 is a plan view of a combined film layer of a light shielding layer, a first semiconductor layer, a first conductive layer, and a third conductive layer in the pixel driving circuit of FIG5 ;

[0059] 13 is a plan view of a combined film layer of a third conductive layer, a second semiconductor layer, and a fourth conductive layer in the pixel driving circuit of FIG5 ;

[0060] FIG14 is a plan view of a second conductive layer in the pixel driving circuit of FIG5 ;

[0061] 15 is a plan view of a combined film layer of a third conductive layer, a second semiconductor layer, a fourth conductive layer, and a second conductive layer in the pixel driving circuit of FIG5 ;

[0062] FIG16 is a partial cross-sectional schematic diagram of a display substrate taken along line AA′ in FIG5 according to some embodiments of the present disclosure;

[0063] FIG. 17 is a partial cross-sectional schematic diagram of a display substrate taken along line BB′ in FIG. 5 according to some embodiments of the present disclosure.

[0064] FIG18 is a plan view schematically illustrating a pixel driving circuit for a plurality of sub-pixels in a display substrate according to other embodiments of the present disclosure;

[0065] FIG19 is a plan view of a combined film layer of a first conductive layer, a second semiconductor layer, and a third conductive layer in the pixel driving circuit of FIG18 ;

[0066] FIG20 is a plan view of a second conductive layer in the pixel driving circuit of FIG18 ;

[0067] FIG21 is a partial cross-sectional schematic diagram taken along line CC′ in FIG18 ;

[0068] FIG22 is a plan view schematically illustrating a pixel driving circuit for a plurality of sub-pixels in a display substrate according to other embodiments of the present disclosure;

[0069] FIG23 is a plan view of a combined film layer of a first conductive layer, a second semiconductor layer, and a fourth conductive layer in the pixel driving circuit of FIG22 ;

[0070] FIG24 is a plan view schematically showing the second conductive layer in the pixel driving circuit of FIG22 ;

[0071] FIG25 is a partial cross-sectional schematic diagram taken along line DD′ in FIG22 ;

[0072] FIG26 is a plan view schematically illustrating a pixel driving circuit for a plurality of sub-pixels in a display substrate according to other embodiments of the present disclosure;

[0073] FIG27 is a plan view of a combined film layer of a light shielding layer, a first semiconductor layer, and a first conductive layer in the pixel driving circuit of FIG26 ;

[0074] FIG28 is a plan view of a combined film layer of a first conductive layer and a second semiconductor layer in the pixel driving circuit of FIG26 ;

[0075] FIG29 is a plan view schematically showing the second conductive layer in the pixel driving circuit of FIG26 ;

[0076] FIG30 is a partial cross-sectional schematic diagram taken along line EE' in FIG26;

[0077] FIG31A is a partial cross-sectional schematic diagram taken along line FF′ in FIG26 ;

[0078] FIG31B is a partial cross-sectional schematic diagram of a display substrate taken along line FF′ in FIG26 according to some other embodiments of the present disclosure;

[0079] FIG32 is a plan view schematically illustrating a pixel driving circuit for a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure;

[0080] FIG33 is a plan view schematically showing a light shielding layer in the pixel driving circuit of FIG32 ;

[0081] FIG34 is a plan view of a combined film layer of a light shielding layer and a first semiconductor layer in the pixel driving circuit of FIG32 ;

[0082] FIG35 is a plan view of a combined film layer of a light shielding layer, a first semiconductor layer, a first conductive layer, and a second semiconductor layer in the pixel driving circuit of FIG32 ;

[0083] FIG36 is a plan view of a combined film layer of a light shielding layer, a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a third conductive layer in the pixel driving circuit of FIG32 ;

[0084] FIG37 is a plan view schematically showing the second conductive layer in the pixel driving circuit of FIG32 ;

[0085] FIG38 is a plan view of a composite film layer of a light shielding layer, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a third conductive layer, and a second conductive layer in the pixel driving circuit of FIG32 ;

[0086] FIG39 is a partial cross-sectional schematic diagram taken along line GG′ in FIG32 ;

[0087] FIG40 is a partial cross-sectional schematic diagram taken along line HH′ in FIG32 ;

[0088] FIG41 is a plan view schematically illustrating a pixel driving circuit for a plurality of sub-pixels in a display substrate according to other embodiments of the present disclosure;

[0089] FIG42 is a partial cross-sectional schematic diagram taken along line II′ in FIG41 ;

[0090] FIG43 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure;

[0091] FIG44 is a schematic structural diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0092] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0093] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0094] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0095] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0096] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0097] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0098] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0099] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0100] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0101] The embodiments of the present disclosure provide at least one display substrate, wherein the display substrate comprises: a base substrate; a plurality of sub-pixels located on the base substrate, wherein the plurality of sub-pixels are arranged in an array on the base substrate along a first direction and a second direction, at least one sub-pixel comprises a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; a plurality of signal lines arranged on the base substrate, wherein the plurality of signal lines comprise a first power signal line, and the first power signal line is used to provide a first power signal to the pixel driving circuit, wherein the display substrate further comprises: a light-shielding layer located on the base substrate; a first semiconductor layer located on a side of the light-shielding layer away from the base substrate; The pixel driving circuit includes a third transistor, the third transistor including a third active layer and a third gate, the third active layer being located in the first semiconductor layer, the third gate being located in the first conductive layer, the third active layer including a third channel region, the orthographic projection of the third gate on the substrate at least partially overlapping the orthographic projection of the third channel region on the substrate; and the first power signal line including a first sub-power signal line located in the light shielding layer, the orthographic projection of the first sub-voltage signal line on the substrate overlapping the orthographic projection of the third channel region on the substrate. By arranging the first sub-power signal line in the light shielding layer, the first sub-power signal line can be used as both a light shielding portion and a power signal line to transmit a power signal, thereby eliminating a conductive layer used as a power signal line and a planarization layer, thereby saving costs. Furthermore, the light shielding portion can be made of a low-resistance material, thereby ensuring a low voltage drop across the power signal line in the light shielding portion, facilitating power signal transmission.

[0102] FIG. 1 is a schematic plan view of a display substrate according to some embodiments of the present disclosure.

[0103] 1 , a display substrate 400 according to an embodiment of the present disclosure may include a base substrate 10, a pixel unit PX disposed on the base substrate 10, a driving unit DRU disposed on the base substrate 10, and a trace PL electrically connecting the pixel unit PX to the driving unit DRU, wherein the driving unit DRU is used to drive the pixel unit PX.

[0104] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where a pixel unit PX displaying an image is provided. The non-display area NA is an area where no pixel unit PX is provided, that is, an area where no image is displayed. A driving unit DRU for driving the pixel unit PX and some traces PL connecting the pixel unit PX to the driving unit DRU may be provided in the non-display area NA. The non-display area NA corresponds to a frame in the final display device, and the width of the frame may be determined based on the width of the non-display area NA.

[0105] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0106] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0107] The pixel unit PX is provided in the display area AA. The pixel unit PX is the smallest unit for displaying an image and may be provided in plurality. For example, the pixel unit PX may include a light emitting device that emits white light and / or colored light.

[0108] The pixel units PX may be provided in a plurality and arranged in a matrix along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel units PX, and the pixel units PX may be arranged in various forms. For example, the pixel units PX may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0109] A pixel unit PX may include multiple sub-pixels SP. For example, a pixel unit PX may include three sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For another example, a pixel unit PX may include four sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, the third sub-pixel SP3 may be a blue sub-pixel, and the fourth sub-pixel may be a white sub-pixel.

[0110] Each sub-pixel SP may include a light-emitting element L and a pixel driving circuit 200 for driving the light-emitting element. The light-emitting element may include a current-driven element. Further, the light-emitting element L may be a current-driven light-emitting diode, such as an organic light-emitting diode (OLED). Exemplarily, the first electrode and the second electrode of the light-emitting element L are the anode and cathode of the light-emitting diode, respectively.

[0111] FIG2 is a schematic structural diagram of a sub-pixel according to some embodiments of the present disclosure.

[0112] 2 , each sub-pixel SP includes a light emitting element L and a pixel circuit 200 coupled to the light emitting element L. The pixel circuit 200 is configured to provide a driving current to the light emitting element L to drive the light emitting element L to operate (ie, emit light).

[0113] For example, with continued reference to FIG. 2 , the first electrode of the light-emitting element L is coupled to the pixel circuit 200, and the second electrode of the light-emitting element L is coupled to the second voltage terminal VSS. The second voltage terminal VSS is configured to transmit a second voltage. The second voltage can be a DC reference voltage, for example, the second voltage Vss is -3V. Alternatively, the second voltage Vss is 0V, i.e., the second voltage terminal VSS is grounded. The second voltage terminal VSS only needs to provide 0V or a negative voltage to the second electrode of the light-emitting element L.

[0114] Figure 3 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure. Figure 4 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0115] It should be noted that in the following description, the structure of the pixel circuit is described in detail using the 7T1C pixel circuit as an example. However, the embodiments of the present disclosure are not limited to the 7T1C pixel circuit. Unless there is a conflict, other known pixel circuit structures can be applied to the embodiments of the present disclosure.

[0116] As shown in FIG3 , the pixel circuit includes: a first light emission control subcircuit 201 , a second light emission control subcircuit 207 , a first initialization subcircuit 203 , a second initialization subcircuit 208 , a data writing subcircuit 202 , a driving subcircuit 204 , a compensation subcircuit 206 and a storage subcircuit 205 .

[0117] For example, with reference to FIG3 , a pixel circuit according to an embodiment of the present disclosure is used to drive a light-emitting element L. The pixel circuit includes a second initialization sub-circuit 208 for resetting the voltage of the first electrode of the light-emitting element L during a reset phase. The second initialization sub-circuit 208 is electrically connected to the second scan signal line GL2, the second initialization signal line Vinit2, and the first electrode of the light-emitting element L. The second initialization sub-circuit 208 is controlled by a second scan signal provided by the second scan signal line GL2 to control the connection between the second initialization signal line Vinit2 and the first electrode of the light-emitting element L, thereby initializing the potential of the first electrode of the light-emitting element L, i.e., lowering the potential of the first electrode of the light-emitting element L.

[0118] During the reset stage, the voltage of the first electrode of the light-emitting element L is cleared by the second initialization sub-circuit 208, so that the potential of the first electrode of the light-emitting element L is initialized, thereby preventing the light-emitting element L from emitting light in a dark state due to the influence of the leakage current of the second light-emitting control circuit 207, thereby improving the display quality of the display device having the pixel circuit.

[0119] The pixel circuit further includes a first initialization sub-circuit 203 and a compensation sub-circuit 206, which can be used to reset the voltages of the third node N3 and the first node N1 during a reset phase. The compensation sub-circuit 206 is electrically connected to the third scan signal line GL3, the first node N1, and the third node N3, respectively, and is used to control the connection between the first node N1 and the third node N3 under the control of a third scan signal provided by the third scan signal line GL3. The first initialization sub-circuit 203 is electrically connected to the reset signal line R1, the first initialization signal line Vinit1, and the third node N3, respectively, and is used to control the connection between the first initialization signal line Vinit1 and the third node N3 under the control of a reset signal provided by the reset signal line R1, thereby resetting the voltage of the third node N3. Since the first node N1 and the third node N3 are now connected, the voltage of the first node N1 is also reset, i.e., the potential of the first node is lowered.

[0120] 3 , the pixel circuit further includes a first light emitting control subcircuit 201 for performing voltage compensation on the first node N1 during the compensation phase. The first light emitting control subcircuit 201 is electrically connected to the first power signal line VDD, the light emitting control signal line EM, and the second node N2, respectively, and is configured to control the connection between the first power signal line VDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control signal line EM, thereby writing the first voltage Vdd provided by the first power signal line VDD into the second node N2. At this time, V N2 =Vdd. In this stage, the compensation sub-circuit 206 controls the connection between the first node N1 and the third node N3 in response to the third scan signal received at the third scan signal line GL3, thereby transmitting the voltage Vdd of the second node N2 and the threshold voltage Vth of the driving sub-circuit 204 to the first node N1. Therefore, the voltage V N1 Equal to Vdd+Vth. Exemplarily, the first voltage Vdd from the first voltage terminal VDD is a DC voltage, for example, a DC high-level voltage, for example, the first voltage Vdd is 5V.

[0121] The pixel circuit can transmit the first voltage from the first power signal line VDD and the threshold voltage of the driving sub-circuit to the first node N1 in response to the light-emitting control signal and the third scanning signal, perform voltage compensation on the first node N1, and improve the driving effect of the pixel circuit on the light-emitting element L.

[0122] In FIG3 , the node labeled N1 is a first node electrically connected to the control terminal of the driver sub-circuit 204 , the node labeled N2 is a second node electrically connected to the first terminal of the driver sub-circuit 204 , and the node labeled N3 is a third node electrically connected to the second terminal of the driver sub-circuit 204 .

[0123] 3 , the pixel circuit further includes a data writing sub-circuit 202 for writing the data signal provided by the data signal line Data into the second node N2 during the data writing phase. The data writing sub-circuit 202 is electrically connected to the data signal line Data, the first scanning signal line GL1, and the second node N2, respectively. During the data writing phase, under the control of the first scanning signal provided by the first scanning signal line GL1, the data signal line Data is controlled to be connected to the second node N2, thereby writing the data signal V provided by the data signal line Data into the second node N2. data Write to the second node N2.

[0124] It should be understood that in the pixel circuit provided in the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components. In some embodiments, these nodes represent the junction points of related couplings (i.e., electrical connections) in the equivalent circuit diagram of the pixel circuit. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0125] For example, the light emitting element L is an OLED, and the threshold voltage of the light emitting element L is the threshold voltage V oled-th .

[0126] 3 and 4 , the pixel circuit further includes a storage sub-circuit 205 configured to maintain the potential of the first node N1. The storage sub-circuit 205 may include a storage capacitor C1, which may include a first capacitor plate C1a and a second capacitor plate C1b. The first capacitor plate C1a of the storage capacitor C1 is electrically connected to the first node N1, and the second capacitor plate C1b of the storage capacitor C1 is electrically connected to the first power signal line VDD.

[0127] When the voltage difference between the first power signal line VDD and the first node N1 is greater than the threshold voltage Vth of the driver sub-circuit 204, the driver sub-circuit 204 responds to the voltage V N1 It is turned on and generates a driving current I. The driving circuit satisfies the following formula: I=1 / 2·K·(Vgs-Vth) 2

[0128] Wherein, K is a fixed constant related to the process parameters and geometric dimensions of the driver sub-circuit 204. Vgs is the gate-source voltage difference of the driver transistor in the driver sub-circuit 204.

[0129] Continuing with reference to FIG3 , the pixel circuit further includes a second light-emitting control subcircuit 208, which is configured to output the driving current I transmitted to the third node N3 to the light-emitting element L in response to the light-emitting control signal received at the light-emitting control signal EM during the light-emitting phase of the image frame, so as to drive the light-emitting element L to emit light.

[0130] For example, in some embodiments of the present disclosure, referring to FIG4 , the first initialization subcircuit 203 includes a seventh transistor T1, the second initialization subcircuit 208 includes a first transistor T7, the first emission control subcircuit 201 includes a fifth transistor T5, the second emission control subcircuit 207 includes a sixth transistor T6, the driving subcircuit 204 includes a third transistor T3, the compensation subcircuit 206 includes a second transistor T2, the data writing subcircuit 202 includes a fourth transistor T4, and the storage subcircuit 205 includes a first capacitor C1. The light-emitting element L may be an organic light-emitting diode.

[0131] Each transistor includes a control electrode, i.e., a gate electrode; a first electrode, i.e., a source electrode or a drain electrode; and a second electrode, i.e., the other of the source electrode or the drain electrode. For example, the first transistor includes a first gate electrode, a first source electrode, and a first drain electrode; the second transistor includes a second gate electrode, a second source electrode, and a second drain electrode; the third transistor includes a third gate electrode, a third source electrode, and a third drain electrode; the fourth transistor includes a fourth gate electrode, a fourth source electrode, and a fourth drain electrode; the fifth transistor includes a fifth gate electrode, a fifth source electrode, and a fifth drain electrode; the sixth transistor includes a sixth gate electrode, a sixth source electrode, and a sixth drain electrode; and the seventh transistor includes a seventh gate electrode, a seventh source electrode, and a seventh drain electrode.

[0132] The first capacitor C1 may include a first capacitor plate C1a and a second capacitor plate C1b. The first capacitor plate C1a of the first capacitor C1 is electrically connected to the first node N1, that is, the first capacitor plate C1a of the first capacitor C1 is electrically connected to the third gate of the third transistor and the first electrode of the second transistor, and the second capacitor plate C1b of the first capacitor C1 is electrically connected to the first power signal line VDD and the first electrode of the fifth transistor.

[0133] A first gate of the first transistor T1 is electrically connected to a reset signal line R1, a first electrode of the first transistor T1 is electrically connected to a third node N3, and a second electrode of the first transistor T1 is electrically connected to a first initialization signal line Vinit1. For example, the first initialization signal line Vinit1 is configured to provide a first initialization signal. The first electrode of the first transistor T1 is one of the first source and the first drain of the first transistor, and the second electrode of the first transistor T1 is the other of the first source and the first drain of the first transistor.

[0134] The second gate of the second transistor T2 is electrically connected to the third scan signal line GL3, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. That is, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3 and the first capacitor plate C1a of the first capacitor C1, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the first electrode of the first transistor T1. For example, the first electrode of the second transistor T2 is one of the second source and the second drain of the second transistor, and the second electrode of the second transistor T2 is the other of the second source and the second drain of the second transistor.

[0135] The third gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the node N3. For example, the first electrode of the third transistor T3 is one of the third source and the third drain of the third transistor, and the second electrode of the third transistor T3 is the other of the third source and the third drain of the third transistor.

[0136] A fourth gate of the fourth transistor T4 is electrically connected to the first scan signal line GL1, a second electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and a first electrode of the fourth transistor T4 is electrically connected to the second node N2. For example, the first electrode of the fourth transistor T4 is one of the fourth source and the fourth drain of the fourth transistor, and the second electrode of the fourth transistor T4 is the other of the fourth source and the fourth drain of the fourth transistor.

[0137] A fifth gate of the fifth transistor T5 is electrically connected to the light-emission control signal line EM. A first electrode of the fifth transistor T5 is electrically connected to the first power signal line VDD. A second electrode of the fifth transistor T5 is electrically connected to the second node N2, that is, the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The first power signal line VDD is used to provide a high voltage Vdd. For example, the first electrode of the fifth transistor T5 is one of the fifth source and the fifth drain of the fifth transistor, and the second electrode of the fifth transistor T5 is the other of the fifth source and the fifth drain of the fifth transistor.

[0138] A sixth gate of the sixth transistor T6 is electrically connected to the light-emission control signal line EM; a first electrode of the sixth transistor T6 is electrically connected to the node N3, that is, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3 and the second electrode of the second transistor T2; and a second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting element L, which may be an anode. For example, the first electrode of the sixth transistor T6 is one of the sixth source and the sixth drain of the sixth transistor, and the second electrode of the sixth transistor T6 is the other of the sixth source and the sixth drain of the sixth transistor.

[0139] A seventh gate of the seventh transistor T7 is electrically connected to the second scan signal line GL2, a second electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal Vinit2, and a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4. That is, the first electrode of the seventh transistor T7 is electrically connected to the second electrode of the sixth transistor and the first electrode of the light-emitting element L. For example, the second initialization signal line Vinit2 is used to provide the second initialization signal. The first electrode of the seventh transistor T7 is one of the seventh source and the seventh drain of the seventh transistor, and the second electrode of the seventh transistor T7 is the other of the seventh source and the seventh drain of the seventh transistor.

[0140] That is, one of the second source and the second drain, the third gate and the first capacitor plate are respectively electrically connected to the first node N1, one of the third source and the third drain, the other of the fourth source and the fourth drain, and the other of the fifth source and the fifth drain are respectively electrically connected to the second node N2, the other of the first source and the first drain, the other of the second source and the second drain, the other of the third source and the third drain, and one of the sixth source and the sixth drain are respectively electrically connected to the third node N3, and the other of the sixth source and the sixth drain and the other of the seventh source and the seventh drain are respectively electrically connected to the fourth node N4.

[0141] The first electrode of the light emitting element L is electrically connected to the second electrode of the sixth transistor, and the second electrode of the light emitting element L is electrically connected to the second voltage terminal VSS. The second voltage terminal VSS is used to provide a low voltage Vss.

[0142] In the embodiment of the present disclosure, Vinit1 and Vinit2 may be the same or different.

[0143] In an embodiment of the present disclosure, the fifth gate of the fifth transistor T5 and the sixth gate of the sixth transistor T5 may be connected to the same light emitting control signal line.

[0144] In the embodiment of the present disclosure, the second transistor T2 may be an oxide thin film transistor, and the other transistors (e.g., the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) may be low-temperature polysilicon thin film transistors. However, the embodiment of the present disclosure is not limited thereto.

[0145] In at least one embodiment of the pixel circuit described in the present disclosure, the voltage value of Vinit1 can be greater than or equal to -6V and less than or equal to -2V. For example, the voltage value of Vinit1 can be -2V, -3V, -4V, -5V or -6V, but is not limited thereto.

[0146] The threshold voltage Vth of the transistor may be greater than or equal to -5V and less than or equal to -0.5V; for example, Vth may be -2.5V or -3V.

[0147] The voltage value of the high voltage Vdd provided by the first power signal line VDD may be greater than or equal to 3V and less than or equal to 6V. For example, the voltage value of Vdd may be 4.6V, but is not limited thereto.

[0148] The absolute value of the high voltage Vdd may be greater than 1.5 times the absolute value of Vth. For example, the absolute value of the high voltage Vdd may be 1.6 times, 1.8 times, or 2 times the absolute value of Vth.

[0149] Optionally, the voltage value of the low voltage Vss provided by the second power signal line VSS may be greater than or equal to -6V and less than or equal to -3V; for example, the voltage value of Vss may be -5V, -4V or -3V.

[0150] In at least one embodiment of the present disclosure, the voltage value of Vinit2 may be greater than or equal to -7 V and less than or equal to 0 V. For example, the voltage value of the second initialization voltage may be -6 V, -5 V, -4 V, -3 V, or -2 V, but is not limited thereto.

[0151] Optionally, the voltage difference between the voltage value of Vinit2 and the voltage value of VSS needs to be smaller than the turn-on voltage of the light-emitting element, so that when the first electrode of the light-emitting element is connected to Vinit2, the light-emitting element does not emit light.

[0152] In an embodiment of the present disclosure, the second transistor T2 included in the compensation sub-circuit can be an oxide thin film transistor, which can reduce the leakage of the control end of the driving circuit, ensure the stability of the voltage of the control end of the driving circuit, and help improve display quality, improve display uniformity, and reduce flicker.

[0153] In an embodiment of the present disclosure, the seventh transistor T7 may be controlled by a separate GOA, which is electrically connected to the second scan signal line GL2 , so that the light emitting element L may be reset at a specific frequency, for example, 240 Hz.

[0154] In the embodiments of the present disclosure, the second scan signal provided by the second scan signal line GL2 can be a high-frequency signal. By increasing the frequency of the second scan signal provided by the second scan signal line GL2, the refresh frequency of resetting the first electrode of the light-emitting element L can be increased, so that the brightness build-up time of the light-emitting element L during the refresh phase and the hold phase remains consistent. This can reduce the low-frequency component of the light-emitting hold phase, reduce visible brightness changes, improve flicker levels, and reduce load and power consumption.

[0155] It should be noted that, in the embodiments of the present disclosure, each thin film transistor T1, T2, T3, T4, T5, T6 and T7 may be a p-channel field effect transistor, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 may be an n-channel field effect transistor.

[0156] FIG5 is a planar schematic diagram of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure; FIG6 is a planar schematic diagram of a light-shielding layer in the pixel driving circuit according to FIG5; FIG7 is a planar schematic diagram of a first semiconductor layer in the pixel driving circuit according to FIG5; FIG8 is a planar schematic diagram of a combined film layer of a light-shielding layer and a first semiconductor layer in the pixel driving circuit according to FIG5; FIG9 is a planar schematic diagram of a first conductive layer in the pixel driving circuit according to FIG5; FIG10 is a planar schematic diagram of a combined film layer of a light-shielding layer, a first semiconductor layer and a first conductive layer in the pixel driving circuit according to FIG5; FIG11 is a planar schematic diagram of a third conductive layer in the pixel driving circuit according to FIG5; FIG12 is a planar schematic diagram of a pixel driving circuit according to FIG5 A planar schematic diagram of the combined film layer of the light-shielding layer, the first semiconductor layer, the first conductive layer and the third conductive layer in the driving circuit; Figure 13 is a planar schematic diagram of the combined film layer of the third conductive layer, the second semiconductor layer and the fourth conductive layer in the pixel driving circuit of Figure 5; Figure 14 is a planar schematic diagram of the second conductive layer in the pixel driving circuit of Figure 5; Figure 15 is a planar schematic diagram of the combined film layer of the third conductive layer, the second semiconductor layer, the fourth conductive layer and the second conductive layer in the pixel driving circuit of Figure 5; Figure 16 is a partial cross-sectional schematic diagram of the display substrate according to some embodiments of the present disclosure taken along the center line AA' of Figure 5; Figure 17 is a partial cross-sectional schematic diagram of the display substrate according to some embodiments of the present disclosure taken along the center line BB' of Figure 5.

[0157] For example, in an embodiment of the present disclosure, with reference to Figures 5 to 17, a display substrate 400 includes a light shielding layer 1, a first semiconductor layer 2, a first conductive layer 3, a third conductive layer 4, a second semiconductor layer 5, a fourth conductive layer 6, a second conductive layer 7, a planarization layer PLN, and a first electrode layer 100, which are sequentially arranged away from a base substrate 10. The display substrate may further include multiple insulating layers and multiple passivation layers, for example, an insulating layer GI and a passivation layer PVX, wherein the insulating layer GI includes an insulating layer GI-1 located between the first conductive layer 2 and the third conductive layer 4. In order to clearly describe the inventive aspects of the present disclosure, schematic diagrams of multiple insulating layers and multiple passivation layers are omitted from the multiple schematic diagrams of the present disclosure.

[0158] The pixel driving circuit includes a plurality of signal lines disposed on a substrate. The plurality of signal lines include a first power signal line VDD for providing a first power signal to the pixel driving circuit. The plurality of signal lines further include a first initialization signal line Vinit1, a second initialization signal line Vinit2, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, an emission control signal line EM, and a data signal line Data. The first initialization signal line Vinit1, the second initialization signal line Vinit2, the reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, and the emission control signal line EM extend along a first direction X, and the data signal line Data extends along a second direction Y. The reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the emission control signal line EM, and the second initialization signal line Vinit2 are located in the first conductive layer 3; the first initialization signal line Vinit1 is located in the third conductive layer 4. The pixel driving circuit further includes a plurality of transistors and storage capacitors, such as a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 and a storage capacitor C1 .

[0159] For example, in some embodiments of the present disclosure, with reference to FIG5 , the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C1. The first transistor T1 includes a first gate G1, a first source S1, and a first drain D1, wherein the first gate G1 is electrically connected to the reset signal line R1, and one of the first source S1 and the first drain D1 is electrically connected to the first initialization signal line Vinit1; the second transistor T2 includes a second gate G2, a second source S2, and a second drain D2, wherein the second gate G2 is electrically connected to the third scan signal line GL3; the third transistor T3 includes a third gate G3, a third source S3, and a third drain D3; the fourth transistor T4 includes a fourth gate G4, a fourth source S4, and a fourth drain The fourth gate D4 is electrically connected to the first scan signal line GL1, and one of the fourth source S4 and the fourth drain D4 is electrically connected to the data signal line Data; the fifth transistor T5 includes a fifth gate G5, a fifth source S5 and a fifth drain D5, the fifth gate G5 is electrically connected to the light emitting control signal line EM, and one of the fifth source S5 and the fifth drain D5 is electrically connected to the first power signal line; the sixth transistor T6 includes a sixth gate G6, a sixth source S6 and a sixth drain D6, the sixth gate G6 is electrically connected to the light emitting control signal line EM The seventh transistor T7 includes a seventh gate G7, a seventh source S7 and a seventh drain D7, wherein the seventh gate G7 is electrically connected to the second scan signal line GL2, and one of the seventh source S7 and the seventh drain D7 is electrically connected to the second initialization signal line Vinit2; and one of the second source S2 and the second drain D2, the third gate G3 and the first capacitor plate are electrically connected to the first node N1 respectively; one of the third source S3 and the third drain D3, the other of the fourth source S4 and the fourth drain D4, and the first gate G3 are electrically connected to the first node N1 respectively; The fifth source S5 and the other of the fifth drain D5 are respectively electrically connected to the second node N2; the first source S1 and the other of the first drain D1, the second source S2 and the other of the second drain D2, the third source S3 and the other of the third drain D3, and one of the sixth source S6 and the sixth drain D6 are respectively electrically connected to the third node N3; the sixth source S6 and the other of the sixth drain D6, and the seventh source S7 and the other of the seventh drain D7 are respectively electrically connected to the fourth node N4.

[0160] For example, in some disclosed embodiments, with reference to FIG5 and FIG14 , the display substrate 400 further includes a plurality of conductive transition portions 70 located in the second conductive layer 7, wherein the plurality of conductive transition portions 70 include a second conductive transition portion 702, the second conductive transition portion 702 being used to electrically connect one of the first source S1 and the first drain D1 of the first transistor T1 to the first initialization signal line Vinit1; the plurality of conductive transition portions 70 further include a third conductive transition portion 703, the third conductive transition portion 703 being used to electrically connect one of the second source S2 and the second drain D2 of the second transistor T2 to the first node N1; the plurality of conductive transition portions 70 further include a fourth conductive transition portion 704, the fourth conductive transition portion 704 being used to electrically connect the other of the second source S2 and the second drain D2 of the second transistor T2 and the third source S3 of the third transistor T3. and the third drain D3 of the third transistor T3, the other of the first source S1 and the first drain D1 of the first transistor T1, and one of the sixth source S6 and the sixth drain D6 of the sixth transistor T6 are electrically connected to the third node N3 respectively; the plurality of conductive transition portions 70 further include a fifth conductive transition portion 705, the fifth conductive transition portion 705 is used to electrically connect one of the fourth source S4 and the fourth drain D4 of the fourth transistor T4 to the data signal line Data; the plurality of conductive transition portions 70 further include a sixth conductive transition portion 706, the sixth conductive transition portion 706 is used to electrically connect the other of the third source S3 and the third drain D3 of the third transistor T3, the other of the fourth source S4 and the fourth drain D4 of the fourth transistor T4, and one of the fifth source S5 and the fifth drain D5 of the fifth transistor T5 to the third node N3 respectively. The second node N2 is electrically connected; the multiple conductive transition parts 70 also include a seventh conductive transition part 707, and the seventh conductive transition part 707 is used to electrically connect the other of the fifth source S5 and the fifth drain D5 of the fifth transistor T5 to the first power signal line VDD; the multiple conductive transition parts 70 also include an eighth conductive transition part 708, and the eighth conductive transition part 708 is used to electrically connect the other of the sixth source S6 and the sixth drain D6 of the sixth transistor T6 and one of the seventh source S7 and the seventh drain D7 of the seventh transistor T7 to the fourth node N4 respectively; the multiple conductive transition parts 70 also include a ninth conductive transition part 709, and the ninth conductive transition part 709 is used to electrically connect the other of the seventh source S7 and the seventh drain D7 of the seventh transistor T7 to the second initialization signal line Vinit2.

[0161] For example, in some embodiments of the present disclosure, with reference to FIG5-10 and FIG16, a display substrate 400 includes: a light shielding layer 1 located on a base substrate 10; a first semiconductor layer 2 located on a side of the light shielding layer 1 away from the base substrate 10; and a first conductive layer 3 located on a side of the first semiconductor layer 2 away from the base substrate 10. A pixel driving circuit includes multiple transistors. For example, the pixel driving circuit includes a driving transistor for driving the light-emitting device to emit light. The driving transistor may be a third transistor T3. The third transistor T3 includes a third active layer ACT3 and a third gate G3. The third active layer ACT3 is located in the first semiconductor layer 2, and the third gate G3 is located in the first conductive layer 3. The third active layer ACT3 includes a third channel region CH3. The orthographic projection of the third gate G3 on the base substrate at least partially overlaps with the orthographic projection of the third channel region CH3 on the base substrate. The first power signal line VDD includes a first sub-power signal line VDD1 located in the light shielding layer 1. The orthographic projection of the first sub-power signal line on the base substrate overlaps the orthographic projection of the third channel region CH3 on the base substrate. The first semiconductor layer 2 may include single crystal silicon, amorphous silicon or polycrystalline silicon semiconductor material. For example, the third transistor may be a low temperature polycrystalline silicon thin film transistor.

[0162] For example, in some embodiments of the present disclosure, referring to FIG. 5 , FIG. 7 and FIG. 10 , the pixel driving circuit further includes a first transistor T1 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a seventh transistor T7 . The first transistor T1 includes a first active layer ACT1 and a first gate G1, the first active layer ACT1 is located in the first semiconductor layer 2, and the first gate G1 is located in the first conductive layer 3; the fourth transistor T4 includes a fourth active layer ACT4 and a fourth gate G4, the fourth active layer ACT4 is located in the first semiconductor layer 2, and the fourth gate G4 is located in the first conductive layer 3; the fifth transistor T5 includes a fifth active layer ACT5 and a fifth gate G5, the fifth active layer ACT5 is located in the first semiconductor layer 2, and the fifth gate G5 is located in the first conductive layer 3; the sixth transistor T6 includes a sixth active layer ACT6 and a first gate G6, the sixth active layer ACT6 is located in the first semiconductor layer 2, and the sixth gate G6 is located in the first conductive layer 3; and the seventh transistor T7 includes a seventh active layer ACT7 and a seventh gate G7, the seventh active layer ACT7 is located in the first semiconductor layer 2, and the seventh gate G7 is located in the first conductive layer 3.

[0163] 5 and 6 , in some embodiments of the present disclosure, the first power signal line VDD further includes a second sub-power signal line VDD2 located in the light shielding layer 1. The main portion VDD1-L of the first sub-power signal line extends along the first direction X, and the second sub-power signal line VDD2 extends along the second direction Y.

[0164] Exemplarily, continuing to refer to Figures 5 and 6, the display substrate includes m first sub-power signal lines VDD1 and n second sub-power signal lines VDD2 located in the light-shielding layer 1, and each of the m first sub-power lines crosses with n second sub-power signal lines VDD2, so that the portion of the first power signal line VDD located in the light-shielding layer 1 has a grid structure, m is greater than or equal to 1, and n is greater than or equal to 2.

[0165] By disposing the first sub-power signal line and the second sub-power signal line of the first power signal line in the light-shielding layer, they can be used as both a light-shielding portion and a power signal line to transmit power signals, thereby eliminating a conductive layer and a planarization layer used as the power signal line, thereby saving costs. The light-shielding portion can be made of a low-resistance material to ensure that the voltage drop of the power signal line in the light-shielding portion is small, which is beneficial for the transmission of the power signal. At the same time, the grid-shaped design of the first power signal line can facilitate the transmission of the first power signal in the first and second directions, shortening the transmission distance, reducing the voltage drop, and improving the driving effect of the pixel driving circuit. Disposing the first sub-power signal line and the second sub-power signal line of the first power signal line in the light-shielding layer can be used as both a light-shielding portion and a power signal line to transmit power signals. The signal line routing width can be designed to be smaller, which is beneficial for improving the flatness of the film layer and the aperture ratio of the display substrate, and is beneficial for improving the display effect of the display product.

[0166] For example, in some embodiments of the present disclosure, referring to FIG16 , the display substrate further includes: a second conductive layer 7 located on a side of the first conductive layer 3 remote from the base substrate; a planarization layer PLN located on a side of the second conductive layer 7 remote from the base substrate; and a first electrode layer 100 located on a side of the planarization layer PLN remote from the base substrate. With reference to FIG5 and FIG14 , the pixel driving circuit includes a third transistor T3, which may be a driving transistor, for example. The third transistor T3 includes a third source S3 and a third drain D3, each located in the second conductive layer 7.

[0167] Exemplarily, referring to Figure 16, the light-emitting element L also includes a first electrode 110, an organic light-emitting functional layer 111 and a second electrode 112, and the first electrode 110 is located in the first electrode layer 100; the planarization layer PLN includes a first surface PLN1 facing the second conductive layer 7 and a second surface PLN2 facing the first electrode layer 100, the first surface PLN1 contacts at least a portion of the second conductive layer 7, and the second surface PLN2 contacts at least a portion of the first electrode layer 100.

[0168] For example, in some embodiments of the present disclosure, the pixel driving circuit further includes a storage capacitor C1. Referring to Figures 5, 11, and 12, the storage capacitor C1 includes a first capacitor plate C1a and a second capacitor plate C1b. At least a portion of the first capacitor plate C1a is located in the first conductive layer 3. The portion of the first capacitor plate C1a that overlaps with the third active layer ACT3 serves as the third gate of the third transistor. The display substrate further includes a third conductive layer 4 located on a side of the first conductive layer 3 away from the base substrate. The second capacitor plate C1b is located in the third conductive layer 4. The portion of the first power signal line VDD located in the light shielding layer 1 is electrically connected to the second capacitor plate C1b within the display area via a second via VH2.

[0169] For example, in some embodiments of the present disclosure, with reference to FIG5 , FIG14 , and FIG16 , the display substrate 400 further includes: a second conductive layer 7 located on a side of the first conductive layer 3 away from the base substrate; a third transistor T3 including a third source S3 and a third drain D3, wherein the third source S3 and the third drain D3 are located in the second conductive layer 7; and the first power signal line VDD further includes a third sub-power signal line VDD3 located in the second conductive layer 7. The orthographic projection of the third sub-power signal line VDD3 on the base substrate at least partially overlaps with the orthographic projection of the second sub-power signal line VDD2 on the base substrate. The arrangement of partially parallel first power signal lines can reduce voltage drops on the first power signal lines, improve the stability of the drive circuit, and thus enhance the display quality of the display substrate.

[0170] For example, in some embodiments of the present disclosure, referring to FIG5 , FIG6 , and FIG14 , the display substrate 400 includes k third sub-power signal lines VDD3 located in the second conductive layer 7 ; the number n of the second sub-power signal lines VDD2 is at least twice the number k of the third sub-power signal lines VDD3 . k is greater than or equal to 1, and n is greater than or equal to 2. By densely arranging the first power signal lines along the second direction in the light shielding layer 1 , the voltage drop across the first power signal lines can be reduced, thereby improving the stability of the drive circuit and enhancing the display quality of the display substrate.

[0171] Exemplarily, referring to FIG. 5 , FIG. 6 and FIG. 14 , the third sub-power signal line VDD3 is electrically connected to the second sub-power signal line VDD2 through the first via hole VH1 .

[0172] For example, in some embodiments of the present disclosure, with reference to FIG5 , FIG13 , FIG15 , and FIG17 , the display substrate 400 further includes a second semiconductor layer 5 located on a side of the first semiconductor layer 2 away from the base substrate 10. The pixel driving circuit further includes a second transistor T2, which includes a second active layer ACT2 located in the second semiconductor layer 5. For example, the second semiconductor layer 5 may include an oxide semiconductor material, that is, the second transistor T2 may be an oxide thin film transistor.

[0173] For example, in some embodiments of the present disclosure, in combination with Figures 5, 13 and 17, the second transistor T2 includes a second gate G2, the second gate includes a first sub-gate G21 and a second sub-gate G22, the layer where the first sub-gate G21 is located is located on the side of the second semiconductor layer 5 close to the base substrate 10, the layer where the second sub-gate G22 is located is located on the side of the second semiconductor layer 5 away from the base substrate 10, the orthographic projection of the first sub-gate G21 on the base substrate 10 at least partially overlaps with the orthographic projection of the second active layer ACT2 on the base substrate 10, and the orthographic projection of the second sub-gate G22 on the base substrate 10 at least partially overlaps with the orthographic projection of the second active layer ACT2 on the base substrate 10.

[0174] For example, in some embodiments of the present disclosure, with reference to FIG13 , FIG16 , and FIG17 , the display substrate further includes a third conductive layer 4 located between the first semiconductor layer 2 and the second semiconductor layer 5; and a fourth conductive layer 6 located on a side of the second semiconductor layer 5 away from the base substrate 10. The first sub-gate G21 of the second transistor T2 is located in the third conductive layer 4, and the second sub-gate G22 of the second transistor T2 is located in the fourth conductive layer 6. In other words, the second transistor T2 has a dual-gate structure located in different conductive layers.

[0175] For example, a gate insulating layer 50 may be disposed between the first sub-gate G21 and the second active layer ACT2 . A gate insulating layer 50 may be disposed between the second sub-gate G22 and the second active layer ACT2 . The display substrate may further include other insulating layers, such as an interlayer insulating layer 60 .

[0176] For example, in some embodiments of the present disclosure, with reference to Figures 5, 9, 11 and 12, the pixel driving circuit further includes a storage capacitor C1, which includes a first capacitor plate C1a and a second capacitor plate C1b; at least a portion of the first capacitor plate C1a is located in the first conductive layer 3; and at least a portion of the second capacitor plate C1b is located in the third conductive layer 4.

[0177] For example, in some embodiments of the present disclosure, with reference to FIG5 , FIG6 , FIG11 , and FIG14 , a portion of the third sub-power signal line VDD3 is electrically connected to the second sub-power signal line VDD2 via a first via VH1, and another portion of the third sub-power signal line VDD3 is electrically connected to at least a portion of the second capacitor plate C1b within the display area via a second via VH2. For example, the second sub-power signal line VDD2, the third sub-power signal line VDD3, and the second capacitor plate C1b can all be electrically connected to each other via the second via VH2.

[0178] For example, in some embodiments of the present disclosure, the material of the light shielding layer 1 may include copper or aluminum. For example, the resistivity of the material of the light shielding layer 1 is lower than the resistivity of the material of the second conductive layer.

[0179] For example, in some embodiments of the present disclosure, the display substrate includes a plurality of sub-pixels and a pixel driving circuit for driving the plurality of sub-pixels. For example, with reference to FIG5 and FIG6 , the plurality of sub-pixels include sub-pixels located in column j and sub-pixels located in column j+1. In the light shielding layer 1, the first portion P1 of the first power signal line that provides the first power signal line to the pixel driving circuit of the sub-pixel in column j and the second portion P2 of the first power signal line that provides the first power signal line to the pixel driving circuit of the sub-pixel in column j+1 are symmetrical with respect to the first imaginary straight line M1, wherein the first imaginary straight line M1 is a straight line extending along the second direction Y. That is, the first power signal lines included in the pixel driving circuits of two adjacent sub-pixels are symmetrical with respect to the first imaginary straight line M1.

[0180] For example, in some embodiments of the present disclosure, the connection method of the second gate G2 in the second transistor T2 can be changed in the pixel driving circuit of the display substrate. For example, the first sub-gate G21 of the second gate G2 can be disposed in the first conductive layer 3, and the second sub-gate G22 of the second gate G2 can be disposed in the third conductive layer 4 or the fourth conductive layer 6. This can eliminate a conductive layer, such as the fourth conductive layer or the third conductive layer, thereby reducing the manufacturing process and saving costs. The display substrate can also dispose a portion of the first power signal line in the light shielding layer, which can be used as both a light shielding portion and a power signal line to transmit the power signal. This can eliminate a conductive layer used as a power signal line and a planarization layer, thereby saving costs. The light shielding portion can be made of a low-resistance material to ensure a low voltage drop on the power signal line in the light shielding portion, which is beneficial for the transmission of the power signal. At the same time, the grid-like design of the first power signal line facilitates the transmission of the first power signal in the first and second directions, shortening the transmission distance and reducing voltage drop, thereby improving the driving effect of the pixel driving circuit.

[0181] For example, in some embodiments of the present disclosure, the pixel driving circuit may be a low-temperature polysilicon driving circuit, for example, the second transistor may be an LTPS (Low Temperature Poly-Silicon) thin film transistor. That is to say, the pixel driving circuit provided by the embodiments of the present disclosure is compatible with an LTPS display substrate. In this case, the second semiconductor layer and the fourth conductive layer may be removed to achieve a high PPI display substrate. By arranging the first sub-power signal line and the second sub-power signal line in the first power signal line in the light-shielding layer, they can be used as both a light-shielding portion and a power signal line to transmit power signals, thereby eliminating a layer of conductive layer used as a power signal line and a layer of planarization layer, thereby saving costs. The light-shielding portion may be made of a low-resistance material to ensure that the voltage drop of the power signal line in the light-shielding portion is small, which is beneficial to the transmission of the power signal. At the same time, the grid-shaped first power signal line design may facilitate the transmission of the first power signal in the first direction and the second direction, shorten the transmission distance, reduce the voltage drop, and enhance the driving effect of the pixel driving circuit. The first sub-power signal line and the second sub-power signal line in the first power signal line are arranged in the light-shielding layer, which can be used as both a light-shielding part and a power signal line to transmit power signals. The signal line routing width can be designed to be smaller, which is beneficial to improving the flatness of the film layer and the aperture ratio of the display substrate, and is beneficial to improving the display effect of the display product.

[0182] Figure 18 is a planar schematic diagram of a pixel driving circuit for multiple sub-pixels in a display substrate according to other embodiments of the present disclosure; Figure 19 is a planar schematic diagram of a combined film layer of a first conductive layer, a second semiconductor layer, and a third conductive layer in the pixel driving circuit of Figure 18; Figure 20 is a planar schematic diagram of the second conductive layer in the pixel driving circuit of Figure 18; and Figure 21 is a partial cross-sectional schematic diagram taken along line CC' in Figure 18.

[0183] For example, in some embodiments of the present disclosure, with reference to FIG18 and FIG19 , a display substrate 400 includes a plurality of sub-pixels and a pixel driving circuit for driving the plurality of sub-pixels. The pixel driving circuit includes a plurality of signal lines disposed on a base substrate. The plurality of signal lines includes a first power signal line VDD for providing a first power signal to the pixel driving circuit. The plurality of signal lines further includes a first initialization signal line Vinit1, a second initialization signal line Vinit2, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, an emission control signal line EM, and a data signal line Data. The first initialization signal line Vinit1, the second initialization signal line Vinit2, the reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, and the emission control signal line EM extend along a first direction X, and the data signal line Data extends along a second direction Y. The reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the light-emission control signal line EM, and the second initialization signal line Vinit2 are located in the first conductive layer 3; the first initialization signal line Vinit1 is located in the third conductive layer 4. A portion of the third scan signal line GL3 is located in the first conductive layer 3, and another portion of the third scan signal line GL3 is located in the third conductive layer 4. In other words, the third scan signal line is formed by a portion located in the first conductive layer 3 and another portion located in the third conductive layer 4 in parallel, and is used to transmit a third scan signal.

[0184] For example, in some embodiments of the present disclosure, in combination with Figures 18, 20 and 21, the display substrate 400 also includes: a second conductive layer 7 located on the side of the first conductive layer 3 away from the base substrate; the third transistor T3 includes a third source S3 and a third drain D3, and the third source S3 and the third drain D3 are located in the second conductive layer 7, and the first power signal line VDD also includes a first conductive transition portion 701 located in the second conductive layer 7, and the first conductive transition portion is electrically connected to the second sub-power signal line VDD2 through the first via VH1.

[0185] For example, a gate insulating layer 50 may be disposed between the first sub-gate G21 and the second active layer ACT2 . A gate insulating layer 50 may be disposed between the second sub-gate G22 and the second active layer ACT2 . The display substrate may further include other insulating layers, such as an interlayer insulating layer 60 .

[0186] For example, in some embodiments of the present disclosure, referring to FIG. 18 and FIG. 20 , the orthographic projection of the first conductive transition portion 701 on the base substrate 10 at least partially overlaps with the orthographic projection of the second sub-power signal line VDD2 on the base substrate 10 .

[0187] For example, in some embodiments of the present disclosure, with reference to FIG18 and FIG19 , the display substrate further includes a second transistor T2, which includes a second gate G2, which includes a first sub-gate G21 and a second sub-gate G22. The display substrate further includes a second semiconductor layer 5 and a third conductive layer 4 located on a side of the second semiconductor layer 5 away from the base substrate 10; the first sub-gate G21 is located in the first conductive layer 3, and the second sub-gate G22 is located in the third conductive layer 4.

[0188] For example, in some embodiments of the present disclosure, with reference to FIG18 and FIG19 , the display substrate further includes a storage capacitor C1, which includes a first capacitor plate C1a and a second capacitor plate C1b. At least a portion of the first capacitor plate C1a is located in the first conductive layer 3, and at least a portion of the second capacitor plate C1b is located in the third conductive layer 4. A portion of the first conductive connection portion 701 is electrically connected to the second sub-power signal line VDD2 through a first via VH1, and another portion of the first conductive connection portion 701 is electrically connected to at least a portion of the second capacitor plate C1b within the display area through a second via VH2.

[0189] By changing the connection method of the gate of the second transistor T2, for example, setting the first sub-gate G21 of the second transistor in the first conductive layer 3 and the second sub-gate G22 in the third conductive layer 4, the second capacitor plate C1b of the storage capacitor C1 can also be correspondingly set in the third conductive layer 4, thereby eliminating a conductive layer, reducing the corresponding metal mask, and saving costs.

[0190] Figure 22 is a planar schematic diagram of a pixel driving circuit of multiple sub-pixels in a display substrate according to other embodiments of the present disclosure; Figure 23 is a planar schematic diagram of a combined film layer of a first conductive layer, a second semiconductor layer and a fourth conductive layer in the pixel driving circuit of Figure 22; Figure 24 is a planar schematic diagram of the second conductive layer in the pixel driving circuit of Figure 22; Figure 25 is a partial cross-sectional schematic diagram taken along line DD' in Figure 22.

[0191] For example, in some embodiments of the present disclosure, with reference to FIG22 and FIG23 , a display substrate 400 includes a plurality of sub-pixels and a pixel driving circuit for driving the plurality of sub-pixels. The pixel driving circuit includes a plurality of signal lines disposed on a base substrate. The plurality of signal lines includes a first power signal line VDD for providing a first power signal to the pixel driving circuit. The plurality of signal lines further includes a first initialization signal line Vinit1, a second initialization signal line Vinit2, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, an emission control signal line EM, and a data signal line Data. The first initialization signal line Vinit1, the second initialization signal line Vinit2, the reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, and the emission control signal line EM extend along a first direction X, and the data signal line Data extends along a second direction Y. The reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the light-emission control signal line EM, and the second initialization signal line Vinit2 are located in the first conductive layer 3; the first initialization signal line Vinit1 is located in the fourth conductive layer 6. A portion of the third scan signal line GL3 is located in the first conductive layer 3, and another portion of the third scan signal line GL3 is located in the fourth conductive layer 6. In other words, the third scan signal line is formed by a portion located in the first conductive layer 3 and another portion located in the fourth conductive layer 6 in parallel, and is used to transmit a third scan signal.

[0192] For example, in some embodiments of the present disclosure, in combination with Figures 22, 24 and 25, the display substrate 400 also includes: a second conductive layer 7 located on the side of the first conductive layer 3 away from the base substrate; the third transistor T3 includes a third source S3 and a third drain D3, and the third source S3 and the third drain D3 are located in the second conductive layer 7, and the first power signal line VDD also includes a first conductive transition portion 701 located in the second conductive layer 7, and the first conductive transition portion is electrically connected to the second sub-power signal line VDD2 through the first via VH1.

[0193] For example, a gate insulating layer 50 may be disposed between the first sub-gate G21 and the second active layer ACT2 . A gate insulating layer 50 may be disposed between the second sub-gate G22 and the second active layer ACT2 . The display substrate may further include other insulating layers, such as an interlayer insulating layer 60 .

[0194] For example, in some embodiments of the present disclosure, referring to FIG. 22 and FIG. 24 , the orthographic projection of the first conductive transition portion 701 on the base substrate 10 at least partially overlaps with the orthographic projection of the second sub-power signal line VDD2 on the base substrate 10 .

[0195] For example, in some embodiments of the present disclosure, with reference to FIG22 and FIG23 , the display substrate further includes a second transistor T2, which includes a second gate G2, which includes a first sub-gate G21 and a second sub-gate G22. The display substrate further includes a second semiconductor layer 5 and a fourth conductive layer 6 located on a side of the second semiconductor layer 5 away from the base substrate 10; the first sub-gate G21 is located in the first conductive layer 3, and the second sub-gate G22 is located in the fourth conductive layer 6.

[0196] The display substrate further includes a storage capacitor C1, which includes a first capacitor plate C1a and a second capacitor plate C1b. At least a portion of the first capacitor plate C1a is located in the first conductive layer 3, and at least a portion of the second capacitor plate C1b is located in the fourth conductive layer 6. A portion of the first conductive connection portion 701 is electrically connected to the second sub-power signal line VDD2 through a first via VH1, and another portion of the first conductive connection portion 701 is electrically connected to at least a portion of the second capacitor plate C1b within the display area through a second via VH2.

[0197] By changing the connection method of the gate of the second transistor T2, for example, setting the first sub-gate G21 of the second transistor in the first conductive layer 3 and the second sub-gate G22 in the fourth conductive layer 6, the second capacitor plate C1b of the storage capacitor C1 can also be correspondingly set in the fourth conductive layer 6, thereby eliminating a conductive layer, reducing the corresponding metal mask, and saving costs.

[0198] For example, in some embodiments of the present disclosure, the pixel driving circuit of the display substrate includes a second transistor. The second transistor can be a single-gate structure. For example, the gate of the second transistor can be set in the first conductive layer 3. That is, the gate of the second transistor in the pixel driving circuit can be set in the same layer as the gate of other transistors, such as the third transistor, thereby eliminating the third conductive layer and the fourth conductive layer, and reducing the corresponding metal mask. The light shielding portion can be made of a low-resistance material to ensure that the voltage drop of the power signal line in the light shielding portion is small, which is conducive to the transmission of the power signal. At the same time, the grid-shaped first power signal line design can facilitate the transmission of the first power signal in the first direction and the second direction, shorten the transmission distance, reduce the voltage drop, and improve the driving effect of the pixel driving circuit.

[0199] Figure 26 is a planar schematic diagram of a pixel driving circuit of multiple sub-pixels in a display substrate according to other embodiments of the present disclosure; Figure 27 is a planar schematic diagram of a combined film layer of a light-shielding layer, a first semiconductor layer and a first conductive layer in the pixel driving circuit of Figure 26; Figure 28 is a planar schematic diagram of a combined film layer of a first conductive layer and a second semiconductor layer in the pixel driving circuit of Figure 26; Figure 29 is a planar schematic diagram of the second conductive layer in the pixel driving circuit of Figure 26; Figure 30 is a partial cross-sectional schematic diagram taken along the center line EE' of Figure 26; Figure 31A is a partial cross-sectional schematic diagram taken along the center line FF' of Figure 26; Figure 31B is a partial cross-sectional schematic diagram of a display substrate according to other embodiments of the present disclosure taken along the center line FF' of Figure 26.

[0200] 26 to 28 , the display substrate 400 includes a first initialization signal line Vinit1, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, a light emission control signal line EM, and a second initialization signal line Vinit2. The first initialization signal line Vinit1, the reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, the light emission control signal line EM, and the second initialization signal line Vinit2 are all located in the first conductive layer 3.

[0201] For example, in some embodiments of the present disclosure, with reference to Figures 26-28 and 31A, the display substrate 400 may further include a first conductive layer 3 and a second semiconductor layer 5. The first conductive layer 3 is located on a side of the second semiconductor layer 5 away from the base substrate. The display substrate 400 may further include a first insulating layer GI1 located between the first semiconductor layer 2 and the second semiconductor layer; and a second insulating layer GI2 located between the second semiconductor layer 5 and the first conductive layer 3. The display substrate also includes a second transistor T2 and a third transistor T3. The second transistor T2 includes a second gate G2 and a second active layer ACT2. The third transistor T3 includes a third gate G3 and a third active layer ACT3. The second gate G2 and the third gate G3 are both located in the first conductive layer 3. The orthographic projection of the second gate G2 on the base substrate at least partially overlaps with the orthographic projection of the second active layer ACT2 on the base substrate. The orthographic projection of the third gate G3 on the base substrate at least partially overlaps with the orthographic projection of the third active layer ACT3 on the base substrate.

[0202] For example, the first insulating layer GI1 and a portion of the second insulating layer GI2 together constitute the gate insulating layer of the third transistor T3 , and a portion of the second insulating layer GI2 constitutes the gate insulating layer of the second transistor T2 .

[0203] For example, in some embodiments of the present disclosure, with reference to FIG28 and FIG31A, the second transistor T2 can be a single-gate structure, the thickness of the insulating layer between the first semiconductor layer 2 and the first conductive layer 3 is d1, the thickness between the second semiconductor layer 5 and the first conductive layer is d2, the spacing between the first semiconductor layer 2 and the second semiconductor layer 5 in the direction perpendicular to the substrate is d3, and the thickness of the second semiconductor layer 5 is d4. Among them, the sum of d2, d3 and d4 is substantially equal to the value of d1. Among them, substantially equal means that the ratio of the absolute values ​​of the two is between 0.8 and 1.2. By adjusting the spacing between the first semiconductor layer 2, the second semiconductor layer 5 and the first conductive layer 3, it is ensured that the first conductive layer can be used as the top gate of the first semiconductor layer 2 and the second semiconductor layer 5 at the same time, which can reduce the manufacturing process and save costs.

[0204] For example, in some embodiments of the present disclosure, with reference to Figures 26-28 and 31B, the display substrate 400 may further include a first conductive layer 3 and a second semiconductor layer 5. The first conductive layer 3 is located on a side of the first semiconductor layer 2 away from the base substrate, and the second semiconductor layer 5 is located on a side of the first conductive layer 3 away from the base substrate. The display substrate 400 may further include a first insulating layer GI1 located between the first semiconductor layer 2 and the first conductive layer 3; and a second insulating layer GI2 located between the first conductive layer 3 and the second semiconductor layer 5. The display substrate also includes a second transistor T2 and a third transistor T3. The second transistor T2 includes a second gate G2 and a second active layer ACT2. The third transistor T3 includes a third gate G3 and a third active layer ACT3. Both the second gate G2 and the third gate G3 are located in the first conductive layer 3. The orthographic projection of the second gate G2 on the base substrate at least partially overlaps with the orthographic projection of the second active layer ACT2 on the base substrate, and the orthographic projection of the third gate G3 on the base substrate at least partially overlaps with the orthographic projection of the third active layer ACT3 on the base substrate.

[0205] For example, a portion of the first insulating layer GI1 together constitutes the gate insulating layer of the third transistor T3 , and a portion of the second insulating layer GI2 constitutes the gate insulating layer of the second transistor T2 .

[0206] For example, in some embodiments of the present disclosure, with reference to FIG. 28 and FIG. 31B , the second transistor T2 may have a single-gate structure. For example, the second transistor T2 may have a bottom-gate structure, wherein the gate G2 of the second transistor T2 and the gate G3 of the third transistor T3 may be located in the same conductive layer, such as the first conductive layer 3. By designing the second transistor T2 as a bottom-gate structure and arranging the gate G2 of the second transistor and the gate G3 of the third transistor in the same layer, the manufacturing process can be reduced and costs can be saved.

[0207] For example, in some embodiments of the present disclosure, in combination with Figures 26, 29 and 30, the display substrate further includes a second conductive layer 7 located on the side of the first conductive layer 3 away from the base substrate; at least a portion of the first capacitor plate C1a of the storage capacitor C1 is located in the first conductive layer 3, and at least a portion of the second capacitor plate C1b of the storage capacitor C1 is located in the second conductive layer 7.

[0208] For example, in some embodiments of the present disclosure, with reference to Figures 26, 27, and 29, the display substrate 400 includes a third sub-power signal line VDD3. The third sub-power signal line VDD3 and the second capacitor plate C1b are both located in the second conductive layer 7, and the third sub-power signal line VDD3 is connected to at least a portion of the second capacitor plate C1b. The display substrate also includes a second sub-power signal line VDD2 located in the light shielding layer 1. The third sub-power signal line VDD3 is electrically connected to the second sub-power signal line VDD2 through a first via VH1.

[0209] For example, in some embodiments of the present disclosure, with reference to Figures 26 and 30, the pixel driving circuit includes a storage capacitor C1, which includes a first capacitor plate C1a and a second capacitor plate C1b; at least a portion of the first capacitor plate C1a is located in the first conductive layer 3, and the second capacitor plate C1b includes a first sub-capacitor plate C1b1 and a second sub-capacitor plate C1b2, the first sub-capacitor plate C1b1 is located in the second conductive layer 7, and the second sub-capacitor plate C1b2 is located in the light shielding layer 1; the orthographic projection of each of the first sub-capacitor plate C1b1 and the second sub-capacitor plate C1b2 on the substrate at least partially overlaps with the orthographic projection of the first capacitor plate C1a on the substrate. By providing a sandwich-structured storage capacitor, the capacity of the storage capacitor can be increased, the compensation capability of the driving transistor can be improved, and the driving capability of the pixel driving circuit can be improved, thereby improving the display effect of the display product.

[0210] For example, in some embodiments of the present disclosure, the second sub-capacitor plate C1b2 can adopt a widened design to further increase the capacity of the storage capacitor and improve the compensation capability of the driving transistor, which is beneficial to improving the driving capability of the pixel driving circuit and thereby improving the display effect of the display product.

[0211] Exemplarily, at least some embodiments of the present disclosure also provide a display substrate, wherein the display substrate includes: a base substrate; a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged in an array on the base substrate along a first direction and a second direction, at least one sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; a plurality of signal lines arranged on the base substrate, the plurality of signal lines including a first power signal line, the first power signal line being used to provide a first power signal to the pixel driving circuit, wherein the display substrate also includes: a light-shielding layer located on the base substrate; a first semiconductor layer located on a side of the light-shielding layer away from the base substrate; and a first conductive layer located on a side of the first semiconductor layer away from the base substrate; the first power signal line also includes a first sub-power signal line and a second sub-power signal line located in the light-shielding layer, the main part of the first sub-power signal line extends along the first direction, and the second sub-power signal line extends along the second direction, the first sub-power signal line and the second sub-power signal line are electrically connected to each other for transmitting the first power signal. By arranging the first and second sub-power signal lines within the light-shielding layer, the first power signal line can function as both a light-shielding portion and a power signal line for transmitting power signals. This eliminates the need for a conductive layer and a planarization layer for power signal lines, saving costs. The first and second sub-power signal lines are arranged in a grid pattern, shortening the transmission distance of the first power signal. This minimizes the voltage drop across the power signal line within the light-shielding portion, facilitating power signal transmission.

[0212] For example, in some embodiments of the present disclosure, the light-shielding portion in the display substrate may not include the first power signal line, and may only be used to shield a local area in the pixel driving circuit of the display substrate, and the first power signal line may be located in other film layers. For example, the display substrate may further include a fifth conductive layer, and the data signal line Data for transmitting the data signal and the first power signal line VDD for transmitting the first power signal may both be arranged in the fifth conductive layer. That is to say, in some embodiments of the present disclosure, the pixel driving circuit may be compatible with the traditional light-shielding layer design. By optimizing the connection method of the gate of the second transistor in the pixel driving circuit, for example, the second transistor is designed as a single-gate structure, and the second gate of the second transistor is arranged in the third conductive layer, a conductive layer can be omitted, the corresponding metal mask template can be reduced, and costs can be saved.

[0213] Figure 32 is a planar schematic diagram of a pixel driving circuit of multiple sub-pixels in a display substrate according to some embodiments of the present disclosure; Figure 33 is a planar schematic diagram of a light-shielding layer in the pixel driving circuit according to Figure 32; Figure 34 is a planar schematic diagram of a combined film layer of a light-shielding layer and a first semiconductor layer in the pixel driving circuit according to Figure 32; Figure 35 is a planar schematic diagram of a combined film layer of a light-shielding layer, a first semiconductor layer, a first conductive layer, and a second semiconductor layer in the pixel driving circuit according to Figure 32; Figure 36 is a planar schematic diagram of a combined film layer of a light-shielding layer, a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a third conductive layer in the pixel driving circuit according to Figure 32; Figure 37 is a planar schematic diagram of the second conductive layer in the pixel driving circuit according to Figure 32; Figure 38 is a planar schematic diagram of a combined film layer of a light-shielding layer, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a third conductive layer, and a second conductive layer in the pixel driving circuit according to Figure 32; Figure 39 is a partial cross-sectional schematic diagram taken along line GG' in Figure 32; and Figure 40 is a partial cross-sectional schematic diagram taken along line HH' in Figure 32.

[0214] Illustratively, at least some embodiments of the present disclosure further provide a display substrate. Referring to FIG. 1 , the display substrate includes: a base substrate 100; and a plurality of sub-pixels SP located on the base substrate, wherein the plurality of sub-pixels SP are arranged in an array on the base substrate 100 along a first direction X and a second direction Y, and at least one sub-pixel SP includes a light-emitting device L and a pixel driving circuit 200 for driving the light-emitting device L to emit light, and the first direction X and the second direction Y intersect.

[0215] Exemplarily, in combination with Figures 36, 39 and 40, the display substrate also includes a first semiconductor layer 2 located on the base substrate; a first conductive layer 3 located on the side of the first semiconductor layer 2 away from the base substrate; a second semiconductor layer 5 located on the side of the first conductive layer 3 away from the base substrate; and a third conductive layer 4 located on the side of the second semiconductor layer 5 away from the base substrate.

[0216] For example, with reference to Figures 32-36, the pixel driving circuit of the display substrate 400 includes a second transistor T2 and a third transistor T3. The second transistor T2 and the third transistor T3 can both have a top-gate structure. The second transistor T2 includes a second active layer ACT2 and a second gate G2, and the third transistor T3 includes a third active layer ACT3 and a third gate G3. The active layer ACT2 of the second transistor can include an oxide semiconductor material such as IGZO, and the active layer ACT3 of the third transistor can include a low-temperature polysilicon semiconductor material. That is, the transistor types of the second transistor and the third transistor can be different. For example, the second transistor can be an oxide thin-film transistor, and the third transistor can be a low-temperature polysilicon thin-film transistor. The active layer of the second transistor and the active layer of the third transistor can be located in different layers. For example, the active layer ACT2 of the second transistor can be located in the second semiconductor layer 5, and the active layer ACT3 of the third transistor can be located in the first semiconductor layer 2. The second gate G2 of the second transistor and the third gate G3 of the third transistor may also be located in different layers. For example, the gate G2 of the second transistor may be located in the third conductive layer 4 , and the gate G3 of the third transistor may be located in the first conductive layer 3 .

[0217] For example, with reference to Figures 34-36 , the third active layer ACT3 in the third transistor includes a third channel region CH3, and the orthographic projection of the third gate G3 of the third transistor on the substrate at least partially overlaps with the orthographic projection of the third channel region CH3 on the substrate. The second active layer ACT2 in the second transistor includes a second channel region CH2, and the orthographic projection of the second gate G2 of the second transistor on the substrate at least partially overlaps with the orthographic projection of the second channel region CH2 on the substrate.

[0218] By designing the second transistor into a top-gate structure, at least one conductive layer can be reduced, for example, the fourth conductive layer can be reduced, thereby saving costs and wiring space, which is beneficial to improving the aperture ratio and flatness of the display substrate.

[0219] Exemplarily, with reference to Figures 33, 35 and 40, the display substrate includes a light-shielding layer 1 located on the side of the first semiconductor layer 2 close to the base substrate, and the light-shielding layer includes a first light-shielding portion 101 and a second light-shielding portion 102, the orthographic projection of the first light-shielding portion 101 on the base substrate at least partially overlaps with the orthographic projection of the third channel region CH3 on the base substrate, and can be used to shield the channel region of the third transistor; the orthographic projection of the second light-shielding portion 102 on the base substrate at least partially overlaps with the orthographic projection of the second channel region CH2 on the base substrate, and can be used to shield the channel region of the second transistor, that is, the light-shielding layer 1 can be used to shield the second transistor and the third transistor at the same time, thereby improving the performance of the second transistor and the third transistor, thereby improving the display quality of the display substrate.

[0220] Exemplarily, referring to Figures 33 and 38, the first light-shielding portion 101 includes a first light-shielding sub-portion 1011 extending along the first direction X and a second light-shielding sub-portion 1012 extending along the second direction Y. The first light-shielding sub-portion 1011 and the second light-shielding sub-portion 1012 are connected so that the first light-shielding portion 101 forms an L-shaped structure; and / or, the second light-shielding portion 102 extends from a part of the first light-shielding sub-portion 1011 along the second direction Y, that is, the light-shielding component used for the second transistor and the third transistor can be continuous, which is beneficial to improving the light-shielding effect of the light-shielding portion on the second transistor and the third transistor.

[0221] For example, with reference to Figures 32 and 39, the display substrate further includes a second conductive layer 7 located on a side of the third conductive layer 4 away from the base substrate; and a fifth conductive layer 8 located on a side of the second conductive layer 7 away from the base substrate. A data signal line Data for transmitting a data signal and a first power signal line VDD for transmitting a first power signal can both be disposed in the fifth conductive layer 8. Multiple data signal lines Data and multiple first power signal lines VDD are spaced apart in a first direction X, and each of the multiple data signal lines Data and multiple first power signal lines VDD extends along a second direction Y. The light shielding portion 1 in the display substrate may not include the first power signal line and may be used only to shield a local area of ​​the pixel driving circuit of the display substrate. That is, the design of the light shielding layer in at least some embodiments of the present disclosure is compatible with conventional light shielding layer designs.

[0222] It should be noted that the display substrate 400 may further include an insulating layer located between any two adjacent layers among the aforementioned semiconductor layers and the aforementioned conductive layers. As shown in FIG39 , an insulating layer 50 may be provided between the layer where the light shielding portion 1 is located and the second semiconductor layer 5, and an insulating layer 50 may be provided between the second semiconductor layer 5 and the third conductive layer 4. For example, the insulating layer 50 may be a gate insulating layer. An insulating layer 61 may be provided between the third conductive layer 4 and the second conductive layer 7, and an insulating layer 62 may be provided between the second conductive layer 7 and the fifth conductive layer 8. For example, the insulating layers 61 and 62 may be interlayer insulating layers. As shown in FIG40 , an insulating layer IL1 may be provided between the layer where the light shielding portion 1 is located and the first semiconductor layer 2, an insulating layer IL2 may be provided between the first semiconductor layer 2 and the first conductive layer 3, an insulating layer IL3 may be provided between the first conductive layer 3 and the third conductive layer 4, and an insulating layer IL4 may be provided between the third conductive layer 4 and the fifth conductive layer 8. It should be noted that at least one of the above-mentioned insulating layers 50, 61, 62, IL1, IL2, IL3, and IL4 can be a single-film structure, that is, it includes only a single insulating film layer, or it can be a multi-film structure, that is, it includes more than two insulating film layers. The embodiment of the present disclosure does not impose any special restrictions on the structure of the insulating film layer.

[0223] For example, referring to Figures 32 and 36, the pixel driving circuit of the display substrate 400 may further include a first transistor T1, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The active layer of each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be located in the first semiconductor layer 2. The pixel circuit of the display substrate may further include a storage capacitor C1, which includes a first capacitor plate C1a and a second capacitor plate C1b. The first capacitor plate C1a may be located in the first conductive layer 3, and the second capacitor plate C1b may be located in the third conductive layer 4. The second capacitor plate C1b of the storage capacitor is electrically connected to one of the first power signal lines VDD through a third via VH3. One of the fifth gate and the fifth drain of the fifth transistor is electrically connected to the data signal line Data through a fourth via.

[0224] Exemplarily, the display substrate 400 includes a first initialization signal line Vinit1, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, a light-emission control signal line EM, and a second initialization signal line Vinit2. The reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the light-emission control signal line EM, and the second initialization signal line Vinit2 are all located in the first conductive layer 3; the first initialization signal line Vinit1 and the third scan signal line GL3 are both located in the third conductive layer 4.

[0225] For example, with reference to Figures 32 and 37, the display substrate 400 further includes a plurality of conductive transition portions 70 located in the second conductive layer 7, wherein the plurality of conductive transition portions 70 include a second conductive transition portion 702, wherein the second conductive transition portion 702 is used to electrically connect one of the first source S1 and the first drain D1 of the first transistor T1 to the first initialization signal line Vinit1; the plurality of conductive transition portions 70 further include a third conductive transition portion 703, wherein the third conductive transition portion 703 is used to electrically connect one of the second source S2 and the second drain D2 of the second transistor T2 to the first node N1; the plurality of conductive transition portions 70 further include a third conductive transition portion 703, wherein the third conductive transition portion 703 is used to electrically connect one of the second source S2 and the second drain D2 of the second transistor T2 to the first node N1; The transition portion 70 further includes a fourth conductive transition portion 704, the fourth conductive transition portion 704 being used to electrically connect the other of the second source S2 and the second drain D2 of the second transistor T2, one of the third source S3 and the third drain D3 of the third transistor T3, the other of the first source S1 and the first drain D1 of the first transistor T1, and one of the sixth source S6 and the sixth drain D6 of the sixth transistor T6 to the third node N3 respectively; the plurality of conductive transition portions 70 further include a fifth conductive transition portion 705, the fifth conductive transition portion 705 being used to electrically connect the fourth source S4 and the fourth drain D6 of the fourth transistor T4 to the third node N3 respectively. The plurality of conductive transition portions 70 further include a sixth conductive transition portion 706, which is used to electrically connect the other of the third source S3 and the third drain D3 of the third transistor T3, the other of the fourth source S4 and the fourth drain D4 of the fourth transistor T4, and one of the fifth source S5 and the fifth drain D5 of the fifth transistor T5 to the second node N2 respectively; the plurality of conductive transition portions 70 further include a seventh conductive transition portion 707, which is used to electrically connect the fifth source S5 and the fifth drain D5 of the fifth transistor T5 to the second node N2 respectively. The other one of D5 is electrically connected to the first power signal line VDD; the multiple conductive transition parts 70 also include an eighth conductive transition part 708, and the eighth conductive transition part 708 is used to electrically connect the other one of the sixth source S6 and the sixth drain D6 of the sixth transistor T6 and one of the seventh source S7 and the seventh drain D7 of the seventh transistor T7 to the fourth node N4 respectively; the multiple conductive transition parts 70 also include a ninth conductive transition part 709, and the ninth conductive transition part 709 is used to electrically connect the other one of the seventh source S7 and the seventh drain D7 of the seventh transistor T7 to the second initialization signal line Vinit2.

[0226] For example, in some embodiments of the present disclosure, the light shielding portion in the display substrate may not include the first power signal line, and is only used to shield a local area in the pixel driving circuit, and the first power signal line may be located in other film layers. For example, the display substrate may include a fifth conductive layer, and the data signal line Data for transmitting the data signal and the first power signal line VDD for transmitting the first power signal may both be arranged in the fifth conductive layer. That is to say, in some embodiments of the present disclosure, it is compatible with the traditional light shielding layer design. By optimizing the connection method of the second gate of the second transistor in the pixel driving circuit, for example, adjusting the film layer where the double gate is located in the second transistor, the first sub-gate G21 of the second transistor is arranged in the first conductive layer 3, and the second sub-gate G22 is arranged in the third conductive layer 4 or the fourth conductive layer 6, the second capacitor plate C1b of the storage capacitor C1 can also be correspondingly arranged in the third conductive layer 4 or the fourth conductive layer 6, thereby eliminating at least one conductive layer, reducing the corresponding metal mask template, and saving costs.

[0227] 41 is a schematic plan view of a pixel driving circuit for a plurality of sub-pixels in a display substrate according to some other embodiments of the present disclosure; and FIG. 42 is a schematic partial cross-sectional view taken along line II′ in FIG. 41 .

[0228] Illustratively, at least some embodiments of the present disclosure further provide a display substrate, referring to FIG. 1 , wherein the display substrate includes: a base substrate 100; and a plurality of sub-pixels SP located on the base substrate, wherein the plurality of sub-pixels SP are arranged in an array on the base substrate 100 along a first direction X and a second direction Y, and at least one sub-pixel SP includes a light-emitting device L and a pixel driving circuit 200 for driving the light-emitting device L to emit light, and the first direction X and the second direction Y intersect.

[0229] For example, in some embodiments of the present disclosure, in combination with reference to Figures 41-42, the display substrate 400 also includes: a first semiconductor layer 2 located on the base substrate; a first conductive layer 3 located on the side of the first semiconductor layer 2 away from the base substrate; a second semiconductor layer 5 located on the side of the first conductive layer 3 away from the base substrate; and a third conductive layer 4 located on the side of the second semiconductor layer 5 away from the base substrate. The pixel driving circuit includes a second transistor T2 and a third transistor T3, the second transistor T2 having a dual-gate structure, and the third transistor T3 having a top-gate structure; the third transistor T3 includes a third active layer ACT3 and a third gate G3, the third active layer ACT3 is located in the first semiconductor layer 2, the third gate G3 is located in the first conductive layer 3, the third active layer ACT3 includes a third channel region CH3, and the orthographic projection of the third gate G3 on the substrate at least partially overlaps with the orthographic projection of the third channel region CH3 on the substrate; and the second transistor T2 includes a second active layer ACT2 and a second gate G2, the second gate G2 includes a first sub-gate G21 and a second sub-gate G22, the first sub-gate G21 is located in the first conductive layer 3, and the second sub-gate G22 is located in the third conductive layer 4, the orthographic projection of the first sub-gate G21 on the substrate at least partially overlaps with the orthographic projection of the second active layer ACT2 on the substrate, and the orthographic projection of the second sub-gate G22 on the substrate at least partially overlaps with the orthographic projection of the second active layer ACT2 on the substrate.

[0230] It should be noted that in some embodiments of the present disclosure, as shown in Figures 41 and 42, the display substrate 400 may not include a light shielding portion, that is, a separate light shielding layer is not required. In this case, there is no need to provide a mask plate for forming the light shielding layer, thereby reducing one masking process. In other embodiments of the present disclosure, the designs shown in Figures 41 and 42 may also include a light shielding portion and are compatible with traditional light shielding layer designs.

[0231] Exemplarily, the display substrate 400 further includes a second conductive layer 7 located on a side of the third conductive layer 4 away from the base substrate; and a fifth conductive layer 8 located on a side of the second conductive layer 7 away from the base substrate. The data signal line Data for transmitting a data signal and the first power signal line VDD for transmitting a first power signal can both be provided in the fifth conductive layer 8. The plurality of data signal lines Data and the plurality of first power signal lines VDD are spaced apart in the first direction, and each of the plurality of data signal lines Data and the plurality of first power signal lines VDD extends along the second direction Y. The light shielding portion 1 in the display substrate may not include the first power signal line and may only be used to shield a local area in the pixel driving circuit of the display substrate. That is, the design of the light shielding layer in at least some embodiments of the present disclosure is compatible with the design of a traditional light shielding layer.

[0232] For example, in some embodiments of the present disclosure, the second transistor may include a dual-gate structure, and the second sub-gate G22 of the second transistor may be further disposed in the fourth conductive layer 6. For example, the display substrate further includes: a first semiconductor layer 2 located on the base substrate; a first conductive layer 3 located on a side of the first semiconductor layer 2 away from the base substrate; a second semiconductor layer 5 located on a side of the first conductive layer 3 away from the base substrate; and a fourth conductive layer 6 located on a side of the second semiconductor layer 5 away from the base substrate. The pixel driving circuit includes a second transistor T2 and a third transistor T3, the second transistor T2 having a dual-gate structure, and the third transistor T3 having a top-gate structure; the third transistor T3 includes a third active layer ACT3 and a third gate G3, the third active layer ACT3 is located in the first semiconductor layer 2, the third gate G3 is located in the first conductive layer 3, the third active layer ACT3 includes a third channel region CH3, and the orthographic projection of the third gate G3 on the substrate at least partially overlaps with the orthographic projection of the third channel region CH3 on the substrate; and the second transistor T2 includes a second active layer ACT2 and a second gate G2, the second gate G2 includes a first sub-gate G21 and a second sub-gate G22, the first sub-gate G21 is located in the first conductive layer 3, and the second sub-gate G22 is located in the fourth conductive layer 6, the orthographic projection of the first sub-gate G21 on the substrate at least partially overlaps with the orthographic projection of the second active layer ACT2 on the substrate, and the orthographic projection of the second sub-gate G22 on the substrate at least partially overlaps with the orthographic projection of the second active layer ACT2 on the substrate.

[0233] By disposing the first sub-gate of the second transistor in the first conductive layer 3 and the second sub-gate of the second transistor in the third conductive layer or the fourth conductive layer, at least one conductive layer can be omitted, which can reduce the corresponding metal mask and save costs. Figure 43 is a schematic diagram of the structure of a display panel according to some embodiments of the present disclosure; Figure 44 is a schematic diagram of the structure of a display device according to some embodiments of the present disclosure.

[0234] 43 , at least some embodiments of the present disclosure further provide a display panel 600. The display panel 600 may include the display substrate 400 as described above.

[0235] 44 , at least some embodiments of the present disclosure further provide a display device 800. The display device 800 includes the display substrate 400 described above or the display panel 600 described above.

[0236] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0237] It should be understood that the display panel and display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate described above. For details, please refer to the above description and will not be repeated here. Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate substrate; A plurality of sub-pixels located on the substrate, the plurality of sub-pixels are arranged in an array on the substrate along a first direction and a second direction, at least one sub-pixel comprises a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; A plurality of signal lines are arranged on the substrate, the plurality of signal lines include a first power signal line, and the first power signal line is used to provide a first power signal to the pixel driving circuit. The display substrate further comprises: a light shielding layer located on the base substrate; a first semiconductor layer located on a side of the light shielding layer away from the base substrate; and a first conductive layer located on a side of the first semiconductor layer away from the base substrate; The pixel driving circuit includes a third transistor, the third transistor includes a third active layer and a third gate, the third active layer is located in the first semiconductor layer, the third gate is located in the first conductive layer, the third active layer includes a third channel region, and an orthographic projection of the third gate on the substrate at least partially overlaps with an orthographic projection of the third channel region on the substrate; and The first power signal line includes a first sub-power signal line located in the light shielding layer, and an orthographic projection of the first sub-power signal line on the base substrate covers an orthographic projection of the third channel region on the base substrate.

2. The display substrate according to claim 1, wherein: The first power signal line further includes a second sub-power signal line located in the light shielding layer, the main body of the first sub-power signal line extends along the first direction, and the second sub-power signal line extends along the second direction; and The display substrate includes m first sub-power signal lines and n second sub-power signal lines located in the light-shielding layer, each of the m first sub-power signal lines respectively crosses with n second sub-power signal lines, so that the portion of the first power signal line located in the light-shielding layer has a grid structure.

3. The display substrate according to claim 1 or 2, wherein: The display substrate further comprises: a second conductive layer located on a side of the first conductive layer away from the base substrate; a planarization layer located on a side of the second conductive layer away from the base substrate; and a first electrode layer located on a side of the planarization layer away from the base substrate; The light emitting element further includes a first electrode, wherein the first electrode is located in the first electrode layer; and The planarization layer includes a first surface facing the second conductive layer and a second surface facing the first electrode layer, the first surface contacts at least a portion of the second conductive layer, and the second surface contacts at least a portion of the first electrode layer.

4. The display substrate according to claim 3, wherein: The pixel driving circuit further includes a storage capacitor, wherein the storage capacitor includes a first capacitor plate and a second capacitor plate; The portion where the first capacitor plate overlaps with the third active layer is the third gate; and The portion of the first power signal line located in the light shielding layer is electrically connected to the second capacitor plate in the display area.

5. The display substrate according to claim 3 or 4, wherein: The display substrate further comprises: a second conductive layer located on a side of the first conductive layer away from the base substrate; The third transistor further includes a third source and a third drain, wherein the third source and the third drain are located in the second conductive layer; and The first power signal line further includes a third sub-power signal line located in the second conductive layer.

6. The display substrate according to claim 5, wherein: An orthographic projection of the third sub-power signal line on the base substrate at least partially overlaps with an orthographic projection of the second sub-power signal line on the base substrate.

7. The display substrate according to claim 6, wherein: The display substrate comprises k third sub-power signal lines located in the second conductive layer; and The number n of the second sub power signal lines is more than twice the number k of the third sub power signal lines.

8. The display substrate according to any one of claims 5 to 7, wherein: The third sub-power signal line is electrically connected to the second sub-power signal line through a first via hole.

9. The display substrate according to claim 3 or 4, wherein: The display substrate further comprises: a second conductive layer located on a side of the first conductive layer away from the base substrate; The third transistor further includes a third source and a third drain, wherein the third source and the third drain are located in the second conductive layer; and The first power signal line further includes a first conductive transition portion located in the second conductive layer, and the first conductive transition portion is electrically connected to the second sub-power signal line through a first via hole.

10. The display substrate according to claim 9, wherein: An orthographic projection of the first conductive transition portion on the base substrate at least partially overlaps with an orthographic projection of the second sub-power signal line on the base substrate.

11. The display substrate according to any one of claims 1 to 10, wherein: The display substrate further comprises: a second semiconductor layer located on a side of the first semiconductor layer away from the base substrate; The pixel driving circuit further includes a second transistor, the second transistor includes a second active layer, and the second active layer is located in the second semiconductor layer; and The first semiconductor layer includes single crystal silicon, amorphous silicon or polycrystalline silicon semiconductor material, and the second semiconductor layer includes oxide semiconductor material.

12. The display substrate according to claim 11, wherein: The second transistor includes a second gate, the second gate includes a first sub-gate and a second sub-gate, the layer where the first sub-gate is located is located on the side of the second semiconductor layer close to the base substrate, the layer where the second sub-gate is located is located on the side of the second semiconductor layer away from the base substrate, the orthographic projection of the first sub-gate on the base substrate at least partially overlaps with the orthographic projection of the second active layer on the base substrate, and the orthographic projection of the second sub-gate on the base substrate at least partially overlaps with the orthographic projection of the second active layer on the base substrate.

13. The display substrate according to claim 12, wherein: The display substrate further comprises: a third conductive layer located between the first semiconductor layer and the second semiconductor layer; and a fourth conductive layer located on a side of the second semiconductor layer away from the base substrate; and The first sub-gate is located in the third conductive layer, and the second sub-gate is located in the fourth conductive layer.

14. The display substrate according to claim 12, wherein: The display substrate further comprises: a third conductive layer located on a side of the second semiconductor layer away from the base substrate; and The first sub-gate is located in the first conductive layer, and the second sub-gate is located in the third conductive layer.

15. The display substrate according to claim 12, wherein: The display substrate further comprises: a fourth conductive layer located on a side of the second semiconductor layer away from the base substrate; and The first sub-gate is located in the first conductive layer, and the second sub-gate is located in the fourth conductive layer.

16. The display substrate according to claim 13 or 14, wherein: At least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the third conductive layer.

17. The display substrate according to claim 15, wherein: At least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the fourth conductive layer.

18. The display substrate according to claim 16 or 17, wherein: A portion of the third sub-power signal line is electrically connected to the second sub-power signal line through a first via hole, and another portion of the third sub-power signal line is electrically connected to at least a portion of the second capacitor plate through a second via hole.

19. The display substrate according to claim 16 or 17, wherein: A portion of the first conductive transition portion is electrically connected to the second sub-power signal line through a first via hole, and another portion of the first conductive transition portion is electrically connected to at least a portion of the second capacitor plate through a second via hole.

20. The display substrate according to claim 11, wherein: The first conductive layer is located on a side of the second semiconductor layer away from the substrate; The second transistor and the third transistor both have a top gate structure; and The second transistor includes a second gate, and the second gate and the third gate are both located in the first conductive layer, the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate.

21. The display substrate according to claim 20, wherein: The display substrate further comprises: a second conductive layer located on a side of the first conductive layer away from the base substrate; and At least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the second conductive layer.

22. The display substrate according to claim 21, wherein: The third sub-power signal line and at least a portion of the second capacitor plate both located in the second conductive layer are connected to each other, and the third sub-power signal line is electrically connected to the second sub-power signal line through a first via hole.

23. The display substrate according to claim 21 or 22, wherein: The second capacitor plate includes a first sub-capacitor plate and a second sub-capacitor plate, the first sub-capacitor plate is located in the second conductive layer, and the second sub-capacitor plate is located in the light shielding layer; and An orthographic projection of each of the first sub-capacitor plate and the second sub-capacitor plate on the base substrate at least partially overlaps with an orthographic projection of the first capacitor plate on the base substrate.

24. The display substrate according to any one of claims 1 to 23, wherein: The pixel driving circuit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; the plurality of signal lines further include a first initialization signal line, a second initialization signal line, a reset signal line, a first scan signal line, a second scan signal line, a third scan signal line, a light emission control signal line and a data signal line, the first initialization signal line, the second initialization signal line, the reset signal line, the first scan signal line, the second scan signal line, the third scan signal line and the light emission control signal line extend along a first direction, and the data signal line extends along a second direction; The first transistor includes a first gate, a first source and a first drain, the first gate is electrically connected to the reset signal line, and one of the first source and the first drain is electrically connected to the first initialization signal line; The second gate is electrically connected to the third scan signal line; The fourth transistor comprises a fourth gate, a fourth source and a fourth drain, the fourth gate is electrically connected to the first scan signal line, and one of the fourth source and the fourth drain is electrically connected to the data signal line; The fifth transistor comprises a fifth gate, a fifth source and a fifth drain, the fifth gate is electrically connected to the light emitting control signal line, and one of the fifth source and the fifth drain is electrically connected to the first power signal line; The sixth transistor comprises a sixth gate, a sixth source and a sixth drain, and the sixth gate is electrically connected to the light emitting control signal line; The seventh transistor comprises a seventh gate, a seventh source and a seventh drain, the seventh gate is electrically connected to the second scan signal line, and one of the seventh source and the seventh drain is electrically connected to the second initialization signal line; as well as One of the second source and the second drain, the third gate and the first capacitor plate are mutually connected The third source and one of the third drain, the other of the fourth source and the fourth drain, and the other of the fifth source and the fifth drain are electrically connected to each other, the first source and the other of the first drain, the other of the second source and the second drain, the other of the third source and the third drain, and one of the sixth source and the sixth drain are electrically connected to each other, and the other of the sixth source and the sixth drain and the other of the seventh source and the seventh drain are electrically connected to each other.

25. A display substrate, wherein: The display substrate comprises: substrate substrate; A plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged in an array on the base substrate along a first direction and a second direction, at least one sub-pixel comprises a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; and A plurality of signal lines are arranged on the substrate, the plurality of signal lines include a first power signal line, and the first power signal line is used to provide a first power signal to the pixel driving circuit. The display substrate further comprises: a light shielding layer located on the base substrate; a first semiconductor layer located on a side of the light shielding layer away from the base substrate; and a first conductive layer located on a side of the first semiconductor layer away from the base substrate; and The first power signal line also includes a first sub-power signal line and a second sub-power signal line located in the light-shielding layer, the main part of the first sub-power signal line extends along the first direction, the second sub-power signal line extends along the second direction, the first sub-power signal line and the second sub-power signal line are electrically connected to each other for transmitting the first power signal.

26. A display substrate, wherein: The display substrate comprises: a substrate substrate; and A plurality of sub-pixels located on the substrate, the plurality of sub-pixels are arranged in an array on the substrate along a first direction and a second direction, at least one sub-pixel comprises a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; The display substrate further comprises: a first semiconductor layer located on the base substrate; a first conductive layer located on a side of the first semiconductor layer away from the base substrate; a second semiconductor layer located on a side of the first conductive layer away from the base substrate; and a third conductive layer located on a side of the second semiconductor layer away from the base substrate. electrical layer; The pixel driving circuit comprises a second transistor and a third transistor, wherein the second transistor and the third transistor both have a top gate structure; The third transistor comprises a third active layer and a third gate, the third active layer is located in the first semiconductor layer, the third gate is located in the first conductive layer, the third active layer comprises a third channel region, and an orthographic projection of the third gate on the substrate at least partially overlaps with an orthographic projection of the third channel region on the substrate; and The second transistor includes a second active layer and a second gate, the second active layer is located in the second semiconductor layer, the second gate is located in the third conductive layer, the second active layer includes a second channel region, and the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projection of the second channel region on the substrate.

27. The display substrate according to claim 26, wherein: The display substrate further comprises a light shielding layer located on a side of the first semiconductor layer close to the base substrate; as well as The display substrate includes a first light-shielding portion and a second light-shielding portion located in the light-shielding layer, wherein an orthographic projection of the first light-shielding portion on the base substrate at least partially overlaps with an orthographic projection of the third channel region on the base substrate, and an orthographic projection of the second light-shielding portion on the base substrate at least partially overlaps with an orthographic projection of the second channel region on the base substrate.

28. The display substrate according to claim 27, wherein: The first light shielding portion includes a first light shielding sub-portion extending along a first direction and a second light shielding sub-portion extending along a second direction, and the first light shielding sub-portion and the second light shielding sub-portion are connected so that the first light shielding portion forms an L-shaped structure; and / or, The second light shielding portion extends from a portion of the first light shielding sub-portion along a second direction.

29. A display substrate, wherein: The display substrate comprises: a substrate substrate; and A plurality of sub-pixels located on the substrate, the plurality of sub-pixels are arranged in an array on the substrate along a first direction and a second direction, at least one sub-pixel comprises a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the first direction and the second direction intersect; Wherein, the display substrate further comprises: a first semiconductor layer located on the base substrate; A first conductive layer located on a side of the semiconductor layer away from the substrate; a second semiconductor layer located on a side of the first conductive layer away from the substrate; a third conductive layer located on a side of the second semiconductor layer away from the substrate; and a fourth conductive layer located on a side of the third conductive layer away from the substrate; The pixel driving circuit comprises a second transistor and a third transistor, the second transistor has a double-gate structure, and the third transistor has a top-gate structure; The third transistor comprises a third active layer and a third gate, the third active layer is located in the first semiconductor layer, the third gate is located in the first conductive layer, the third active layer comprises a third channel region, and an orthographic projection of the third gate on the substrate at least partially overlaps with an orthographic projection of the third channel region on the substrate; and The second transistor includes a second active layer and a second gate, the second gate includes a first sub-gate and a second sub-gate, the first sub-gate is located in the first conductive layer, the second sub-gate is located in the third conductive layer or the fourth conductive layer, the orthographic projection of the first sub-gate on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the orthographic projection of the second sub-gate on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate.

30. A display panel comprising the display substrate according to any one of claims 1-29.

31. A display device comprising the display substrate according to any one of claims 1 to 29 or the display panel according to claim 30.