Generating a hardware description for configuring a digital electronic circuit

Abstract

Generating a hardware description for configuring a digital electronic circuit, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), wherein the hardware description configures the digital electronic circuit to parse input data comprising a sequence of input tokens against an LL(1) grammar. This is achieved by implementing a recursive transition network (RTN) or an augmented transition network (ATN) representing the grammar within the digital electronic circuit. When the grammar defines a data format, such as a JSON schema, XML Schema Definition (XSD), or ASN.1 schema, a document can be validated against the data format by the configured digital electronic circuit processing the document as the input data. The RTN may comprise one or more embedded networks. The RTN may be processed such that the edges of the RTN connecting to an embedded network may be non-input-consuming edges.

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