Stacked field effect transistor structure with independent gate control between top and bottom gates
GB2638597APending Publication Date: 2025-08-27INTERNATIONAL BUSINESS MACHINE CORPORATION
Patent Information
- Application Number
- GB2025004501
- Authority / Receiving Office
- GB · GB
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-10-26
- Filing Date
- 2023-10-23
- Publication Date
- 2025-08-27
Smart Images
Figure 00000000_0000_ABST
Abstract
A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.
Need to check novelty before this filing date? Find Prior Art
Citation Information
Patent Citations
Vertically stacked complementary-FET device with independent gate control
CN110783273A
Vertically stacked complementary-FET device with independent gate control
US10510622B1
Stacked nanosheet rom
US11315938B1
Stacked Nanosheet CFET with Gate All Around Structure
US20210265345A1
Stacked field effect transistor with wrap-around contacts
US20210265348A1